TW519694B - Method for forming MOS transistor with silicide - Google Patents

Method for forming MOS transistor with silicide Download PDF

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TW519694B
TW519694B TW89124594A TW89124594A TW519694B TW 519694 B TW519694 B TW 519694B TW 89124594 A TW89124594 A TW 89124594A TW 89124594 A TW89124594 A TW 89124594A TW 519694 B TW519694 B TW 519694B
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Hung-Huei Tzeng
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Vanguard Int Semiconduct Corp
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Abstract

A method for forming a MOS transistor with silicide at least comprises: providing a silicon substrate; forming a dielectric layer on the silicon substrate, such a dielectric layer at least capable of being used as a gate dielectric layer; forming a polysilicon layer on the dielectric layer, such a polysilicon layer at least capable of being used as a gate conductor layer; performing a pattern transfer step to remove a portion of the polysilicon layer and a portion of the dielectric layer to form a gate structure; forming a spacer on the sidewall of the gate structure; doping a plurality of metal particles to the silicon substrate and the polysilicon layer; performing a thermal treatment to convert at least a portion of the metal particles to a silicide layer; and removing the unreacted portion of the metal particles.

Description

519694 五、發明說明(1) 5 - 1發明領域: 本發明係有關於形成金氧半電晶體的方法,特別是可 以減少副作用與控制金屬矽化物位置之形成金氧半電晶體 的方法。 5 - 2發明背景: 由於金屬石夕化物(s i 1 i c i d e )具有低電阻、财高溫以及 易與多晶矽結合等優點,金屬矽化物已廣泛地被應用在半 導體元件的製程中,例如用來連接金屬内連線與電晶體之 源汲極的一部份或著用來做為閘極之多晶矽化金屬 (po 1 y c i de )的一部份。 習知技藝中形成金屬矽化物的方法可分為兩種:一種 是直接形成金屬矽化物層於底材上;另一種則是先形成金 屬於底材上,再以熱處理程序使金屬與矽反應而生成金屬 矽化物。 前一種方法係讓含有^夕的化合物與含有金屬的化合物 反應以形成金屬矽化物,因此很難避免副產品(by-pro d u c t)與污染 等問題 。舉例 來說, 在以化 學氣相 沉積直 接形成二矽化鎢(WSi 2)時,一般是讓Si Η和WF辰應以形成519694 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a metal oxide semi-electric crystal, particularly a method for forming a metal oxide semi-electric crystal which can reduce side effects and control the position of a metal silicide. 5-2 Background of the Invention: Due to the advantages of low resistance, high temperature, and easy combination with polycrystalline silicon, metal silicides have been widely used in the fabrication of semiconductor devices, such as used to connect metals. Part of the interconnect and source drain of the transistor or part of the polycrystalline silicon silicide (po 1 yci de) used as the gate. There are two methods for forming metal silicide in conventional techniques: one is to directly form a metal silicide layer on the substrate; the other is to first form a metal on the substrate and then react the metal and silicon by a heat treatment process And metal silicide is formed. The former method involves reacting a compound containing metal with a metal-containing compound to form a metal silicide, so it is difficult to avoid problems such as by-produce and pollution. For example, when chemical vapor deposition is used to directly form tungsten disilicon (WSi 2), Si 让 and WF are generally allowed to form.

519694519694

五、發明說明(2) (F)而使得在隨後的 因氟的熱擴散而變 以避免的缺失。 WSi y但此時wSi 2會包含不可忽略的氟 製私(特別是熱程序)中閘極的性能會 壞。換g之’副產品與污染是此方法難 後一種方法係將形成金屬矽化物所需的金 =上士因此整個方法的效率便取決於形成金屬之程文 ,。由於金屬一般都是以物理氣相沉積(physicai H deposition、PVD)(滅鑛、蒸鍍)或化學氣相沉積 chemical vapor dep〇siti〇n, CVD)所形成,而蒸 控制瘵鍍金屬的成份與形成階梯覆蓋性好的金屬,、广不易 能量使用效率不高且形成之金屬的階梯覆蓋性不好錢鍍的 化學氣相沉積又如前所述般難以避免副盥 ,並且 。顯然地,這個作法的效率不高並且不易:確形:,問題 金屬。 &所t的 明顯地,習知技藝之各種形成金屬矽化物的 許多可以改善的空間,因此有必要發展更有效率皆有 更少之形成金屬矽化物方法。 且則作用V. Description of the invention (2) (F) Defects to be avoided due to subsequent thermal diffusion of fluorine. WSi y but at this time wSi 2 will contain non-negligible fluorine (especially thermal program). The gate performance will deteriorate. For g ’s by-products and contamination, this method is difficult. The latter method is the gold required to form a metal silicide = sergeant. Therefore, the efficiency of the entire method depends on the process of forming the metal. Metals are generally formed by physical vapor deposition (PVD) (demineralization, evaporation) or chemical vapor deposition (CVD), and the composition of the metal is controlled by evaporation. With the formation of metal with good step coverage, it is not easy to use energy, the step coverage of the formed metal is not good, and the chemical vapor deposition of the plated metal is difficult to avoid as described above. Obviously, this approach is not efficient and easy: shape: problem metal. Obviously, there are many room for improvement in the formation of metal silicides by various techniques, so it is necessary to develop more efficient methods with fewer metal silicides. And effect

5 - 3發明目的及概述: 種可以有效率地形成金 本發明之主要目的在於提出一 屬石夕化物的方法。5-3 Purpose and summary of the invention: A method for efficiently forming gold The main purpose of the present invention is to propose a method that belongs to the petrochemical industry.

519694 、發明說明(3) 本‘月之另一目的在於提供可以入 程中減少附產品與污染等副作用的方法,屬石夕化物形成過 本發明 氧半電晶體 層在矽底材 形成多晶矽 極導體層; 與部份之介 構的側壁上 執行熱處理 金屬梦化 當然,本發 晶石夕層而已 之 實施例 至少包 介電質 質層上 轉移步 形成閘 數個金 以將至 及移除 擴展到 較佳 的方法, 上,在此 層在介電 執行圖案 電質層以 ;攙雜多 程序,藉 物層;以 明還可以 為一種形 含:提供 層至少可 ,在此多 驟,藉以 極結構; 屬顆粒至 少部份之 未反應之 圖案轉移 成具金屬 矽底材; 作為閘極 晶石夕層至 移除部份 形成間隙 石夕底材與 這些金屬 部份這些 步驟僅移 石夕化物之金 形成介電質 介電質層;' 少可作為閑 之多晶矽層 壁在閘極結 多晶石夕層; 顆粒轉變為 金屬顆粒。 除部份之多 5 - 4發明詳細說明:519694, Description of the invention (3) Another purpose of this month is to provide a method that can reduce side effects such as by-products and pollution during the process. It is a lithium oxide. The oxygen semi-electric crystal layer of the present invention has been formed on the silicon substrate to form a polycrystalline silicon electrode. Conductor layer; metal heat treatment is performed on part of the side wall of the structure. Of course, this embodiment of the spar crystal layer at least includes a step of forming a plurality of gold layers on the dielectric layer to remove and remove it. Extending to a better method, on this layer, the dielectric layer of the pattern is performed on the dielectric; doped with multiple procedures, borrowed layers; the Ming can also be a form: provide the layer at least, in this step, so that Pole structure; at least part of the unreacted pattern of the particles is transferred to a metal silicon substrate; as the gate spar layer to the removed part to form a gap slab substrate and these metal parts these steps only move the slab The gold of the compound forms a dielectric dielectric layer; 'It can be used as a free polycrystalline silicon layer wall at the gate junction polycrystalline layer; the particles are transformed into metal particles. Except for the part 5-4 invention details:

針對習知技術形成金屬矽化物之製程中的各種缺失, 本發明的發明人提出幾個切入點:第一、由於直接形成金 屬石夕化物的作法必須以化學反應形成金屬石夕化物,因此反 應過程產生的副產品與污染是難以避免的,因此總是必須 透過修改反應室或在晶圓形成隔離層(barrier layer)來In view of various defects in the process of forming metal silicide by conventional techniques, the inventor of the present invention proposes several entry points: First, because the method of directly forming metal silicide must form a metal silicide by chemical reaction, so the reaction The by-products and pollution generated by the process are unavoidable, so it is always necessary to modify the reaction chamber or form a barrier layer on the wafer.

519694 五、發明說明(4) 控制反應物/污染的影響。第二、先形成金屬再透過熱處 理以形成金屬矽化物的作法,除了金屬必須能均勻地分佈 在晶圓上以確保金屬矽化物能確實地形成外,還必須能护^ 制金屬穿透至晶圓内的深度以確保金屬矽化物不會影響7 使變壞)位於其下之半導體結構的性質。第三、形成^屬 於晶圓上的方式可以任意地調整,唯一的限制是形成金屬 的品質。 人提出一種形成金氧半電 之佈植方法( 粒(金屬原子或金屬離子: 再進行熱處理程序以形成 應直接形成金屬石夕化物, 生;由於佈植方法可以精 雜能量、攙雜濃度與攙雜 佈進而確保金屬矽化物的 能量使用效率不會如濺鍍 電晶體製程的產出( 根據這幾點,本發明的發明 晶體的方法:先使用技術已成熟 implantation method)將金屬顆 形成在晶圓·表面上(或表層内), 金屬矽化物。由於不是以化學反 因此可以避免副產品與污染的發 確地控制所攙雜之金屬顆粒的纔 方位,因此可確保金屬的均勻分 均勻分佈;再者由於佈植方法的 般低,因此本發明不會導致整個 throughout)下降 〇 本發明之一較佳實施例為一 曰^ 種形成具金屬矽化物之金 乳牛電阳體的方法,至少包含下列步驟: 如第一 A圖所示,提供石夕底材10並形成介電質層邮519694 V. Description of the invention (4) Controlling the influence of reactants / contamination. Second, the method of forming a metal before forming a metal silicide through heat treatment, in addition to the metal must be evenly distributed on the wafer to ensure that the metal silicide can be reliably formed, and the metal must be protected from penetrating to the crystal. Depth inside the circle to ensure that the metal silicide does not affect the properties of the semiconductor structure below it. Third, the method of forming the substrate can be arbitrarily adjusted, and the only limitation is the quality of the formed metal. People proposed a method of implantation to form metal-oxygen semi-electricity (particles (metal atoms or metal ions: further heat treatment procedures to form metal lithotripsy should be directly formed), because the implantation method can refine energy, impurity concentration and impurity The layout further ensures that the energy use efficiency of the metal silicide is not as high as the output of the sputtering transistor process (according to these points, the method of inventing the crystal of the present invention: first using a mature technology implantation method) to form metal particles on the wafer · Metal silicide on the surface (or in the surface layer). Since it is not chemically reversed, by-products and pollution can be avoided to control the position of the mixed metal particles, so it can ensure the uniform distribution of the metal; Because the implantation method is so low, the present invention does not cause the entire through-out to decrease. One preferred embodiment of the present invention is a method for forming a golden cow bovine anode with metal silicide, which includes at least the following steps. : As shown in the first diagram A, the Shixi substrate 10 is provided and a dielectric layer is formed.

第7頁 519694Page 7 519694

少可作為閘極介電質層用 且典型的厚度大約為5"〇埃 五、發明說明(5) 石夕底材1 0上,在此介電質層11至 。介電質層1 1通常為氧化層,並 至3 0 0埃。 如第一 B圖所示,形成多日 在此多晶…2至少可作= "上。 12的典型厚度大約為5〇〇埃至35〇〇埃。曰 冋日守夕晶矽層 如第一 C圖所示,執行一 多晶矽層1 2與部份之介電質層 形成間隙壁1 3在閘極結構的側 圖案轉移步驟,移除部份之 11以形成一閘極結構,然後 壁上。It can be used as a gate dielectric layer, and its typical thickness is about 5 " 0 Angstrom. 5. Description of the invention (5) Shi Xi substrate 10, where the dielectric layers 11 to. The dielectric layer 11 is usually an oxide layer, and is up to 300 angstroms. As shown in the first B diagram, multiple days are formed. Here, at least two polycrystalline silicon can be used as ". A typical thickness of 12 is about 500 to 3500 angstroms. On the following day, as shown in the first C diagram, the polysilicon silicon layer performs a polysilicon layer 12 and a portion of the dielectric layer to form a spacer 13 on the side of the gate structure, and removes part of the pattern. 11 to form a gate structure, and then the wall.

卞十甘° ί — D圖所示,以離子佈植(ion implantation)技 ΐ ΐ二=習知技術,攙雜多數個金屬顆粒14,例如金屬離 則屬原子,至矽底材1 〇。當然,除非用光阻覆蓋,否 、 刀的金屬顆粒1 4也會被攙雜到間隙壁1 3。 粒如第~ Ε圖所示,執行一熱處理程序,藉以使金屬顆 2 1 4與石夕底材1 〇以及多晶矽層1 2此二者反應而形成金屬矽 ^物層1 當然此時未與矽底材1 0或多晶矽層1 2接觸之部 ^金屬顆教1 4並不會形成金屬石夕化物層15(這些未反應之 ,屬顆粒1 4並未晝出以簡化圖示)。一般而言,金屬矽化 f,1 5係為下列之一:二矽化鈦、二矽化鈷、二矽化鎢、 在白 一碎化猛、一碎化组以及二碎化把’並且金屬卞 十 甘 ° As shown in the figure D, ion implantation technology is adopted. Ϊ́2 = the conventional technology, which is doped with a large number of metal particles 14, for example, the metal ion is an atom, up to 10% on the silicon substrate. Of course, unless it is covered with a photoresist, if not, the metal particles 14 of the knife will also be doped to the gap wall 1 3. As shown in Figures ~ E, a heat treatment process is performed to make the metal particles 2 1 4 react with the Shixi substrate 10 and the polycrystalline silicon layer 12 to form a silicon metal layer 1 of course. The parts in contact with the silicon substrate 10 or the polycrystalline silicon layer 12 ^ metal particles 1 14 will not form a metal oxide layer 15 (these unreacted particles 14 are not shown in the day to simplify the illustration). Generally speaking, the metal silicide f, 15 series is one of the following: titanium disilicide, cobalt disilicide, tungsten disilicide, white disintegration, a disintegration group, and disintegration.

第8頁 519694 五、發明說明(6) 矽化物層1 5的種類係取決於金屬顆粒1 4的種類。 隨後的步驟是移除未反應之部份金屬顆粒1 4。藉以避 免在隨後的多重金屬内連線等製程中,發生不正常的短路 等現象。當然,此步驟也可擴展到移除未直接與矽底材接 觸之部份金屬矽化物層1 5。 必須一提的是,第一 C圖至第一 E圖的步驟尚可以修改 為在圖案轉移的步驟中並未移除任何介電質層1 1。如此作 的好處是在隨後的製程中,介電質層1 1可以用來作為隨後 形成之其它結構的一部份,例如作為隨後形成之閘極的閘 極介電質層。 以上所述僅為本發明之較佳實施例而已,並非用以限 定本發明之申請專利範圍;凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾,均應包含在下述之申請 專利範圍内。 «Page 8 519694 V. Description of the invention (6) The type of the silicide layer 15 depends on the type of the metal particles 14. The subsequent step is to remove unreacted portions of the metal particles 14. In order to avoid abnormal short-circuits during subsequent processes such as multi-metal interconnections. Of course, this step can also be extended to remove a portion of the metal silicide layer 15 that is not in direct contact with the silicon substrate. It must be mentioned that the steps from the first C picture to the first E picture can still be modified so that no dielectric layer 11 is removed in the step of pattern transfer. The advantage of this is that in subsequent processes, the dielectric layer 11 can be used as part of other structures that are subsequently formed, such as the gate dielectric layer of the subsequently formed gate. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. «

第9頁 519694 圖式簡單說明 第一 A圖至第一 E圖是本發明一較佳實施例之基本步驟 的橫截面示意圖。 主要部分之代表符號·· 10 矽底材 11 介電質層 12 多晶石夕層 13 間隙璧 14 金屬顆粒 15 金屬矽化物層Page 9 519694 Brief Description of Drawings Figures A through E are schematic cross-sectional views of the basic steps of a preferred embodiment of the present invention. Symbols of the main parts ... 10 Silicon substrate 11 Dielectric layer 12 Polycrystalline layer 13 Gap 14 Metal particles 15 Metal silicide layer

Claims (1)

519694 六、申請專利範圍 1. 形成具金屬矽化物之金氧半電晶體的方法,至少包含: 提供一 ί夕底材; 形成一介電質層在該矽底材上,該介電質層至少可作 為一閘極介電質層; 形成一多晶石夕層在該介電質層上,該多晶石夕層至少可 作為一閘極導體層; 執行一圖案轉移步驟,藉以移除部份之該多晶矽層與 部份之該介電質層以形成一閘極結構; 形成一間隙壁在該閘極結構的側壁上; 攙雜多數個金屬顆粒至該矽底材與該多晶矽層; 執行一熱處理程序,藉以將至少部份之該些金屬顆粒 轉變為一金屬石夕化物層;以及 移除未反應之部份該些金屬顆粒。 2. 如申請專利範圍第1項所述之方法,其中上述之介電質 層為氧化層。 3. 如申請專利範圍第1項所述之方法,其中上述之介電質 層的厚度大約為5 0埃至3 0 0埃。 4. 如申請專利範圍第1項所述之方法,其中上述之多晶矽 層的厚度大約為5 0 0埃至3 5 0 0埃。 5. 如申請專利範圍第1項所述之方法,其中上述之金屬顆519694 6. Application patent scope 1. Method for forming gold-oxygen semi-electric crystal with metal silicide, including at least: providing a substrate; forming a dielectric layer on the silicon substrate, the dielectric layer At least as a gate dielectric layer; forming a polycrystalline layer on the dielectric layer, the polycrystalline layer can be used as at least a gate conductor layer; performing a pattern transfer step to remove it Part of the polycrystalline silicon layer and part of the dielectric layer to form a gate structure; forming a gap wall on the side wall of the gate structure; doping a plurality of metal particles to the silicon substrate and the polycrystalline silicon layer; A heat treatment process is performed to transform at least a portion of the metal particles into a metal oxide layer; and remove an unreacted portion of the metal particles. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned dielectric layer is an oxide layer. 3. The method according to item 1 of the scope of patent application, wherein the thickness of the dielectric layer is about 50 angstroms to 300 angstroms. 4. The method according to item 1 of the scope of patent application, wherein the thickness of the polycrystalline silicon layer is about 500 angstroms to 3 500 angstroms. 5. The method as described in item 1 of the scope of patent application, wherein the above-mentioned metal particles 519694 六、申請專利範圍 粒係為下列之一:金屬離子以及金屬原子。 6. 如申請專利範圍第1項所述之方法,其中上述之金屬顆 粒係以離子佈植技術所攙雜的。 7. 如申請專利範圍第1項所述之方法,其中上述之金屬矽 化物層係為下列之一:二矽化鈦、二矽化鈷、二矽化鎢、 二矽化鉑、二石夕化猛、二矽化钽以及二矽化把。 8. 如申請專利範圍第1項所述之方法,更包含移除未直接 與該矽底材接觸之部份該金屬矽化物層。 9. 一種形成具金屬石夕化物之金氧半電晶體的方法,至少包 含: 提供一矽底材; 形成一介電質層在該矽底材上,該介電質層至少可作 為一閘極介電質層; 形成一多晶石夕層在該介電質層上,該多晶石夕層至少可 作為一閘極導體層; 執行一圖案轉移步驟,藉以移除部份之該多晶矽層以 形成一閘極結構; 形成一間隙壁在該閘極結構的側壁上; 攙雜多數個金屬顆粒至該矽底材與該多晶矽層; 執行一熱處理程序,藉以將至少部份之該些金屬顆粒519694 6. Scope of patent application The grain system is one of the following: metal ions and metal atoms. 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned metal particles are doped with ion implantation technology. 7. The method as described in item 1 of the scope of patent application, wherein the above-mentioned metal silicide layer is one of the following: titanium disilicide, cobalt disilicide, tungsten disilicide, platinum disilicide, two stone dispersants, two Tantalum silicide and disilicide. 8. The method described in item 1 of the patent application scope further comprises removing a portion of the metal silicide layer that is not in direct contact with the silicon substrate. 9. A method for forming a metal oxide semi-transistor with a metal oxide, at least comprising: providing a silicon substrate; forming a dielectric layer on the silicon substrate, the dielectric layer being at least a gate A polar dielectric layer; forming a polycrystalline silicon layer on the dielectric layer, the polycrystalline silicon layer can be used as at least a gate conductor layer; performing a pattern transfer step to remove a portion of the polycrystalline silicon Layer to form a gate structure; forming a gap wall on the side wall of the gate structure; doping a plurality of metal particles to the silicon substrate and the polycrystalline silicon layer; performing a heat treatment process so as to at least part of the metals Granules 第12頁 519694 六、申請專利範圍 轉變為一金屬石夕化物層;以及 移除未反應之部份該些金屬顆粒。 1 0 .如申請專利範圍第9項所述之方法,其中上述之介電質 層為氧化層。 11.如申請專利範圍第9項所述之方法,其中上述之介電質 層的厚度大約為5 0埃至3 0 0埃。 1 2 .如申請專利範圍第9項所述之方法,其中上述之多晶矽 層的厚度大約為5 0 0埃至3 5 0 0埃。 1 3 .如申請專利範圍第9項所述之方法,其中上述之金屬顆 粒係為下列之一:金屬離子以及金屬原子。 1 4.如申請專利範圍第9項所述之方法,其中上述之金屬顆 粒係以離子佈植技術所攙雜的。 1 5 .如申請專利範圍第9項所述之方法,其中上述之金屬矽 化物層係為下列之一:二矽化鈦、二矽化鈷、二矽化鎢、 二矽化鉑、二石夕化猛、二矽化组以及二矽化把。 1 6 .如申請專利範圍第9項所述之方法,更包含移除未直接 與該矽底材接觸之部份該金屬矽化物層。Page 12 519694 VI. Scope of patent application Turning into a metal oxide layer; and removing unreacted part of these metal particles. 10. The method according to item 9 of the scope of patent application, wherein the above-mentioned dielectric layer is an oxide layer. 11. The method according to item 9 of the scope of patent application, wherein the thickness of the dielectric layer is about 50 angstroms to 300 angstroms. 12. The method according to item 9 of the scope of the patent application, wherein the thickness of the polycrystalline silicon layer is about 500 angstroms to 350 angstroms. 13. The method according to item 9 of the scope of patent application, wherein the above-mentioned metal particles are one of the following: metal ions and metal atoms. 1 4. The method according to item 9 of the scope of patent application, wherein the above-mentioned metal particles are doped with ion implantation technology. 15. The method as described in item 9 of the scope of the patent application, wherein the metal silicide layer is one of the following: titanium disilicide, cobalt disilicide, tungsten disilicide, platinum disilicide, two stones, Two silicided groups and two silicided handles. 16. The method according to item 9 of the scope of patent application, further comprising removing a portion of the metal silicide layer that is not in direct contact with the silicon substrate. 第13頁Page 13
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