US20110196638A1 - Test apparatus, information processing system and data transfer method - Google Patents

Test apparatus, information processing system and data transfer method Download PDF

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Publication number
US20110196638A1
US20110196638A1 US12/942,915 US94291510A US2011196638A1 US 20110196638 A1 US20110196638 A1 US 20110196638A1 US 94291510 A US94291510 A US 94291510A US 2011196638 A1 US2011196638 A1 US 2011196638A1
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Prior art keywords
read
control apparatus
test
section
data
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Abandoned
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US12/942,915
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English (en)
Inventor
Kazumoto Tamura
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Advantest Corp
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Advantest Corp
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Priority to US12/942,915 priority Critical patent/US20110196638A1/en
Assigned to ADVANTEST CORPORATION reassignment ADVANTEST CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAMURA, KAZUMOTO
Publication of US20110196638A1 publication Critical patent/US20110196638A1/en
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Definitions

  • the present invention relates to a test apparatus, an information processing system, and a data transfer method for testing a device under test.
  • a test apparatus for testing a semiconductor device or the like includes one or more test units and a control apparatus. Each test unit supplies a test signal to the device under test.
  • the control apparatus can be realized as a computer connected to the test units via a serial communication cable or the like.
  • the control apparatus issues commands to each of the test units to control the test units.
  • the control apparatus when reading data such as test results from a storage apparatus in a test unit, issues a read command to the test unit and receives a response to the read command. After a read command has been issued to the test unit, the control apparatus must be in a standby state not performing other processes until receiving the response to the read command.
  • test units supplying test signals to the devices under test are controlled from remote control apparatuses.
  • the total time from when a control apparatus issues a read command to when the response is received is increased, thereby increasing the processing time of the control apparatus.
  • a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit.
  • the relay apparatus includes a read issuing section that receives a command from the control apparatus and issues a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the test unit; a buffer section that buffers the read data transmitted from the test unit in response to the read command; and a data transmitting section that receives the read command from the control apparatus and sends back the read data buffered in the buffer section.
  • an information processing system comprising a processing unit; a control apparatus that controls the processing unit; and a relay apparatus that relays between the control apparatus and the processing unit.
  • the relay apparatus includes a read issuing section that receives a command from the control apparatus and issues a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the processing unit; a buffer section that buffers the read data transmitted from the processing unit in response to the read command; and a data transmitting section that receives the read command from the control apparatus and sends back the read data buffered in the buffer section.
  • test apparatus that tests a device under test
  • the test apparatus includes a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit.
  • the data transfer method comprises receiving a command from the control apparatus and issuing a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the test unit, by a read issuing section of the relay apparatus; buffering the read data transmitted from the test unit in response to the read command, by a buffer section of the relay apparatus; and receiving the read command from the control apparatus and sending back the read data buffered in the buffer section, by a data transmitting section of the relay apparatus.
  • FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention.
  • FIG. 2 shows configurations of a test unit 12 and the relay apparatus 16 according to the present embodiment.
  • FIG. 3 shows exemplary propagation of a normal read command issued to the test unit 12 by the control apparatus 14 .
  • FIG. 4 shows exemplary propagation of commands when the control apparatus 14 issues commands that are different from the normal commands of FIG. 3 , to read data from the test unit 12 .
  • FIG. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention.
  • the test apparatus 10 tests a device under test such as a semiconductor device.
  • the test apparatus 10 includes one or more test units 12 , a control apparatus 14 , and a relay apparatus 16 .
  • Each test unit 12 sends and receives signals to and from the device under test.
  • each test unit 12 may supply the device under test with a test signal having a waveform corresponding to a test pattern, and judge acceptability of the device under test by comparing a response signal from the device under test to a logic value corresponding to an expected value pattern.
  • the control apparatus 14 provides a command to each of the one or more test units 12 to control the test units 12 .
  • the control apparatus 14 may be realized as a computer that functions as the control apparatus 14 by executing a program.
  • the relay apparatus 16 relays commands and responses between the control apparatus 14 and the one or more test units 12 .
  • one or more transmission lines 22 which each have a length of several meters, may be connected between the control apparatus 14 and one or more relay apparatuses 16 to transmit serial data.
  • a tester bus 24 may be connected between the relay apparatus 16 and the test units 12 to transmit parallel data.
  • FIG. 2 shows configurations of a test unit 12 and the relay apparatus 16 according to the present embodiment.
  • the relay apparatus 16 includes a register 26 , a read issuing section 28 , a first communicating section 30 , a second communicating section 32 , a buffer section 34 , a data transmitting section 36 , and a bus IF section 38 .
  • Data is written to the register 26 according to commands from the control apparatus 14 .
  • data designating an address in a storage apparatus of a test unit 12 is written to the register 26 .
  • the read issuing section 28 receives a command from the control apparatus 14 and issues a read command for reading read data stored in the storage apparatus of the test unit 12 at an address designated by the control apparatus 14 .
  • the read issuing section 28 issues the read command for reading the read data stored at the address indicated by data written in the register 26 , in response to data being written in the register 26 .
  • the first communicating section 30 receives from the control apparatus 14 commands transmitted from the control apparatus 14 to the test unit 12 .
  • the first communicating section 30 receives the read command issued from the read issuing section 28 .
  • the first communicating section 30 generates packets including the received commands.
  • the first communicating section 30 transmits each of the generated packets to the transmission line 22 connected to the test unit 12 that is the transmission destination for the packet, via the bus IF section 38 .
  • the second communicating section 32 receives, via the bus IF section 38 , packets transmitted from the one or more test units 12 .
  • the second communicating section 32 extracts commands or responses to commands transmitted thereto included in the packets.
  • the second communicating section 32 transmits to the control apparatus 14 the extracted commands or responses.
  • the second communicating section 32 After acquiring the read data, which is the response sent from the test unit 12 in response to the read command issued by the read issuing section 28 , the second communicating section 32 writes the read data to the buffer section 34 instead of transmitting the read data to the control apparatus 14 .
  • the buffer section 34 buffers the read data written by the second communicating section 32 .
  • the data transmitting section 36 receives the read command from the control apparatus 14 and sends back the read data buffered in the buffer section 34 .
  • the relay apparatus 16 may include a plurality of buffer sections 34 corresponding to each of a plurality of test units 12 .
  • the buffer sections 34 each buffer the read data transmitted from the corresponding test unit 12 .
  • the data transmitting section 36 reads the read data from the buffer section 34 corresponding to the test unit 12 designated by the read command, and transmits this read data to the control apparatus 14 .
  • the bus IF section 38 converts the data transmitted from the relay apparatus 16 to the test unit 12 , from a format such as parallel data that can be handled by the relay apparatus 16 to a format such as serial data that can be transmitted on the transmission line 22 .
  • the bus IF section 38 also converts data sent from the test unit 12 to the relay apparatus 16 , from a format such as serial data that can be transmitted on the transmission line 22 to a format such as parallel data that can be handled by the relay apparatus 16 .
  • the one or more test units 12 each include a functional testing section 42 , a DC testing section 44 , a bus IF section 46 , and a sending/receiving section 48 .
  • the functional testing section 42 performs functional testing on the device under test.
  • the functional testing section 42 operates according to a command received from the control apparatus 14 .
  • the DC testing section 44 supplies DC power supply voltage to the device under test.
  • the DC testing section 44 performs DC testing on the device under test.
  • the DC testing section 44 operates according to a command from the control apparatus 14 .
  • the bus IF section 46 converts the data transmitted from the test unit 12 to the relay apparatus 16 , from a format such as parallel data that can be handled by the test unit 12 to a format such as serial data that can be transmitted on the transmission line 22 .
  • the bus IF section 46 converts the data transmitted from the relay apparatus 16 to the test unit 12 , from a format such as serial data that can be transmitted on the transmission line 22 to a format such as parallel data that can be handled by the test unit 12 .
  • the sending/receiving section 48 receives, from the relay apparatus 16 via the bus IF section 46 , packets including commands or responses sent from the control apparatus 14 to the test unit 12 .
  • the sending/receiving section 48 extracts the commands or responses included in the packets.
  • the sending/receiving section 48 transmits the extracted commands or responses to the functional testing section 42 or the DC testing section 44 .
  • the sending/receiving section 48 receives commands or responses to be transmitted from the functional testing section 42 and the DC testing section 44 to the control apparatus 14 .
  • the sending/receiving section 48 generates packets including the received commands or responses.
  • the sending/receiving section 48 transmits the generated packets to the relay apparatus 16 via the bus IF section 46 .
  • FIG. 3 shows exemplary propagation of a normal read command issued to the test unit 12 by the control apparatus 14 .
  • commands beginning with “srd” represent read commands for reading data from a designated address in a storage apparatus.
  • the term “TH1 PG” following the “srd” in the read commands represents an address designating the location to read the data from.
  • commands including “DATA” following “srd TH1 PG” represent responses corresponding to the read commands.
  • FIG. 4 uses the same labeling.
  • the read command shown in FIG. 3 is issued by the control apparatus 14 .
  • the read command issued by the control apparatus 14 is sequentially transmitted in the following order: control apparatus 14 ⁇ relay apparatus 16 ⁇ sending/receiving section 48 of the test unit 12 ⁇ functional testing section 42 of the test unit 12 .
  • the functional testing section 42 of the test unit 12 Upon receiving the read command, the functional testing section 42 of the test unit 12 reads the data from the address indicated by the read command, and issues a response that contains the read data.
  • the response issued by the functional testing section 42 of the test unit 12 is sequentially transmitted in the following order: functional testing section 42 of the test unit 12 ⁇ sending/receiving section 48 of the test unit 12 ⁇ relay apparatus 16 ⁇ control apparatus 14 .
  • control apparatus 14 Upon issuing the read command, the control apparatus 14 cannot perform a subsequent process until the response to the read command is received. Accordingly, in the present example, the control apparatus 14 cannot perform processes from time 2 to time 12.
  • FIG. 4 shows exemplary propagation of commands when the control apparatus 14 issues commands that are different from the normal commands of FIG. 3 , to read data from the test unit 12 .
  • the control apparatus 14 of the present embodiment issues commands to the relay apparatus 16 that differ from the normal read command shown in FIG. 3 , reads the data from the test unit 12 , and temporarily holds the data in the relay apparatus 16 . In the present embodiment, this process is referred to as “posted read.”
  • the commands having “swt PRD” at the beginning thereof represent write commands that are issued to the relay apparatus 16 by the control apparatus 14 and that instruct the relay apparatus 16 to perform the posted read.
  • the term “TH1 PG(X)” following the “swt PRD” represents an address designating the location from which data is read according to the posted read.
  • commands including “srd TP Buf” represent read commands for reading data temporarily held by the relay apparatus 16 according to the posted read.
  • the command included in “DATA” following “srd TP Buf” represents a response corresponding to the read command.
  • the control apparatus 14 When the relay apparatus 16 is to perform the posted read, the control apparatus 14 issues a write command to the relay apparatus 16 . In this case, the control apparatus 14 writes data designating an address in a storage apparatus of a test unit 12 to the register 26 .
  • the read issuing section 28 of the relay apparatus 16 generates a normal read command for reading the read data stored at the address indicated by data written in the register 26 , and is triggered by data being written in the register 26 .
  • the first communicating section 30 of the relay apparatus 16 then generates a packet including the read command generated by the read issuing section 28 , and transmits the packet to the corresponding test unit 12 .
  • the sending/receiving section 48 of the test unit 12 receives the read command from the relay apparatus 16 .
  • the sending/receiving section 48 of the test unit 12 supplies the corresponding processing section, i.e. the functional testing section 42 or the DC testing section 44 , with the received read command.
  • the processing section that receives the read command transmits the data stored at the address in the storage apparatus designated by the read command to the sending/receiving section 48 , as read data.
  • the sending/receiving section 48 of the test unit 12 Upon receiving the read data, the sending/receiving section 48 of the test unit 12 generates a packet including the read data and transmits the packet back to the relay apparatus 16 .
  • the second communicating section 32 of the relay apparatus 16 receives the packet including the read data from the test unit 12 .
  • the second communicating section 32 of the relay apparatus 16 extracts the read data from the received packet and writes the read data to the buffer section 34 . In this way, the relay apparatus 16 can read data from the test unit 12 and temporarily hold this data.
  • the control apparatus 14 When reading the read data temporarily held according to the posted read, the control apparatus 14 issues a read command to the relay apparatus 16 .
  • the data transmitting section 36 of the relay apparatus 16 receives the read command from the control apparatus 14 and sends the read data buffered in the buffer section 34 back to the control apparatus 14 .
  • the data transmitting section 36 may receive a confirmation command from the control apparatus 14 and send back status information indicating the buffering status of the read data by the buffer section 34 .
  • the data transmitting section 36 may transmit, as the status information, a flag indicating whether the buffer section 34 is buffering the read data or the number of pieces of read data buffered in the buffer section 34 .
  • the control apparatus 14 can issue read commands to the relay apparatus 16 after confirming that the buffer section 34 is buffering the read data.
  • the data transmitting section 36 may postpone completion of the read command until the read data is buffered in the buffer section 34 .
  • the data transmitting section 36 may postpone the transmission of data in response to the read command received from the control apparatus 14 .
  • the data transmitting section 36 can reliably send the read data back to the control apparatus 14 .
  • control apparatus 14 can read data in a storage apparatus of a test unit 12 without issuing a read command to the test unit 12 . Furthermore, unlike a case in which a read command is issued, the control apparatus 14 can perform a subsequent process immediately after issuing the write command. Accordingly, in the example of FIG. 4 , the control apparatus 14 can perform other processes from time 5 onward. As a result, the test apparatus 10 can efficiently read data from the test unit 12 without having a wait time for the reading of data by the control apparatus 14 .
  • the control apparatus 14 may instruct the relay apparatus 16 to perform the posted read by using a read command instead of the write command. In this case, the control apparatus 14 issues a read command for reading data from the register 26 .
  • the read issuing section 28 may issue a normal read command for reading data from an address in the storage apparatus of a test unit 12 , with the reading of data from the register 26 as a trigger.
  • the technology described via the above embodiments is not limited to use in a test apparatus 10 , and can be applied in a common information processing system.
  • the technology described via the above embodiments can be applied in an information processing system that includes one or more processing units that process information, a control apparatus that controls the processing units, and a relay apparatus that relays between the control apparatus and the processing units.
  • the processing units of the information processing system have the same function and configuration as the test units 12 according to the above embodiments
  • the control apparatus of the information processing system has the same function and configuration as the control apparatus 14 according to the above embodiments
  • the relay apparatus of the information processing system has the same function and configuration as the relay apparatus 16 according to the above embodiments.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Information Transfer Systems (AREA)
US12/942,915 2008-05-30 2010-11-09 Test apparatus, information processing system and data transfer method Abandoned US20110196638A1 (en)

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US12/942,915 US20110196638A1 (en) 2008-05-30 2010-11-09 Test apparatus, information processing system and data transfer method

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US5720608P 2008-05-30 2008-05-30
PCT/JP2008/064347 WO2009144838A1 (ja) 2008-05-30 2008-08-08 試験装置、情報処理システムおよびデータ伝送方法
US12/942,915 US20110196638A1 (en) 2008-05-30 2010-11-09 Test apparatus, information processing system and data transfer method

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US12/945,736 Active 2031-08-24 US8942946B2 (en) 2008-05-30 2010-11-12 Test apparatus and information processing system
US12/945,758 Abandoned US20110208448A1 (en) 2008-05-30 2010-11-12 Test apparatus and information processing system
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US12/945,731 Active 2031-03-30 US8805634B2 (en) 2008-05-30 2010-11-12 Test apparatus and test method

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JP (4) JP4674273B2 (ko)
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TWI615619B (zh) * 2016-06-24 2018-02-21 致伸科技股份有限公司 與受測物通訊之方法以及應用該方法之系統
TWI653519B (zh) * 2017-05-03 2019-03-11 和碩聯合科技股份有限公司 配置單元、檢測系統及檢測方法
CN114968365B (zh) * 2022-07-27 2022-10-28 广州智慧城市发展研究院 适配器寄存器单元及包含其的主机适配器电路

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US20110208448A1 (en) 2011-08-25
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US8942946B2 (en) 2015-01-27
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WO2009144844A1 (ja) 2009-12-03
US8805634B2 (en) 2014-08-12

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