TWI644405B - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TWI644405B TWI644405B TW105133404A TW105133404A TWI644405B TW I644405 B TWI644405 B TW I644405B TW 105133404 A TW105133404 A TW 105133404A TW 105133404 A TW105133404 A TW 105133404A TW I644405 B TWI644405 B TW I644405B
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Abstract
本揭露提供一種半導體結構及其製造方法。半導體結構包括:一基板,包括一第一表面及一第二表面,該第二表面係與該第一表面相對;一接墊,設置在該第一表面上方;一第一保護件,設置在該第一表面上方且部分覆蓋該接墊;以及一重佈線層(redistribution layer,RDL),設置在該第一保護件上方,且包括一導線及一第二保護件,該導線係延伸在該第一保護件上方,該第二保護件係部分覆蓋該導線;其中該導線包括一插塞部以及一焊座部,該插塞部與該接墊耦合且在該第一保護件內朝該接墊延伸,該焊座部延伸在該第一保護件上方,該焊座部包括複數個第一凸出部,向遠離第一保護件之方向凸出。
Description
本發明係關於一種半導體結構,包括在一重佈線層(redistribution layer,RDL)中的導線,複數個凸出部設置至少在該導線的一部分上方且與設置在該導線或環繞該導線之保護件上方之連接件交界。
半導體裝置對於許多現代應用而言是很重要的。隨著電子技術的進展,半導體裝置的尺寸越來越小,功能越來越強大,且整合的電路數量越來越多。由於半導體裝置的尺度微小化,晶圓級晶片尺度封裝(wafer level chip scale packaging,WLCSP)已廣泛地應用於製造半導體裝置。在此等微小半導體裝置內,實施許多製造步驟。
然而,微型化尺度的半導體裝置之製造技術變得越來越複雜。製造半導體裝置的複雜度增加可造成缺陷,例如電互連不良、發生破裂、或元件脫層(delamination)。因此,修飾結構與製造半導體裝置有許多挑戰。上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露提供一種半導體結構,包含:一基板,包括一第一表面及一第二表面,該第二表面係與該第一表面相對;一接墊,設置在該第一表面上方;一第一保護件,設置在該第一表面上方且部分覆蓋該接墊;以及一重佈線層(redistribution layer,RDL),設置在該第一保護件上方,且包括一導線及一第二保護件,該導線係延伸在該第一保護件上方,該第二保護件係部分覆蓋該導線;其中該導線包括一插塞部以及一焊座部,該插塞部與該接墊耦合且在該第一保護件內朝該接墊延伸,該焊座部延伸在該第一保護件上方,該焊座部包括複數個第一凸出部,向遠離該第一保護件之方向凸出。
在本揭露之實施中,該第二保護件暴露該等第一凸出部。
在本揭露之實施中,該半導體結構進一步包含一導電元件,設置在該基板與該導線的該焊座部之間。
在本揭露之實施中,該焊座部包括複數個第二凸出部,朝該基板凸出且被該第一保護件環繞。
在本揭露之實施中,該等第一凸出部係設置在該等第二凸出部上方。
在本揭露之實施中,該等第一凸出部係分別垂直對準該等第二凸出部。
在本揭露之實施中,該等第一凸出部係分別插置在該等第二凸出部之間。
在本揭露之實施中,該半導體結構進一步包含一連接件,設置在該焊座部上方。
在本揭露之實施中,該連接件係與該等第一凸出部交界。
在本揭露之實施中,該等第一凸出部係凸伸至該連接件中。
在本揭露之實施中,該等第一凸出部係被該第二保護件環繞。
本揭露另提供一種半導體結構之製造方法,包含:提供一基板;設置一接墊在該基板上方;設置一第一保護件在該基板上方,以部分覆蓋該接墊;設置一導電材料在該第一保護件及該接墊上方,以形成一電連接至該接墊之導線;設置一第二保護件在該第一保護件上方,以部分覆蓋該導線;以及形成複數個第一凸出部在該第二保護件暴露出之導線上方。
在本揭露之實施中,該等第一凸出部係藉由蝕刻、雷射剝蝕、鑽孔或電鍍製程形成。
在本揭露之實施中,該製造方法進一步包含:設置一圖案化遮罩在該導線上方,該圖案化遮罩包括複數個開口;設置該導電材料在該等開口內,以形成該等第一凸出部;以及移除該圖案化遮罩。
在本揭露之實施中,該製造方法進一步包含:設置一圖案化遮罩在該第一保護件上方,該圖案化遮罩包括複數個開口;部分移除該圖案化遮罩暴露出之該第一保護件,以形成複數個凹槽在該第一保護件上方;移除該圖案化遮罩;以及設置該導電材料在該等凹槽內,以形成複數個從該導線朝該基板凸出之第二凸出部。
在本揭露之實施中,該製造方法進一步包含設置一連接件在該第二保護件暴露出且環繞該等第一凸出部之導線上方。
在本揭露之實施中,該導電材料係藉由電鍍或濺鍍製程形成。
在本揭露之實施中,該製造方法進一步包含設置一導電件在該基板上方。
本揭露另提供一種半導體結構,包含:一基板,包括一導電通路;一第一保護件,設置在該基板上方且暴露該導電通路的一部分;一導線,設
置在該第一保護件上方且電連接至該導電通路;以及一第二保護件,設置在該導線上方且暴露該導線的一部分;其中該第二保護件暴露出之該導線的該部分包括複數個第一凸出部,該等第一凸出部係向遠離該第一保護件之方向凸出。
在本揭露之實施中,該導線包括複數個第二凸出部,該等第二凸出部係向該基板凸出且被該第一保護件環繞。
本揭露提供之半導體結構包括一導線,設置在一重佈線層(RDL)中。該導線係被一保護件環繞,且包括一焊座部,經配置以接收一連接件。該焊座部包括複數個從該導線凸出之凸出部,其中該等凸出部經配置以改善在該導線與該連接件之間的黏著或在該導線與該保護件之間的黏著。該等凸出部也可以緩解在該導線上方、在該半導體結構內部或在製程中產生的應力。因此,本揭露之技術可最小化或防止該半導體結構之元件脫層(delamination)及在該半導體結構中產生之裂痕,因而改善該半導體結構的可靠性。
100‧‧‧半導體裝置
101‧‧‧基板
101a‧‧‧第一表面
101b‧‧‧第二表面
102‧‧‧接墊
102a‧‧‧暴露部分
103‧‧‧導電元件
104‧‧‧第一保護件
104a‧‧‧第一孔洞
104b‧‧‧凹槽
105‧‧‧重佈線層
105a‧‧‧導線
105b‧‧‧第二保護件
105c‧‧‧插塞部
105d‧‧‧焊座部
105e‧‧‧第一凸出部
105f‧‧‧第二孔洞
105g‧‧‧第二凸出部
106‧‧‧連接件
107‧‧‧導電通路
107a‧‧‧暴露部分
200‧‧‧半導體裝置
300‧‧‧方法
301‧‧‧步驟
302‧‧‧步驟
303‧‧‧步驟
304‧‧‧步驟
305‧‧‧步驟
306‧‧‧步驟
307‧‧‧步驟
308‧‧‧步驟
309‧‧‧步驟
310‧‧‧步驟
311‧‧‧步驟
312‧‧‧步驟
401‧‧‧第一圖案化遮罩
401a‧‧‧第一開口
402‧‧‧第二圖案化遮罩
402a‧‧‧第二開口
A‧‧‧區域
D‧‧‧距離
參閱詳細說明與申請專利範圍結合考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1係一剖面示意圖,例示本揭露實施例之半導體裝置。
圖2係一剖面示意圖,例示半導體結構包含複數個第二凸出部。
圖3係一剖面示意圖,例示本揭露實施例之半導體結構。
圖4係一剖面示意圖,例示本揭露實施例之半導體結構。
圖5係一剖面示意圖,例示本揭露實施例之半導體結構。
圖6係一剖面示意圖,例示本揭露實施例之半導體結構。
圖7至圖9係圖1之區域A的放大圖,例示各種構形之第一凸出部。
圖10係一剖面示意圖,例示本揭露實施例之半導體結構。
圖11係一流程圖,例示本揭露實施例之半導體結構的製造方法。
圖12至圖28係剖面示意圖,例示本揭露實施例之半導體結構的製造方法。
本揭露之下面說明係伴隨附圖,其等係併入本說明書中並構成本說明書的一部分,且繪示出本揭露的實施例,但本揭露並不限於該等實施例。此外,可適當地整合下面實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在本揭露之實施例中」一語並非必須指相同實施例,然而可為相同實施例。
本揭露提供一種半導體結構,包括在一重佈線層(RDL)中之導線,複數個凸出部設置至少在該導線的一部分上方,以改善該導線與該半導體結構的其它元件(例如,連接件、保護件或類似物)之間的黏著或緩解在該半導體結構上方之應力。為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
半導體結構包括複數個堆疊在上方且彼此交界之元件。例如,連接件(諸如凸塊、柱、一桿或類似物)係設置在導線的一部分上方且與該導線的該部分耦合,或該導線係設置在一保護件上方。由於元件包括不同種類的材料,在元件之間的黏著可能不足;因此,可能發生元件脫層或元件之間的不良電連接。又者,一旦設置該連接件在該導線上方,應力或力係作用在該導線上方且可能對該連接件與該導線以及對該導線下方元件造成傷害。因此,可能在該連接件或該導線中產生出裂痕,可能甚至延伸到該導線下方的元件。
本揭露提供一種半導體結構,包括一導線,設置在一重佈線層(RDL)中。該導線係被一保護件環繞,且包括一焊座部,經配置以接收一連接件。該焊座部包括複數個從該導線凸出之凸出部,其中該等凸出部經配置以改善在該導線與該連接件之間的黏著或在該導線與該保護件之間的黏著。該等凸出部也可以緩解在該導線上方、在該半導體結構內部或在製程中產生的應力。因此,本揭露之技術可最小化或防止該半導體結構之元件脫層(delamination)及在該半導體結構中產生之裂痕,因而改善該半導體結構的可靠性。
圖1係一剖面示意圖,例示本揭露實施例之半導體裝置100。在本揭露之實施例中,半導體結構100包括基板101、接墊102、一個或多個導電元件103、第一保護件104、重佈線層(RDL)105及連接件106。在本揭露之實施例中,半導體結構100係晶粒、晶片或半導體封裝件的一部分。
在本揭露之實施例中,基板101具有預定的功能電路。在本揭露之實施例中,基板101包含數個導電線以及由該等導電線連接的數個電子元件,例如電晶體與二極體。在本揭露之實施例中,基板101為半導體基板。在本
揭露之實施例中,基板101係晶圓。在本揭露之實施例中,基板101包含半導體材料,例如矽、鍺、鎵、砷、以及其組合。在本揭露之實施例中,基板101為矽基板。在本揭露之實施例中,基板101包含例如陶瓷、玻璃、或類似物之材料。在本揭露之實施例中,基板101為玻璃基板。在本揭露之實施例中,基板101係四邊形、矩形、正方形、多邊形、或任何其他合適的形狀。
在本揭露之實施例中,基板101包含第一表面101a以及與第一表面101a相對的第二表面101b。在本揭露之實施例中,第一表面101a為正面或是主動面,其中電路或電子元件係設置第一表面101a上。在本揭露之實施例中,第二表面101b為背面或是非主動面(inactive side)。
在本揭露之實施例中,接墊102係位於基板101上方。在本揭露之實施例中,接墊102係位於基板101的第一表面101a上方或是基板101的第一表面101a內。在本揭露之實施例中,接墊102係位於基板101的第二表面101b上方。在本揭露之實施例中,接墊102係電連接至基板101中的電路或電子元件。在本揭露之實施例中,接墊102電連接基板101外部的電路,因而基板101中的電路可經由接墊102而電連接至基板101外部的電路。在本揭露之實施例中,接墊102係經配置以接收導電結構。在本揭露之實施例中,接墊102為晶粒接墊或是接合接墊。在本揭露之實施例中,接墊102包含金、銀、銅、鎳、鎢、鋁、鈀、與/或其合金。
在本揭露之實施例中,第一保護件104係設置在基板101及接墊102的週邊上方。在本揭露之實施例中,第一保護件104係部分覆蓋接墊102;因此,第一保護件104暴露接墊102的暴露部分102a。在本揭露之實施例中,第一保護件104係環繞接墊102。在本揭露之實施例中,第一保護件104經
配置以提供基板101電氣絕緣及溼氣保護,以便基板101與周圍環境隔離。
在本揭露之實施例中,一個或更多導電元件103係設置在基板101上方。在本揭露之實施例中,導電元件103係設置在基板101的第一表面101a上方。在本揭露之實施例中,導電元件103係電連接至基板101中的電路或電氣元件。在本揭露之實施例中,導電元件103係在基板101上方延伸。在本揭露之實施例中,導電元件103係相鄰於接墊102。在本揭露之實施例中,導電元件103係彼此相鄰。在本揭露之實施例中,導電元件103係彼此平行配置。在本揭露之實施例中,導電元件103係以固定距離(節距)彼此間隔。
在本揭露之實施例中,導電元件103係導電線、金屬線、導電接墊、導電柱、導電層或類似物。在本揭露之實施例中,導電元件103包括銅、金、銀、鎳、焊料、錫、鉛、鎢、鋁、鈦、鈀及/或其合金。
在本揭露之實施例中,第一保護件104係設置在基板101上方。在本揭露之實施例中,第一保護件104係設置在基板101的第一表面101a上方。在本揭露之實施例中,第一保護件104係覆蓋導電元件103且部分覆蓋接墊102。在本揭露之實施例中,第一保護件104暴露接墊102的一部分。在本揭露之實施例中,第一保護件104包括第一孔洞104a,設置在接墊102上方且暴露接墊102的暴露部分102a。在本揭露之實施例中,接墊102的暴露部分102a經配置以接收導電結構或電連接至基板101外部之電路。
在本揭露之實施例中,第一保護件104包括單一膜層的介電材料或數層彼此堆疊之介電材料。在本揭露之實施例中,第一保護件104係以介電材料形成,諸如氧化矽、氧氮化矽、氮化矽、聚合物、聚醯亞胺、聚苯并噁唑(polybenzoxazole,PBO)、聚醯亞胺-吲哚喹唑啉二酮(polyimide-iso-indroquinazalinedione,PIQ)或類似物。
在本揭露之實施例中,重佈線層105係設置在第一保護件104上方。在本揭露之實施例中,重佈線層105包括導線105a以及第二保護件105b,導線105a在第一保護件104上方延伸;,第二保護件105b部分覆蓋導線105a。在本揭露之實施例中,重佈線層105來自接墊102之路徑重新佈線,以便重新分佈基板101的輸入輸出(input/output,I/O)端。
在本揭露之實施例中,導線105a係設置在第一保護件104上方且與第一保護件104共形。在本揭露之實施例中,導線105a係電連接至接墊102或基板101。在本揭露之實施例中,導線105a包括導電材料,諸如金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。
在本揭露之實施例中,導線105a包括插塞部105c以及焊座部105d,插塞部105c與接墊102耦合,焊座部105d設置在導電元件103之至少一者上方。在本揭露之實施例中,插塞部105c係設置在接墊102上方。在本揭露之實施例中,插塞部105c係在第一保護件104內朝接墊102延伸。在本揭露之實施例中,插塞部105c係朝接墊102延伸通過第一保護件104的一部分。在本揭露之實施例中,插塞部105c係設置在接墊102上方且電連接至接墊102。在本揭露之實施例中,插塞部105c係與第一保護件104暴露出之接墊102的暴露部分102a耦合。
在本揭露之實施例中,插塞部105c係在第一保護件104上方延伸。在本揭露之實施例中,焊座部105d係透過插塞部105c電連接至接墊102。在本揭露之實施例中,焊座部105d係經配置以接收導電結構或透過插塞部105c或接墊102電連接至基板101外部之電路。
在本揭露之實施例中,第二保護件105b係設置在第一保護件104上方。在本揭露之實施例中,導線105a係被第二保護件105b環繞。在本揭露之
實施例中,第二保護件105b係暴露導線105a的一部分。在本揭露之實施例中,插塞部105c係設置在第二保護件105b內或被第二保護件105b覆蓋,且第二保護件105b暴露焊座部105d。在本揭露之實施例中,第二保護件105b包括第二孔洞105f,設置在焊座部105d上方且至少部分暴露焊座部105d。
在本揭露之實施例中,第二保護件105b包括單一膜層的介電材料或數層彼此堆疊之介電材料。在本揭露之實施例中,第二保護件105b係以介電材料形成,諸如氧化矽、氧氮化矽、氮化矽、聚合物、聚醯亞胺、聚苯并噁唑(PBO)、聚醯亞胺-吲哚喹唑啉二酮(PIQ)或類似物。
在本揭露之實施例中,焊座部105d包括複數個第一凸出部105e,從焊座部105d向遠離第一保護件104之方向凸出。在本揭露之實施例中,第一凸出部105e向上設置在焊座部105d上方。在本揭露之實施例中,第一凸出部105e係與焊座部105d正交地延伸。在本揭露之實施例中,第一凸出部105e係被第二保護件105b環繞。在本揭露之實施例中,第二保護件105b暴露第一凸出部105e。
在本揭露之實施例中,第一凸出部105e係設置在導電元件103之一者上面或對準導電元件103之一者。在本揭露之實施例中,第一凸出部105e係不對準導電元件103之任一者。在本揭露之實施例中,第一凸出部105e係設置在兩個相鄰導電元件103上方且之間。在本揭露之實施例中,第一凸出部105e係以固定或不固定距離彼此間隔。在本揭露之實施例中,第一凸出部105e係彼此在相等高度或彼此在不同高度。
在本揭露之實施例中,第一凸出部105e的一垂直截面(從圖1所示的視角)係呈一長方形、四邊形或多邊形形狀。在本揭露之實施例中,第一凸出部105e的該垂直截面係呈一錐狀構形。在本揭露之實施例中,第一凸出部
105e的一水平截面(從半導體結構100的俯視圖)係呈一長方形、四邊形、圓形或多邊形形狀。
在本揭露之實施例中,連接件106係設置在焊座部105d上方。在本揭露之實施例中,連接件106與第一凸出部105e交界。在本揭露之實施例中,第一凸出部105e係凸伸至連接件106中。在本揭露之實施例中,第一凸出部105e係被連接件106環繞。在本揭露之實施例中,連接件106係電連接至焊座部105d。在本揭露之實施例中,連接件106係從焊座部105d或第二保護件105b凸出。在本揭露之實施例中,連接件106係至少部分被第二保護件105b環繞或係至少部分設置在第二孔洞105f內。在本揭露之實施例中,接墊106經配置以與導電結構、晶片或封裝件接合。
在本揭露之實施例中,連接件106係呈圓柱狀、球形或半球形形狀。在本揭露之實施例中,連接件106係焊料接合、焊料凸塊、焊球、球柵陣列(BGA)球、受控的塌陷晶片連接(C4)凸塊、微凸塊、或類似物。在本揭露之實施例中,凸塊104為導電柱或桿。
在本揭露之實施例中,焊座部105d包括從焊座部105d凸出之第一凸出部105e。當連接件106係設置在焊座部105d上方時,第一凸出部105e經配置以改善在焊座部105d與連接件106之間的黏著,或緩解在導線105a上方之應力。因此,可最小化或防止導線105a的脫層或在連接件106、導線105a、第一保護件104或第二保護件內發展出裂痕105b。
圖2係一剖面示意圖,例示半導體結構200包含複數個第二凸出部105g。在本揭露之實施例中,半導體結構200包括基板101、接墊102、導電元件103、第一保護件104、重佈線層105及連接件106,具有上文所述或圖1中所繪示者相似之構形。在本揭露之實施例中,半導體結構200包括從焊座
部105d向基板101或第一保護件104凸出之第二凸出部105g。
在本揭露之實施例中,第一保護件104包括複數個凹槽104b,朝基板101凹陷進入第一保護件104中。在本揭露之實施例中,凹槽104b係設置在導電元件103之至少一者上方。
在本揭露之實施例中,焊座部105d包括第一凸出部105e以及第二凸出部105g,第一凸出部105e向連接件106凸出,第二凸出部105g向第一保護件104凸出。在本揭露之實施例中,第一凸出部105e係設置在第二凸出部105g上方。在本揭露之實施例中,焊座部105d係呈一波紋或波浪形狀。在本揭露之實施例中,第二凸出部105g係從焊座部105d向基板101凸出進入到第一保護件104中且被第一保護件104環繞。在本揭露之實施例中,第二凸出部105g係分別設置在凹槽104b內。在本揭露之實施例中,第二凸出部105g係設置在導電元件103之至少一者上方。在本揭露之實施例中,第二凸出部105g係與焊座部105d正交地延伸。
在本揭露之實施例中,第二凸出部105g的垂直截面(從如圖2所示的視角)係呈長方形、四邊形或多邊形。在本揭露之實施例中,第二凸出部105g的垂直截面係呈錐狀構形。在本揭露之實施例中,第一凸出部105e的水平截面(從半導體結構100的底視圖)係呈長方形、四邊形、圓形或多邊形形狀。在本揭露之實施例中,第二凸出部105g係以固定或不固定距離彼此間隔。在本揭露之實施例中,第二凸出部105g係彼此在相等高度或彼此在不同高度。
在圖2所示之實施例中,第一凸出部105e係插置在第二凸出部105g之間。在本揭露之實施例中,第一凸出部105e係不對準第二凸出部105g。
在本揭露之實施例中,如圖3所示,第一凸出部105e係分別垂直對準
第二凸出部105g。在本揭露之實施例中,第一凸出部105e係與對應第二凸出部105g相對設置。
在本揭露之實施例中,如圖4所示,部分第一凸出部105e係對準對應部分第二凸出部105g,同時部分第一凸出部105e係不對準對應部分第二凸出部105g。
在本揭露之實施例中,第二凸出部105g係設置在導電元件103之一者上面。在本揭露之實施例中,在第二凸起部105g與導電元件103之間的距離D係實質上大於零。在本揭露之實施例中,距離D係實質上大於1μm。
在本揭露之實施例中,如圖5所示,第二凸出部105g係不垂直對準導電元件103。在本揭露之實施例中,第二凸出部105g係不對準導電元件103之任一者。在本揭露之實施例中,第二凸出部105g係設置在兩個相鄰導電元件103上面且之間。
在本揭露之實施例中,如圖6所示,第二凸出部105g係垂直對準導電元件103。在本揭露之實施例中,第二凸出部105g係對準導電元件103之一者。
圖7至圖9係圖1之區域A的放大圖,例示各種構形之第一凸出部105e。在本揭露之實施例中,如圖7所示,第一凸出部105e係以實質上平行於導電元件103之方向上延伸。在本揭露之實施例中,如圖8所示,第一凸出部105e係以實質上與導電元件103正交之方向上延伸。在本揭露之實施例中,如圖9所示,第一凸出部105e係相對於導電元件103以預定角度之方向上延伸。在本揭露之實施例中,預定角度約1°至89°。在本揭露之實施例中,第一凸出部105e係延伸相同距離或不同距離。在本揭露之實施例中,第一凸出部105e係相等長度或不同長度。
圖10係一剖面示意圖,例示本揭露另一實施例之半導體裝置200。在本揭露之實施例中,半導體結構200包括基板101、導電通路107、第一保護件104、重佈線層(RDL)105及連接件106。在本揭露之實施例中,基板101、第一保護件104、重佈線層(RDL)105及連接件106具有上文所述或圖1至圖9之任一所繪示者相似之構形。在本揭露之實施例中,導電通路107係延伸通過基板101。在本揭露之實施例中,第一保護件104係設置在基板101上方。在本揭露之實施例中,第一保護件104暴露導電通路107的暴露部分107a。在本揭露之實施例中,重佈線層105係設置在基板101上方。在本揭露之實施例中,重佈線層105係設置在基板101的第二表面101b上方。在本揭露之實施例中,重佈線層105的導線105a係設置在第一保護件104上方且電連接至導電通路107。在本揭露之實施例中,重佈線層105的第二保護件105b係設置在導線105a上方且暴露導線105a的一部分。在本揭露之實施例中,第二保護件105b暴露之導線105a的部分包括複數個第一凸出部105e,向遠離第一保護件104之方向凸出。在本揭露之實施例中,導線105a包括複數個第二凸出部105g,向基板101凸出且被第一保護件104環繞。
本揭露亦提供一種半導體結構(100或200)之製造方法。在本揭露之實施例中,半導體結構(100或200)可藉由一圖11之流程圖所示之方法300形成。方法300包含一些操作,描述與說明,不應被視為操作順序的限制。方法300包含一些步驟(301、302、303、304、305、306、307、308、309、310、311及312)。
在步驟301中,如圖12所示提供或接收基板101。在本揭露之實施例中,基板101係包括第一表面101a及第二表面101b,第二表面101b係與第一表面101a相對。在本揭露之實施例中,基板101包括複數個導電線及複數
個藉由該等導電線連接之電氣元件,諸如電晶體及二極體。在本揭露之實施例中,基板101係半導體基板。在本揭露之實施例中,第一基板101包括矽、鍺、鎵、砷、及其組合。在本揭露之實施例中,基板101係矽基板。在本揭露之實施例中,基板101包括延伸通過基板101之導電通路。在本揭露之實施例中,該導電通路具有上文所述或圖10中所繪示之導電通路107相似之構形。在本揭露之實施例中,基板101具有上文所述或圖1至圖10之任一所繪示者相似之構形。
在步驟302中,如圖13所示,設置接墊102在基板101上方。在本揭露之實施例中,接墊102係設置在基板101的第一表面101a上方。在本揭露之實施例中,接墊102係電連接至基板101中的電路。在本揭露之實施例中,接墊102經配置以接收導電結構。在本揭露之實施例中,接墊102係晶粒接墊或接合接墊。在本揭露之實施例中,接墊102包括金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。在本揭露之實施例中,接墊102係藉由電鍍或任何其它合適的製程形成。在本揭露之實施例中,接墊102係具有上文所述或圖1至圖9之任一所繪示者相似之構形。在本揭露之實施例中,當基板101內部具有延伸通過基板101之導電插塞時,接墊102則被省略。
在本揭露之實施例中,如圖14所示,設置複數個導電元件103在基板101上方。在本揭露之實施例中,導電元件103係設置在基板101的第一表面101a上方。在本揭露之實施例中,導電元件103係導電線、金屬線或類似物。在本揭露之實施例中,導電元件103包括金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。在本揭露之實施例中,導電元件103係藉由光微影、蝕刻、濺鍍、電鍍或任何其它合適的製程形成。在本揭露之實施例中,導電元件103係具有上文所述或圖1至圖9之任一所繪示者相似之構形。
在步驟303中,如圖15所示,設置第一保護件104在基板101上方。在本揭露之實施例中,第一保護件104係覆蓋導電元件103及接墊102。在本揭露之實施例中,第一保護件104係以介電材料形成,諸如氧化矽、氧氮化矽、氮化矽、聚合物、聚醯亞胺、PBO、PIQ或類似物。在本揭露之實施例中,第一保護件104係藉由化學氣相沉積(chemical vapor deposition,CVD)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、旋轉塗佈或任何其它合適的製程形成。在本揭露之實施例中,第一保護件104係具有上文所述或圖1至圖10之任一所繪示者相似之構形。
在步驟304中,如圖16所示,設置第一圖案化遮罩401在第一保護件104上方。在本揭露之實施例中,第一圖案化遮罩401係藉由下列製程形成:設置光阻(photoresist,PR)在第一保護件104上方,再部分移除光阻以形成複數個第一開口401a。在本揭露之實施例中,光阻係藉由沉積或任何其它合適的製程形成。在本揭露之實施例中,光阻係藉由光微影、蝕刻或任何其它合適的製程予以部分移除。在本揭露之實施例中,第一圖案化遮罩401暴露第一保護件104的複數個部分。
在步驟305中,如圖17所示,部分移除第一圖案化遮罩401暴露之第一保護件104,以在第一保護件104上方形成複數個凹槽104b。在本揭露之實施例中,在第一開口401a下方之第一保護件104被部分移除。在本揭露之實施例中,第一圖案化遮罩401暴露之第一保護件104係藉由蝕刻或任何其它合適的製程予以移除。在本揭露之實施例中,凹槽104b具有上文所述或圖2至圖6之任一所繪示者相似之構形。
在步驟306中,如圖18所示,移除第一圖案化遮罩401。在本揭露之
實施例中,第一圖案化遮罩401係藉由蝕刻、剝除或任何其它合適的製程移除。
在步驟307中,如圖19所示,設置一導電材料在凹槽104b內,以形成複數個第二凸出部105g。在本揭露之實施例中,第二凸出部105g係向基板101凸出到第一保護件104中。在本揭露之實施例中,導電材料係藉由金屬填充、電鍍、濺鍍或任何其它合適的製程形成。在本揭露之實施例中,導電材料係設置在第一保護件104上方且在凹槽104b內;之後,在第一保護件104上方之導電材料係藉由化學機械研磨(chemical mechanical polish,CMP)或任何其它合適的製程予以移除。在本揭露之實施例中,導電材料包括金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。在本揭露之實施例中,第二凸出部105g具有上文所述或圖2至圖6之任一所繪示者相似之構形。
在步驟308中,如圖20所示,部分移除在接墊102上方之第一保護件104,以形成第一孔洞104a並部分暴露接墊102。在本揭露之實施例中,第一孔洞104a係藉由下列製程形成:設置光阻(PR)在第一保護件104上方,再將光阻暴露之第一保護件104予以部分移除。在本揭露之實施例中,第一保護件104暴露之接墊102的部分經配置以接收導電結構。在本揭露之實施例中,第一孔洞104a係具有上文所述或圖1至圖6之任一所繪示者相似之構形。在本揭露之實施例中,當導電通路上方之第一保護件104被部分移除時,第一保護件104部分暴露基板101的導電通路。在本揭露之實施例中,第一保護件104暴露之導電通路的部分經配置以接收導電結構。
在步驟309中,如圖21所示,設置導電材料在第一保護件104及接墊102上方,以形成導線105a。在本揭露之實施例中,導線105a係電連接至接墊102。在本揭露之實施例中,導電材料係設置在第一保護件104暴露之
導電通路的暴露部分上方,以形成導線105a,電連接至導電通路。在本揭露之實施例中,導電材料係藉由濺鍍、電鍍或任何其它合適的製程形成。在本揭露之實施例中,第二凸出部105g係從導線105a向基板101凸出。在本揭露之實施例中,導電材料包括金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。
在步驟310中,如圖22所示,設置第二保護件105b在第一保護件104上方,以部分覆蓋導線105a。在本揭露之實施例中,第二保護件105b係以介電材料形成,諸如氧化矽、氧氮化矽、氮化矽、聚合物、聚醯亞胺、PBO、PIQ或類似物。在本揭露之實施例中,第二保護件105b係藉由化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、旋轉塗佈或任何其它合適的製程形成。在本揭露之實施例中,第二保護件105b被部分移除以形成第二孔洞105f並部分暴露導線105的焊座部105d或焊座部105d。在本揭露之實施例中,第二孔洞105f係藉由下列製程形成:設置光阻(PR)在第二保護件105b上方;之後,部分移除在焊座部105d上方之光阻及第二保護件105b。在本揭露之實施例中,第二凸出部105b及第二孔洞105f係具有上文所述或圖1至圖10之任一所繪示者相似之構形。
在步驟311中,如圖23至圖26所示,形成複數個第一凸出部105e在第二保護件105b暴露之導線105上方。在本揭露之實施例中,第一凸出部105e具有上文所述或圖1至圖10之任一所繪示者相似之構形。
在圖23所示之實施例中,第一凸出部105e係藉由部分移除第二保護件105b暴露之導線105的焊座部105d而形成。在本揭露之實施例中,焊座部105d的移除部分係藉由蝕刻、雷射剝蝕、鑽孔或任何其它合適的製程予以移除。
在本揭露之實施例中,第一凸出部105e係在設置第二保護件105b之前形成。在本揭露之實施例中,步驟311係在步驟310之前實施。在圖24至圖26所示之實施例中,第一凸出部105e係設置在焊座部105d上方。在本揭露之實施例中,第一凸出部105e係藉由下列製程形成:如圖24所示,設置第二圖案化遮罩402在導線105上方,第二圖案化遮罩402包括複數個第二開口402a;如圖25所示,設置導電材料在第二開口402a中,以形成第一凸出部105e;以及如圖26所示,移除第二圖案化遮罩402。在本揭露之實施例中,第二圖案化遮罩402係藉由下列製程形成:設置光阻(PR)在第一保護件104上方,再部分移除光阻以形成複數個第二開口402a。在本揭露之實施例中,光阻係藉由沉積或任何其它合適的製程形成。在本揭露之實施例中,光阻之移除部分係藉由光微影、蝕刻或任何其它合適的製程予以移除。在本揭露之實施例中,第二圖案化遮罩402暴露焊座部105d的複數個部分。在本揭露之實施例中,第二圖案化遮罩402係藉由蝕刻、剝除或任何其它合適的製程予以移除。
在本揭露之實施例中,在如圖27所示或如上述步驟310,形成第一凸出部105e之後,設置第二保護件105b在導線105上方。
在步驟312中,如圖28所示,設置連接件106在第二保護件105b暴露之導線105上方。在本揭露之實施例中,連接件106環繞第一凸出部105e。在本揭露之實施例中,連接件106設置在焊座部105d上方並與第一凸出部105e交界。在本揭露之實施例中,連接件106係藉由電鍍、焊球落下、焊料貼合、網印或其它合適的製程形成。在本揭露之實施例中,連接件106至少部分被第二保護件105b環繞或至少部分設置在第二孔洞105f內。在本揭露之實施例中,接墊106經配置以與導電結構、晶片或封裝件接合。在本
揭露之實施例中,連接件106具有上文所述或圖1至圖6或圖10之任一所繪示者相似之構形。在本揭露之實施例中,上述說明圖1至圖6或圖10之任一者中所示之半導體結構(100或200)之製造方法。
本揭露提供一種半導體結構,包含:一基板,包括一第一表面及一第二表面,該第二表面係與該第一表面相對;一接墊,設置在該第一表面上方;一第一保護件,設置在該第一表面上方且部分覆蓋該接墊;以及一重佈線層(redistribution layer,RDL),設置在該第一保護件上方,且包括一導線及一第二保護件,該導線係延伸在該第一保護件上方,該第二保護件係部分覆蓋該導線;其中該導線包括一插塞部以及一焊座部,該插塞部與該接墊耦合且在該第一保護件內朝該接墊延伸,該焊座部延伸在該第一保護件上方,該焊座部包括複數個第一凸出部,向遠離第一保護件之方向凸出。
本揭露另提供一種半導體結構之製造方法,包括:提供一基板;設置一接墊在該基板上方;設置一第一保護件在該基板上方,以部分覆蓋該接墊;設置一導電材料在該第一保護件及該接墊上方,以形成一電連接至該接墊之導線;設置一第二保護件在該第一保護件上方,以部分覆蓋該導線;以及形成複數個第一凸出部在該第二保護件暴露出之導線上方。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自
本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
Claims (19)
- 一種半導體結構,包含:一基板,包括一第一表面及一第二表面,該第二表面係與該第一表面相對;一接墊,設置在該第一表面上方;一第一保護件,設置在該第一表面上方且部分覆蓋該接墊;以及一重佈線層(redistribution layer,RDL),設置在該第一保護件上方,且包括一導線及一第二保護件,該導線係延伸在該第一保護件上方,該第二保護件係部分覆蓋該導線;其中該導線包括一插塞部以及一焊座部,該插塞部與該接墊耦合且在該第一保護件內朝該接墊延伸,該焊座部延伸在該第一保護件上方,該焊座部包括複數個第一凸出部,向遠離該第一保護件之方向凸出;其中該第二保護件包含一孔洞,該等第一凸出部設置於該孔洞中,該孔洞暴露該等第一凸出部。
- 如請求項1所述之半導體結構,進一步包含一導電元件,設置在該基板與該導線的該焊座部之間。
- 如請求項1所述之半導體結構,其中該焊座部包括複數個第二凸出部,朝該基板凸出且被該第一保護件環繞。
- 如請求項3所述之半導體結構,其中該等第一凸出部係設置在該等第二凸出部上方。
- 如請求項3所述之半導體結構,其中該等第一凸出部係分別垂直對準該等第二凸出部。
- 如請求項3所述之半導體結構,其中該等第一凸出部係分別插置在該等第二凸出部之間。
- 如請求項1所述之半導體結構,進一步包含一連接件,設置在該焊座部上方。
- 如請求項7所述之半導體結構,其中該連接件係與該等第一凸出部交界。
- 如請求項7所述之半導體結構,其中該等第一凸出部係凸伸至該連接件中。
- 如請求項1所述之半導體結構,其中該等第一凸出部係被該第二保護件環繞。
- 一種半導體結構之製造方法,包含:提供一基板;設置一接墊在該基板上方;設置一第一保護件在該基板上方,以部分覆蓋該接墊;設置一導電材料在該第一保護件及該接墊上方,以形成一電連接至該接墊之導線;設置一第二保護件在該第一保護件上方,以部分覆蓋該導線;以及藉由部分移除該第二保護件暴露之導線形成複數個第一凸出部在該第二保護件暴露出之導線上方;其中該第二保護件包含一孔洞,該等第一凸出部設置於該孔洞中,該孔洞暴露該等第一凸出部。
- 如請求項11所述之製造方法,其中該等第一凸出部係藉由蝕刻、雷射剝蝕、鑽孔或電鍍製程形成。
- 如請求項11所述之製造方法,進一步包含:設置一圖案化遮罩在該導線上方,該圖案化遮罩包括複數個開口;設置該導電材料在該等開口內,以形成該等第一凸出部;以及移除該圖案化遮罩。
- 如請求項11所述之製造方法,進一步包含:設置一圖案化遮罩在該第一保護件上方,該圖案化遮罩包括複數個開口;部分移除該圖案化遮罩暴露出之該第一保護件,以形成複數個凹槽在該第一保護件上方;移除該圖案化遮罩;以及設置該導電材料在該等凹槽內,以形成複數個從該導線朝該基板凸出之第二凸出部。
- 如請求項11所述之製造方法,進一步包含設置一連接件在該第二保護件暴露出且環繞該等第一凸出部之導線上方。
- 如請求項11所述之製造方法,其中該導電材料係藉由電鍍或濺鍍製程形成。
- 如請求項11所述之製造方法,進一步包含設置一導電件在該基板上方。
- 一種半導體結構,包含:一基板,包括一導電通路;一第一保護件,設置在該基板上方且暴露該導電通路的一部分;一導線,設置在該第一保護件上方且電連接至該導電通路;以及一第二保護件,設置在該導線上方且暴露該導線的一部分;其中該第二保護件暴露出之該導線的該部分包括複數個第一凸出部,該等第一凸出部係向遠離該第一保護件之方向凸出;其中該第二保護件包含一孔洞,該等第一凸出部設置於該孔洞中,該孔洞暴露該等第一凸出部。
- 如請求項18所述之半導體結構,其中該導線包括複數個第二凸出部,該等第二凸出部係向該基板凸出且被該第一保護件環繞。
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US20150340329A1 (en) * | 2014-05-21 | 2015-11-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of forming the same |
Also Published As
Publication number | Publication date |
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US9984987B2 (en) | 2018-05-29 |
TW201806106A (zh) | 2018-02-16 |
CN107689353A (zh) | 2018-02-13 |
US20180114763A1 (en) | 2018-04-26 |
US10141275B2 (en) | 2018-11-27 |
US20180040575A1 (en) | 2018-02-08 |
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