TWI628752B - 半導體結構及其製造方法 - Google Patents
半導體結構及其製造方法 Download PDFInfo
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- TWI628752B TWI628752B TW105133336A TW105133336A TWI628752B TW I628752 B TWI628752 B TW I628752B TW 105133336 A TW105133336 A TW 105133336A TW 105133336 A TW105133336 A TW 105133336A TW I628752 B TWI628752 B TW I628752B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010410 layer Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000011241 protective layer Substances 0.000 claims abstract description 49
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- 238000000034 method Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229920001971 elastomer Polymers 0.000 claims description 4
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- 238000007650 screen-printing Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- 239000010931 gold Substances 0.000 description 6
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- 239000004332 silver Substances 0.000 description 6
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- 230000004888 barrier function Effects 0.000 description 5
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- 239000003989 dielectric material Substances 0.000 description 5
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- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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- 230000018109 developmental process Effects 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
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- 239000011347 resin Substances 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000007779 soft material Substances 0.000 description 2
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- 238000006467 substitution reaction Methods 0.000 description 2
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- 239000000919 ceramic Substances 0.000 description 1
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- 239000011133 lead Substances 0.000 description 1
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Classifications
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Abstract
一種半導體結構包含一基板;設置該基板上方的一接墊;設置該基板上方且暴露該接墊之一暴露部分的一保護層;以及設置該接墊之該暴露部分上方的一凸塊。該凸塊包含一緩衝件及一導電層,該緩衝件位於該接墊之該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊。
Description
本發明係關於一種包含凸塊的半導體結構,其中該凸塊包括緩衝件,其經配置以吸收或釋放該凸塊或該半導體結構的應力。
半導體裝置對於許多現代應用而言是很重要的。隨著電子技術的進展,半導體裝置的尺寸越來越小,功能越來越強大,且整合的電路數量越來越多。由於半導體裝置的尺度微小化,晶圓級晶片尺度封裝(wafer level chip scale packaging,WLCSP)已廣泛地應用於製造半導體裝置。在此等微小半導體裝置內,實施許多製造步驟。
然而,微型化尺度的半導體裝置之製造技術變得越來越複雜。製造半導體裝置的複雜度增加可造成缺陷,例如電互連不良、發生破裂、或元件脫層(delamination)。因此,修飾結構與製造半導體裝置有許多挑戰。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露提供一種半導體結構。該半導體結構包含一基板;設置該基板
上方的一接墊;設置該基板上方且暴露該接墊之一暴露部分的一保護層;以及設置該接墊之該暴露部分上方的一凸塊。該凸塊包含一緩衝件及一導電層,該緩衝件位於該接墊之該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊。
在本揭露之實施例中,該導電層係與該接墊的該暴露部分交界。
在本揭露之實施例中,該緩衝件係絕緣的、彈性的、或可變形的。
在本揭露之實施例中,該緩衝件包含彈性體或聚合物,或該導電層包含銅或焊料。
在本揭露之實施例中,該凸塊係彈性的或可變形的。
在本揭露之實施例中,該凸塊係電連接至該接墊。
在本揭露之實施例中,該緩衝件的一部分係設置於該接墊內或是延伸至該接墊中。
在本揭露之實施例中,該導電層的一部分係設置於該緩衝件內或是受到該緩衝件環繞。
在本揭露之實施例中,該半導體結構另包括一互連結構,設置於該導電層與該接墊之間,並且經設置以將該導電層電連接該接墊。
在本揭露之實施例中,該互連結構係凸塊下金屬化層(UBM),局部設置於該保護層上方或是局部受到該保護層環繞。
在本揭露之實施例中,該互連結構係設置於該緩衝件內或是受到該緩衝件環繞。
在本揭露之實施例中,該互連結構係與該緩衝件共形。
在本揭露之實施例中,該互連結構的一部分係設置於該導電層與該緩衝件之間。
在本揭露之實施例中,該互連結構的一部分係設置於該接墊內或是受到該接墊環繞。
在本揭露之實施例中,該半導體結構另包括一黏著層,設置於該緩衝件與該接墊的該暴露部分之間。
在本揭露之實施例中,該黏著層係設置於該緩衝件與該導電層之間,或該緩衝件係由該黏著層囊封。
在本揭露之實施例中,該黏著層係設置於該接墊內或受到該接墊環繞。
本揭露另提供一種半導體結構的製造方法。該製造方法包括:提供一基板;設置一接墊於該基板上方;設置一保護層於該基板與該接墊上方;局部移除該接墊上方的該保護層;設置一緩衝件於該接墊的一部分上方;以及設置一導電層於該緩衝件上方或附近;其中該緩衝件係受到該導電層環繞,以及該導電層係電連接至該接墊。
在本揭露之實施例中,該製造方法另包括在局部移除該保護層時或之後,局部移除該接墊。
在本揭露之實施例中,該製造方法藉由網印製程設置該緩衝件。
半導體結構經由連接件,例如凸塊(bump)、柱(pillar)、桿(post)或類似物而電連接另一晶片或封裝。該連接件自半導體結構的一接墊(pad)突出並且經配置以與另一晶片或封裝接合。在接合連接件與另一晶片或封裝之後,應力或力會作用於該連接件上並且對於該連接件與連接件下方的那些元件造成破壞。再者,在接合過程中或接合之後,會產生內部應力。連接件中可能產生破裂或甚至延伸至元件中,可能造成元件的脫層;因而發生電連接故障。
本揭露提供一種包含凸塊的半導體結構。該凸塊包括由導電層環繞的
緩衝件。緩衝件可提供凸塊彈性,因而可吸收作用在該凸塊上的力並且釋放製造過程中產生的內部應力。再者,此彈性凸塊可補償由半導體結構的元件之間的熱膨脹錯配造成的半導體結構之翹曲。因此,可最小化或防止半導體結構中的破裂與元件的脫層。因此,可改良半導體結構的可信賴度。
100‧‧‧半導體結構
101‧‧‧基板
101a‧‧‧第一表面
101b‧‧‧第二表面
102‧‧‧接墊
102a‧‧‧暴露部分
103‧‧‧保護層
103a‧‧‧凹槽
104‧‧‧凸塊
104a‧‧‧緩衝件
104a-1‧‧‧第一圓柱部
104a-2‧‧‧第一圓頂部
104b‧‧‧導電層
104b-1‧‧‧第二圓柱部
104b-2‧‧‧第二圓頂部
105‧‧‧黏著層
106‧‧‧互連結構
參閱詳細說明與申請專利範圍結合考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1係一剖面示意圖,例示本揭露實施例的半導體結構。
圖2至圖30係剖面示意圖,例示本揭露實施例的各種架構或形狀之半導體結構。
圖31係一流程圖,例示本揭露實施例之半導體結構的製造方法。
圖32至圖60係剖面示意圖,例示本揭露實施例藉由圖31的方法而製造半導體結構。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式,說明本揭露之實施例,然而本揭露並不受限於該實施例。此外,以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性,然而並非每一實施例必須包含該特定特徵、結構或是特性。再者,重複使用「在本揭露之實施例中」一語並非必須指相同實施例,然而可為相同實施例。
本揭露係關於包含凸塊(bump)的半導體結構,該凸塊包括緩衝件,經配置以補償半導體結構因元件之間熱膨脹錯配(mismatch)造成半導體結構的翹曲(warpage)並在製造過程中釋放半導體結構上方或半導體結構內的應力。為了使得本揭露可被完全理解,以下說明提供詳細的步驟與結構。顯然,本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外,已知的結構與步驟不再詳述,以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而,除了詳細說明之外,本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容,而是由申請專利範圍定義。
半導體結構經由連接件,例如凸塊(bump)、柱(pillar)、桿(post)或類似物而電連接另一晶片或封裝。該連接件自半導體結構的一接墊(pad)突出並且經配置以與另一晶片或封裝接合。在接合連接件與另一晶片或封裝之後,應力或力會作用於該連接件上並且對於該連接件與連接件下方的那些元件造成破壞。再者,在接合過程中或接合之後,會產生內部應力。連接件中可能產生破裂或甚至延伸至元件中,可能造成元件的脫層;因而發生電連接故障。
本揭露提供一種包含凸塊的半導體結構。該凸塊包括由導電層環繞的緩衝件。緩衝件可提供凸塊彈性,因而可吸收作用在該凸塊上的力並且釋放製造過程中產生的內部應力。再者,此彈性凸塊可補償由半導體結構的元件之間的熱膨脹錯配造成的半導體結構之翹曲。因此,可最小化或防止半導體結構中的破裂與元件的脫層。因此,可改良半導體結構的可信賴度。
圖1係一剖面示意圖,例示本揭露實施例的半導體結構。在本揭露之
實施例中,半導體結構100包含基板101、接墊102、保護層103以及凸塊104。在本揭露之實施例中,半導體結構100為晶粒、晶片或半導體封裝的一部分。
在本揭露之實施例中,基板101具有預定的功能電路。在本揭露之實施例中,基板101包含數個導電線以及由該等導電線連接的數個電子元件,例如電晶體與二極體。在本揭露之實施例中,基板101為半導體基板。在本揭露之實施例中,基板101係一晶圓。在本揭露之實施例中,基板101包含半導體材料,例如矽、鍺、鎵、砷、以及其組合。在本揭露之實施例中,基板101為矽基板。在本揭露之實施例中,基板101包含例如陶瓷、玻璃、或類似物之材料。在本揭露之實施例中,基板101為玻璃基板。在本揭露之實施例中,基板101係四邊形、矩形、正方形、多邊形、或任何其他合適的形狀。
在本揭露之實施例中,基板101包含第一表面101a以及與第一表面101a相對的第二表面101b。在本揭露之實施例中,第一表面101a為正面或是主動面,其中電路或電子元件係設置第一表面101a上。在本揭露之實施例中,第二表面101b為背面或是非主動面(inactive side)。
在本揭露之實施例中,接墊102係位於基板101上方。在本揭露之實施例中,接墊102係位於基板101的第一表面101a上方或是基板101的第一表面101a內。在本揭露之實施例中,接墊102係位於基板101的第二表面101b上方。在本揭露之實施例中,接墊102係電連接至基板101中的電路或電子元件。在本揭露之實施例中,接墊102電連接基板101外部的電路,因而基
板101中的電路可經由接墊102而電連接至基板101外部的電路。在本揭露之實施例中,接墊102係經配置以接收導電結構。在本揭露之實施例中,接墊102為晶粒接墊或是接合接墊。在本揭露之實施例中,接墊102包含金、銀、銅、鎳、鎢、鋁、鈀、與/或其合金。
在本揭露之實施例中,保護層103係位於基板101的第一表面101a或第二表面101b上方。在本揭露之實施例中,保護層103係位於基板101與接墊102的周圍上方。在本揭露之實施例中,保護層103局部覆蓋接墊102;因此,接墊102的一暴露部分102a係自保護層103暴露。在本揭露之實施例中,保護層103環繞接墊102。在本揭露之實施例中,保護層103係經配置以對於基板101提供電性絕緣與防潮保護,因而基板101係與周圍環境隔離。
在本揭露之實施例中,保護層103包含彼此堆疊的數層介電材料。在本揭露之實施例中,保護層103係由介電材料形成,該介電材料例如氧化矽、氮氧化矽、氮化矽、或類似物。在本揭露之實施例中,保護層103包含位於接墊102上方的凹槽103a。在本揭露之實施例中,凹槽103a暴露接墊102的暴露部分102a,因而接墊102可容納導電結構或電連接至基板101外部的電路。
在本揭露之實施例中,凸塊104係位於基板101的第一表面101a或第二表面101b上方。在本揭露之實施例中,凸塊104係位於接墊102的暴露部分102a上方。在本揭露之實施例中,凸塊104係接合且電連接至接墊102。在本揭露之實施例中,凸塊104係局部受到保護層103的環繞。在本揭露之實
施例中,凸塊104係位於保護層103的凹槽103a內。在本揭露之實施例中,凸塊104係經配置以接合導電結構、晶片或封裝。
在本揭露之實施例中,凸塊104係自接墊102或保護層103突出。在本揭露之實施例中,凸塊104為圓柱形、球形、或半球形。在本揭露之實施例中,凸塊104為焊料接合、焊料凸塊、焊球、球柵陣列(BGA)球、受控的塌陷晶片連接(C4)凸塊、微凸塊、或類似物。在本揭露之實施例中,凸塊104為導電柱或桿。
在本揭露之實施例中,凸塊104包含緩衝件104a與導電層104b。在本揭露之實施例中,緩衝件104a係位於接墊102的暴露部分102a上方且自接墊102的暴露部分102a突出。在本揭露之實施例中,緩衝件104a係自接墊102延伸並且遠離基板101。在本揭露之實施例中,緩衝件104a係直立在接墊102上方。在本揭露之實施例中,緩衝件104a係位於保護層103的凹槽103a內。在本揭露之實施例中,緩衝件104a為圓柱形。在本揭露之實施例中,緩衝件104a的剖面為圓形、矩形、四邊形、或多邊形。
在本揭露之實施例中,緩衝件104a係經配置以吸收施加於凸塊104上方的力或是半導體結構100內部的應力。在本揭露之實施例中,緩衝件104a包含彈性的、可變形的、可撓的、或軟的材料。在本揭露之實施例中,緩衝件104a包含介電材料。在本揭露之實施例中,緩衝件104a為絕緣的。在本揭露之實施例中,緩衝件104a包含彈性體、矽氧烷(silicone)、樹脂、環氧化合物、聚合物、聚亞醯胺、或聚苯并噁唑(polybenzoxazole,PBO)。
在本揭露之實施例中,導電層104b環繞緩衝層104a並且電連接至接墊
102。在本揭露之實施例中,導電層104b囊封緩衝件104a。在本揭露之實施例中,導電層104b之配置係與緩衝件104a共形。在本揭露之實施例中,緩衝件104a的外表面係與導電層104b交界。在本揭露之實施例中,導電層104b係局部受到保護層103環繞。在本揭露之實施例中,導電層104b係與接墊102的暴露部分102a交界,因而導電層104b電連接至接墊102。在本揭露之實施例中,導電層104b包含銅、金、銀、鎳、焊料、錫、鉛、鎢、鋁、鈦、鈀、與/或其合金。
在本揭露之實施例中,包含緩衝件104a的凸塊104為有彈性的、可變形的或可壓縮的。在本揭露之實施例中,凸塊104係經配置以吸收施加在凸塊104上方的力或是半導體結構100內部的應力,因而可最小化或防止凸塊104或半導體結構中發生破裂。在本揭露之實施例中,凸塊104係經配置以釋放半導體結構100中的元件之間的熱膨脹錯配造成的內部應力。例如,基板101的熱膨脹係數(coefficient of thermal expansion,CTE)係不同於保護層103的CTE,因而在熱製程中,基板101與保護層103的膨脹程度不同,造成半導體結構100的翹曲。具有彈性的凸塊104可減輕或防止半導體結構100的翹曲或彎曲。在本揭露之實施例中,凸塊104係可壓縮的,因而當力施加在凸塊104上方時,凸塊104可降低高度。在本揭露之實施例中,可壓縮的凸塊104可補償半導體結構100的翹曲或彎曲。
圖2與圖3係本揭露實施例之半導體結構100的剖面示意圖,說明本揭露不同架構的緩衝件104與導電層104b。在本揭露之實施例中,緩衝件104包含第一圓柱部104a-1以及第一圓頂部104a-2。在本揭露之實施例中,第
一圓柱部104a-1自接墊102延伸。在本揭露之實施例中,第一圓頂部104a-2係位於第一圓柱部104a-1的一端。在本揭露之實施例中,導電層104b之配置係與緩衝件104a的外表面共形。在本揭露之實施例中,導電層104b包含第二圓柱部104b-1與第二圓頂部104b-2。在本揭露之實施例中,第二圓柱部104b-1環繞第一圓柱部104a-1,以及第二圓頂部104b-2係位於第一圓頂部104a-2上方。
如圖2所示,在本揭露之實施例中,凸塊104的寬度係與凹槽103a的寬度實質相等或是小於凹槽103a的寬度。如圖3所示,在本揭露之實施例中,凸塊104的寬度係實質大於凹槽103的寬度,因而部分的導電層104b位於保護層103上方。
圖4與圖5係本揭露實施例之半導體結構100的剖面圖,其中半導體結構100包括黏著層105。在本揭露之實施例中,黏著層105係位於緩衝件104a與接墊102的暴露部分102a之間。在本揭露之實施例中,緩衝件104a係藉由黏著層105而附接於接墊102上。在本揭露之實施例中,黏著層105係位於凹槽103a內並且受到導電層104b環繞。在本揭露之實施例中,黏著層105包含聚合材料。在本揭露之實施例中,黏著層105為黏膠、助焊劑(flux)、晶粒附接膜(die attach film,DAF)、或類似物。
如圖5所示,在本揭露之實施例中,黏著層105囊封緩衝件104a。在本揭露之實施例中,黏著層105係位於緩衝件104a與導電層104b之間。在本揭露之實施例中,黏著層105係受到導電層104b環繞。在本揭露之實施例中,黏著層105之配置係與緩衝件104a的外表面共形。在本揭露之實施例
中,導電層104b之配置係與黏著層105的外表面共形。
圖6至圖8係本揭露實施例之半導體結構100的剖面示意圖,其中半導體結構100包括互連結構106。在本揭露之實施例中,互連結構106係位於導電層104b與接墊102之間。在本揭露之實施例中,互連結構106環繞緩衝件104a。在本揭露之實施例中,互連結構106係經配置以將導電層104b電連接接墊102。在本揭露之實施例中,互連結構106包含導電材料,例如銅、金、銀、鎳、焊料、錫、鉛、鎢、鋁、鈦、鈀、與/或其合金。
如圖6所示,在本揭露之實施例中,互連結構106係位於凹槽103a內並且受到接墊102、保護層103與導電層104b環繞。如圖7所示,在本揭露之實施例中,互連結構106係局部位於保護層103上方,並且局部受到保護層103環繞。在本揭露之實施例中,緩衝層104a與導電層104b係受到互連結構106環繞。如圖8所示,在本揭露之實施例中,互連結構106之配置係與緩衝件104a的外表面共形,因而環繞緩衝件104a。在本揭露之實施例中,導電層104b之配置係與互連結構106的外表面的一部分共形。在本揭露之實施例中,互連結構106的一部分係位於緩衝件104a與導電層104b之間。
在本揭露之實施例中,互連結構106為凸塊下金屬化層(under bump metallization,UBM)或為UBM的一部分。在本揭露之實施例中,阻障層與晶種層係位於UBM與接墊102之間。在本揭露之實施例中,阻障層係位於接墊102上方,晶種層係位於阻障層上方。在本揭露之實施例中,阻障層係經配置以防止導電層104a之元素擴散至接墊102中。在本揭露之實施例中,阻障層包含金、銀、鎳、錫、鉛、或類似物。在本揭露之實施例中,
晶種層係經配置以將UBM黏著至接墊102。在本揭露之實施例中,晶種層包含銅、金、銀、鎳、焊料、錫、鉛、鋁、鈦、或類似物。
圖9至圖13係本揭露實施例之半導體結構100的剖面示意圖,其中半導體結構100包括不同架構的黏著層105與互連結構106。如圖9所示,在本揭露之實施例中,半導體結構100包含圖4所示之黏著層105以及圖6所示之互連結構106。在本揭露之實施例中,互連結構106環繞黏著層105。如圖10所示,在本揭露之實施例中,半導體結構100包含圖5所示之黏著層105以及圖6所示之互連結構106。如圖11所示,在本揭露之實施例中,半導體結構100包含圖4所示之黏著層105以及圖7所示之互連結構106。如圖12所示,在本揭露之實施例中,半導體結構100包含圖5所示之黏著層105以及圖7所示之互連結構106。如圖13所示,在本揭露之實施例中,半導體結構100包含圖4所示之黏著層105以及圖8所示之互連結構106。
圖14至圖16係本揭露實施例之半導體結構100的剖面示意圖,其中半導體結構100包括不同架構的黏著層105與互連結構106。如圖14所示,在本揭露之實施例中,互連結構106與導電層104b的一部分係位於緩衝件104a內,或受到緩衝件104a環繞。如圖15所示,在本揭露之實施例中,黏著層105係位於緩衝件104a與接墊102之間,互連結構106係位於緩衝件104a與黏著層105內。如圖16所示,在本揭露之實施例中,互連結構106之配置係與緩衝件104a共形,互連結構106的一部分係位於緩衝件104a內。
圖17至圖19係本揭露實施例之半導體結構100的剖面示意圖,其中凸塊104具有不同形狀。如圖17所示,在本揭露之實施例中,凸塊104的剖面
為四邊形或是梯形。如圖18所示,在本揭露之實施例中,凸塊104的剖面為三角形。如圖19所示,在本揭露之實施例中,凸塊104的剖面為多邊形或不規則形。在本揭露之實施例中,導電層104b的外表面、導電層104b與互連結構106a之間的界面或是緩衝件104a與互連結構106之間的界面包含波紋或波浪形狀。
圖20至圖30係本揭露實施例之半導體結構100的剖面示意圖,其中半導體結構100包括突出至接墊102的緩衝件104a。在本揭露之實施例中,緩衝件104a的一部分係位於接墊102內,或是延伸至接墊102中。
如圖20所示,在本揭露之實施例中,緩衝件104a的一部分係突出至接墊102中,並且受到接墊102環繞。如圖21所示,在本揭露之實施例中,黏著層105係位於接墊102內或是受到接墊102環繞,緩衝件104a的一部分係位於黏著層105上方。在本揭露之實施例中,緩衝件104a的一部分係突出至接墊102中。如圖22所示,在本揭露之實施例中,半導體結構100包含圖20所示之緩衝件104a以及圖6所示之互連結構106。如圖23所示,在本揭露之實施例中,半導體結構100包含圖21所示之緩衝件104a以及圖6所示之互連結構106。
如圖24所示,在本揭露之實施例中,緩衝件104a的一部分與互連結構106的一部分係位於接墊102之內或是受到接墊102環繞。如圖25所示,在本揭露之實施例中,半導體結構100包含圖21所示之緩衝件104a與黏著層105,以及圖24所示之互連結構106。
如圖26所示,在本揭露之實施例中,黏著層105係位於接墊102內,緩
衝件104a係位於黏著層105上方或是位於接墊102內,互連結構106係配置如圖11所示。如圖27所示,在本揭露之實施例中,黏著層105係位於接墊102內,緩衝件104a係位於黏著層105上方或位於接墊102內,互連結構106係配置如圖13所示。
如圖28所示,在本揭露之實施例中,互連結構106的一部分與緩衝件104a的一部分係位於接墊102內或受到接墊102環繞。如圖29所示,在本揭露之實施例中,黏著層105、緩衝件104a的一部分以及互連結構106的一部分係位於接墊102內或受到接墊102環繞。如圖30所示,在本揭露之實施例中,黏著層105、緩衝件104a的一部分以及互連結構106的一部分係位於接墊102內,並且互連結構106之配置係與緩衝件104a共形。
本揭露亦提供一種半導體結構100的製造方法。在本揭露之實施例中,半導體結構100可由圖31的方法200予以形成。方法200包含一些操作,描述與說明,不應被視為操作順序的限制。方法200包含一些步驟(201、202、203、204、205與206)。
在步驟201中,提供或接收基板101,如圖32所示。在本揭露之實施例中,基板101包含第一表面101a以及與第一表面101a相對的第二表面101b。在本揭露之實施例中,基板101包含數個導電線,以及由該等導電線連接的數個電子元件,例如電晶體與二極體。在本揭露之實施例中,基板101為半導體基板。在本揭露之實施例中,基板101包含矽、鍺、鎵、砷、以及其組合。在本揭露之實施例中,基板101為矽基板。在本揭露之實施例中,基板101為四邊形、矩形、正方形、多邊形、或任何其他合適的形狀。
在本揭露之實施例中,基板101具有與如上述或圖1至圖30中任一者所示之類似架構。
在步驟202中,設置接墊102於基板101的第一表面101a上方。在本揭露之實施例中,接墊102係電連接至基板101中的電路。在本揭露之實施例中,接墊102係經配置以接收導電結構。在本揭露之實施例中,接墊102為晶粒接墊或接合墊。在本揭露之實施例中,接墊102包含金、銀、銅、鎳、鎢、鋁、鈀、與/或其合金。在本揭露之實施例中,接墊102係由電鍍或任何其他合適的製程形成。在本揭露之實施例中,接墊102具有與如上述或圖1至圖30中任一者所示之類似架構。
在步驟203中,設置保護層103於基板101與接墊102上方,如圖34所示。在本揭露之實施例中,保護層103形成具有介電材料,例如氧化矽、氮氧化矽、氮化矽或類似物。在本揭露之實施例中,保護層103係藉由化學氣相沉積(chemical vapor deposition,CVD)、電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、旋塗或任何其他合適的製程而配置。在本揭露之實施例中,保護層103具有與如上述或圖1至圖30中任一者所示之類似架構。
在步驟204中,局部移除接墊102上方之保護層103,如圖35所示。在本揭露之實施例中,藉由蝕刻或任何其他合適的製程,局部移除保護層103。在本揭露之實施例中,局部移除接墊102上方之保護層103以形成凹槽103a,而且接墊102的暴露部分102a係自保護層103暴露。
在本揭露之實施例中,如圖36所示,在局部移除保護層103時或之後,
局部移除接墊102。在本揭露之實施例中,藉由蝕刻或任何其他合適的製程,局部移除接墊102以形成開口102b。
在步驟205中,緩衝件104a係位於接墊102上方,如圖37至圖42中任一者所示。在本揭露之實施例中,緩衝件104a係藉由網印製程、網印充填(stencil filing)、化學氣相沉積(CVD)、或任何其他合適的製程而配置。在本揭露之實施例中,緩衝件104a係位於凹槽103a內。在本揭露之實施例中,緩衝件104係自接墊102突出。在本揭露之實施例中,緩衝件104a係圓柱形。在本揭露之實施例中,緩衝件104a包含有彈性的、可變形的、可撓的或軟的材料。在本揭露之實施例中,緩衝件104a包含介電材料。在本揭露之實施例中,緩衝件104a係絕緣的。在本揭露之實施例中,緩衝件104a包含彈性體、矽氧烷(silicone)、樹脂、環氧化合物、聚合物、聚亞醯胺、或聚苯并噁唑(polybenzoxazole,PBO)。在本揭露之實施例中,緩衝件104a具有與如上述或圖1至圖30中任一者所示之類似架構。
在本揭露之實施例中,如圖37所示,緩衝件104a係位於接墊102的暴露部分102a上方。在本揭露之實施例中,如圖38所示,在圖36所示之步驟204之後,緩衝件104a係位於開口102b內。在本揭露之實施例中,緩衝件104a係局部位於接墊102內。
在本揭露之實施例中,如圖39至圖42所示,黏著層105係位於緩衝件104a與接墊102之間。在本揭露之實施例中,黏著層105係位於緩衝件104a下方或附接至緩衝件104a,而後緩衝件104a與黏著層105係位於接墊102上方。在本揭露之實施例中,黏著層105係位於接墊102上方,而後緩衝件104a
係位於黏著層105上方。在本揭露之實施例中,黏著層105係藉由印刷、旋塗、或任何其他合適的製程而配置。在本揭露之實施例中,黏著層105具有與如上述或圖4、圖5、圖9至圖13、圖15至圖19、圖21、圖23、圖25至圖27、圖29與圖30中任一者所示之類似架構。
在本揭露之實施例中,如圖39所示,黏著層105係位於接墊102的該暴露部分102a上方並且位於凹槽103a內。在本揭露之實施例中,如圖40所示,黏著層105係位於接墊102內或是位於接墊102的開口102b內。
在本揭露之實施例中,如圖41所示,黏著層105囊封緩衝件104a,而後緩衝件104a與環繞緩衝件104a的黏著層105係位於接墊102上方並且位於凹槽103a內。在本揭露之實施例中,黏著層105之配置係與緩衝件104a的外表面共形。在本揭露之實施例中,如圖42所示,緩衝件104a的一部分與黏著層105的一部分係位於接墊102的開口102b內。
在步驟206中,設置導電層104b於緩衝件104上方或附近,如圖43至圖60中的任一者所示。在本揭露之實施例中,如圖43至圖48所示,導電層104b係分別位於圖37至圖42的緩衝件104a上方。在本揭露之實施例中,藉由配置光阻(photoresist,PR)於保護層103上方、移除該光阻的一部分以圖案化該光阻、配置導電材料於該光阻之所移除的部分內、以及移除該光阻而形成該導電層104b。在本揭露之實施例中,藉由電鍍或任何其他合適的製程,配置該導電材料。在本揭露之實施例中,藉由沉積或任何其他合適的製程而配置該光阻。在本揭露之實施例中,藉由微影、蝕刻、或任何其他合適的製程,移除該光阻的該部分。在本揭露之實施例中,藉由蝕刻、
剝除、或任何其他合適的製程,完全移除該光阻。在本揭露之實施例中,導電層104b具有與如上述或圖1至圖30中任一者所示之類似架構。
在本揭露之實施例中,形成包括緩衝件104a與導電層104b的凸塊104。在本揭露之實施例中,凸塊係有彈性的、可變形的、或可壓縮的。在本揭露之實施例中,凸塊104係經配置以吸收施加於凸塊104上方的力或是在半導體基板100內部的應力。
在本揭露之實施例中,互連結構106係位於接墊102與導電層104b之間,如圖49至圖60中任一者所示。在本揭露之實施例中,導電層104b係經由互連結構106而電連接至接墊102。在本揭露之實施例中,互連結構106係至少局部位於接墊102上方。在本揭露之實施例中,互連結構106為UBM或是UBM的一部分。在本揭露之實施例中,互連結構106具有與如上述或圖6至圖19與圖22至圖30中任一者所示之類似架構。
在本揭露之實施例中,藉由配置第一導電材料於保護層103上方或與緩衝件104a的外表面共形、配置光阻於第一導電材料與保護層103上方、移除光阻的一部分而圖案化該光阻、配置第二導電材料於該光阻之所移除的部分內、以及移除該光阻與位於保護層103上方的第一導電材料之一部分,而形成互連結構106與導電層104b。
在本揭露之實施例中,如圖49至圖54所示,互連結構106環繞緩衝件104a或位於接墊102上方的黏著層105,如圖37、圖39或圖41所示。在本揭露之實施例中,如圖55至圖60所示,互連結構106環繞緩衝件104a或位於接墊102內的黏著層105,如圖38、圖40或圖42所示。
本揭露提供一種半導體結構,包含一基板;位於該基板上方的一接墊;位於該基板上方且暴露該接墊之一暴露部分的一保護層;以及位於該接墊之該暴露部分上方的一凸塊,其中該凸塊包含一緩衝件以及一導電層,該緩衝件位於該接墊之該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊。
本揭露另提供一種半導體結構的製造方法,包含提供一基板;設置一接墊於該基板上方;設置一保護層於該基板與該接墊上方;局部移除該接墊上方的該保護層;設置一緩衝件於該接墊的一部分上方;以及設置一導電層於該緩衝件上方或附近,其中該緩衝件係受到該導電層環繞,該導電層係電連接至該接墊。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
Claims (17)
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;以及一凸塊,設置於該接墊的該暴露部分上方;其中該凸塊包含一緩衝件及一導電層,該緩衝件設置於該接墊的該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊;其中該凸塊係彈性的或可變形的。
- 如請求項1所述之半導體結構,其中該導電層係與該接墊的該暴露部分交界。
- 如請求項1所述之半導體結構,其中該緩衝件係絕緣的、彈性的、或可變形的。
- 如請求項1所述之半導體結構,其中該緩衝件包含彈性體或聚合物,或該導電層包含銅或焊料。
- 如請求項1所述之半導體結構,其中該凸塊係電連接至該接墊。
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;以及一凸塊,設置於該接墊的該暴露部分上方;其中該凸塊包含一緩衝件及一導電層,該緩衝件設置於該接墊的該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊;其中該緩衝件的一部分係設置於該接墊內或是延伸至該接墊中。
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;以及一凸塊,設置於該接墊的該暴露部分上方;其中該凸塊包含一緩衝件及一導電層,該緩衝件設置於該接墊的該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊;其中該導電層的一部分係設置於該緩衝件內或是受到該緩衝件環繞。
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;一凸塊,設置於該接墊的該暴露部分上方,其中該凸塊包含一緩衝件及一導電層,該緩衝件設置於該接墊的該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊;以及一互連結構,設置於該導電層與該接墊之間,並且經設置以將該導電層電連接該接墊;其中該互連結構係設置於該緩衝件內或是受到該緩衝件環繞。
- 如請求項8項所述之半導體結構,其中該互連結構係凸塊下金屬化層(UBM),局部設置於該保護層上方或是局部受到該保護層環繞。
- 如請求項8所述之半導體結構,其中該互連結構係與該緩衝件共形。
- 如請求項8所述之半導體結構,其中該互連結構的一部分係設置於該導電層與該緩衝件之間。
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;一凸塊,設置於該接墊的該暴露部分上方,其中該凸塊包含一緩衝件及一導電層,該緩衝件設置於該接墊的該暴露部分上方,該導電層環繞該緩衝件且電連接至該接墊;以及一互連結構,設置於該導電層與該接墊之間,並且經設置以將該導電層電連接該接墊;其中該互連結構的一部分係設置於該接墊內或是受到該接墊環繞。
- 一種半導體結構,包括:一基板;一接墊,設置於該基板上方;一保護層,設置於該基板上方並且暴露該接墊的一暴露部分;一凸塊,設置於該接墊的該暴露部分上方;以及一黏著層,設置於該緩衝件與該接墊的該暴露部分之間。
- 如請求項13所述之半導體結構,其中該黏著層係設置於該緩衝件與該導電層之間,或該緩衝件係由該黏著層囊封。
- 如請求項13所述之半導體結構,其中該黏著層係設置於該接墊內或受到該接墊環繞。
- 一種半導體結構的製造方法,包括:提供一基板;設置一接墊於該基板上方;設置一保護層於該基板與該接墊上方;局部移除該接墊上方的該保護層;設置一緩衝件於該接墊的一部分上方;以及設置一導電層於該緩衝件上方或附近;其中該緩衝件係受到該導電層環繞,以及該導電層係電連接至該接墊;其中該製造方法另包括在局部移除該保護層時或之後,局部移除該接墊。
- 一種半導體結構的製造方法,包括:提供一基板;設置一接墊於該基板上方;設置一保護層於該基板與該接墊上方;局部移除該接墊上方的該保護層;設置一緩衝件於該接墊的一部分上方;以及設置一導電層於該緩衝件上方或附近;其中藉由網印製程設置該緩衝件。
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US15/203,055 US9704818B1 (en) | 2016-07-06 | 2016-07-06 | Semiconductor structure and manufacturing method thereof |
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CN110164830B (zh) * | 2019-04-26 | 2021-02-05 | 厦门云天半导体科技有限公司 | 一种功率器件的三维互连结构及其制作方法 |
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