CN110164830B - 一种功率器件的三维互连结构及其制作方法 - Google Patents

一种功率器件的三维互连结构及其制作方法 Download PDF

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CN110164830B
CN110164830B CN201910344722.1A CN201910344722A CN110164830B CN 110164830 B CN110164830 B CN 110164830B CN 201910344722 A CN201910344722 A CN 201910344722A CN 110164830 B CN110164830 B CN 110164830B
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CN110164830A (zh
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于大全
姜峰
王阳红
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Xiamen Yun Tian Semiconductor Technology Co ltd
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Abstract

一种功率器件的三维互连结构及其制作方法,包括载板、第一金属层、导电材料、芯片、填充层、金属结构,绝缘层和信号端口;该第一金属层设于载板的上表面,且第一金属层或载板上设有凸起结构;该芯片背面通过导电材料贴合于第一金属层表面;该填充层包覆于芯片和第一金属层外,并露出芯片的焊盘和第一金属层的局部;该金属结构设于填充层表面并设有外连区域;该封装层设于金属结构表面并露出外连区域;该信号端口与外连区域电性连接。本发明通过第一金属层实现更好的散热效果、降低了成本、减小了封装体积、提高了产品的可靠性。

Description

一种功率器件的三维互连结构及其制作方法
技术领域
本发明涉及半导体封装领域,特别是一种功率器件的三维互连结构及其制作方法。
背景技术
随着人们对电子产品的要求向小型化、多功能、环保型等方向的发展,人们努力寻求将电子系统越做越小,集成度越来越高,功能越做越多、越来越强,由此产生了许多新技术、新材料和新设计,其中扇出型封装技术就是这些技术的典型代表。
作为广泛应用的单颗芯片封装技术,传统封装目前已经逐渐呈现出封装效率低下和成本持续攀升的弊端。圆片级封装作为一种新型的封装方式,因能够较大地减少芯片封装尺寸,而被业界广泛采用。现有的BGA封装技术受到有机基板性能的限制。向扇出WLP的转移有助于克服这些限制,且能简化供应链。扇出WLP的主要优点是能很好地控制翘曲,这就能实现高装配良率。在封装自身上建立基板允许在较少的金属层中实现较高的集成和布线密度。扇出WLP是支撑未来集成(特别是对于无线器件)的下一代平台。
发明内容
本发明的主要目的在于克服现有技术中的上述缺陷,提出一种散热性能好、降低成本、减小体积的功率器件的三维互连结构及其制作方法。
本发明采用如下技术方案:
一种功率器件的三维互连结构,包含至少一个芯片,该芯片具有第一表面和第二表面,第一表面设有焊盘,其特征在于:还包括载板、第一金属层和金属结构;该载板上设有至少一个凸起结构;该第一金属层沿载板表面延伸至凸起结构表面;芯片的第二表面通过导电材料与第一金属层粘结,且芯片和凸起结构被绝缘材料包封;该绝缘材料表面制备有金属结构,且部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘电性连接。
所述凸起结构为聚合物或金属或基体本身材料。
一种功率器件的三维互连结构,包含至少一个芯片,芯片具有第一表面和第二表面,第一表面设有焊盘,其特征在于:还包括载板、第一金属层和金属结构;该载板表面设有第一金属层;该第一金属层设有至少一个凸起结构;芯片的第二表面或焊盘通过导电材料与第一金属层粘结,且芯片和凸起结构被绝缘材料包封;该绝缘材料表面制备有金属结构,部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘或第二表面电性连接。
所述金属结构包括金属再布线层和多个信号端口,该金属再布线层表面制备有绝缘层;该信号端口与金属再布线层电性连接。
所述凸起结构高度大于、等于或小于所述芯片高度;或者所述凸起结构高度为大于20um。
所述载板为有机基板、硅、玻璃或者陶瓷。
所述芯片的第二表面还设有第二金属层。
一种功率器件的三维互连结构制作方法,其特征在于:包括如下步骤:
1)在载板上制作凸起结构,在载板和凸起结构上表面制作第一金属层;或者在载板表面制作具有凸起结构的第一金属层;
2)在第一金属层上制作导电材料;
3)将芯片的第二表面通过导电材料与第一金属层贴合;
4)采用绝缘材料包覆凸起结构和芯片,并开孔露出芯片焊盘和凸起结构的局部;
5)在绝缘材料表面制作金属结构,并使部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘电性连接。
在步骤3)-步骤5)中,将芯片的第一表面的焊盘采用倒装方式与第一金属层电性连接,并使部分金属结构与第二表面电性连接。
在步骤4)中采用印刷或者塑封制作所述绝缘材料。
由上述对本发明的描述可知,与现有技术相比,本发明具有如下有益效果:
1、本发明的结构,其在载板或第一金属层上设置凸起结构,使得芯片能实现更好的散热效果、提高了产品的可靠性。
2、本发明的结构,在芯片第二表面设有第二金属层,该第二金属层通过第一金属层可起到接地作用。
3、本发明的结构,可在载板上直接制作凸起结构,降低制作工艺的难度、提升产品的制程良率。
4、本发明的结构,采用扇出型封装结构,降低了封装体翘曲,能实现高装配良率。
5、本发明的结构,可采用晶圆级封装,适合大规模批量生产并降低生产成本。
附图说明
图1为本发明结构图(实施例一);
图2为制作第一金属层示意图(实施例一);
图3为制作导电材料示意图(实施例一);
图4为芯片贴合示意图(实施例一);
图5为制作绝缘材料示意图(实施例一);
图6为刻蚀绝缘材料示意图(实施例一);
图7为制作金属再布线层示意图(实施例一);
图8为制作绝缘层示意图(实施例一);
图9为制作信号端口示意图(实施例一);
图10为本发明结构图(实施例二);
图11为制作第一金属层示意图(实施例二);
图12为制作导电材料示意图(实施例二);
图13为芯片贴合示意图(实施例二);
图14为制作绝缘材料示意图(实施例二);
图15为刻蚀绝缘材料示意图(实施例二);
图16为制作金属再布线层示意图(实施例二);
图17为制作绝缘层示意图(实施例二);
图18为制作信号端口示意图(实施例二);
图19为本发明结构图(实施例三);
图20为制作第一金属层示意图(实施例三);
图21为制作导电材料示意图(实施例三);
图22为芯片贴合示意图(实施例三);
图23为制作绝缘材料示意图(实施例三);
图24为刻蚀绝缘材料示意图(实施例三);
图25为制作金属再布线层示意图(实施例三);
图26为制作绝缘层示意图(实施例三);
图27为制作信号端口示意图(实施例三);
图28为实施例四的结构图;
其中:10、载板,11、凸起结构,20、第一金属层,30、导电材料,40、芯片,41、焊盘,42、第二金属层,50、绝缘材料,60、金属再布线层,61、外连区域,70、绝缘层,80、信号端口。
具体实施方式
以下通过具体实施方式对本发明作进一步的描述。本发明的各附图仅为示意以更容易了解本发明,其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系,在本领域技术人员应能理解是指构件的相对位置而言,对应的,以元件在上一面为正面、在下一面为背面以便于理解,因此皆可以翻转而呈现相同的构件,此皆应同属本说明书所揭露的范围。
实施例一
参见图1至图9,一种功率器件的三维互连结构,包括载板10、第一金属层20、导电材料30、芯片40、绝缘材料50、金属结构等。该载板10上设有凸起结构11。该凸起结构11为贴合于载板10的表面,该载板10可为有机基板、硅、玻璃或者陶瓷,该凸起结构11为聚合物或金属或基体本身材料。
本发明的凸起结构11的截面形状为长方形或梯形,数量可以为至少一个,位于载板10靠近边缘或中间处,不作限定。优选为数量一个,截面为梯形,整体可以是圆柱、棱柱、棱台等。
该第一金属层20沿载板10表面延伸至凸起结构11的上表面,载板10上表面可被完全覆盖或局部覆盖,凸起结构11表面被完全覆盖。
包括有至少一个芯片40,该芯片40具有第一表面和第二表面,第一表面设有焊盘41。该芯片40的第二表面通过导电材料30贴合于第一金属层20表面。该导电材料30面积可大于、等于或小于芯片40背面面积。该芯片40与凸起结构11之间具有一定距离,该距离不作限定。凸起结构11高度可大于或小于或等于芯片40的整体厚度,优选为大于20um。该芯片40为功率芯片,例如MOSFET场效应晶体管,但不限于此。
本发明中,还可在芯片10的第二表面设置第二金属层(图中未示出),该第二金属层通过导电材料30贴合于第一金属层20表面,则第二金属层可与第一金属层20相连实现接地。
该绝缘材料50包封于芯片40和第一金属层20外,即将外露的芯片40及第一金属层20进行覆盖,再进行蚀刻露出芯片40的焊盘41和第一金属层20的局部。该绝缘材料50可采用聚合物材质。该外露的局部的数量不唯一,可以是一处或两处甚至更多。该局部可以是凸起结构11的顶部和/或侧部所在处的第一金属层区域,或者非凸起结构11处所在的第一金属层区域。优选的,外露的局部为一处,位于凸起结构11顶部区域。
该金属结构包括金属再布线层60和多个信号端口80,该金属再布线层60设有外连区域61,金属再布线层60表面制备有绝缘层70。该信号端口80与金属再布线层60电性连接。该绝缘层70用于保护金属再布线层60并露出外连区域61,其可采用聚合物材料,提高产品的绝缘性能且对金属再布线层60起到防氧化的作用。该信号端口80与外连区域61电性连接。该信号端口80为BGA焊球、镍钯金、镍金或钛铜焊盘。
本发明还提出一种功率器件的三维互连结构制作方法,用于制作上述的功率器件的三维互连结构,采用晶圆级封装,包括如下步骤:
1)在载板10上表面贴合一层聚合物材料,对该聚合物材料进行光刻制作形成凸起结构11。
2)在载板10和凸起结构11表面溅镀一层第一金属层20。
3)在第一金属层20上制作导电材料30。
4)将芯片40第二表面通过导电材料30与第一金属层20贴合。
5)制作绝缘材料50包覆外露的第一金属层20、导电材料30和芯片40,并开孔露出芯片40的焊盘41和第一金属层20的局部,填充工艺可以为印刷或塑封,且可通过曝光进行开孔。
6)在绝缘材料50表面制作金属再布线层60,该金属再布线层60设有外连区域61。
7)制作绝缘层70保护金属再布线层60,开孔露出外连区域61。
8)在外连区域61上制作信号端口80。
9)进行切割、标记,形成单颗封装结构。
采用本发明制作方法制作的功率器件,设置有凸起结构11,能实现更好的散热性能,且在载板10上制作凸起结构11,大大降低了成本、减小了封装体积,提高了可靠性。
实施例二
参见图10至图18,一种功率器件的三维互连结构及其制作方法,其主要结构与实施例一相同,区别在于:凸起结构11载板为载板10的一部分,即凸起结构11与载板10的材质相同,该凸起结构11为载板10通过光刻和刻蚀制作而成。
实施例三
参见图19至图27,一种功率器件的三维互连结构,其主要结构与实施例一相同,区别在于:载板10不设有凸起结构11,而在第一金属层20上设有凸起结构11,该凸起结构11可为实心或空心结构,其为金属材质。
其包括一种功率器件的三维互连结构制作方法,包括如下步骤:
1)在载板10表面制作具有凸起结构11的第一金属层20;
2)在第一金属层20上制作导电材料30;
3)将芯片40通过导电材料30与第一金属层20贴合;
4)制作绝缘材料50包覆第一金属层20和芯片40,并开孔露出芯片40的焊盘41和第一金属层20的局部;
5)在绝缘材料50表面制作金属再布线层60,该金属再布线层60设有外连区域61;
6)制作绝缘层70保护金属再布线层60,开孔露出外连区域61;
7)在外连区域61上制作信号端口80。
8)进行切割、标记。
实施例四
参见图28,一种功率器件的三维互连结构,其主要结构与实施例一相同,区别在于:在芯片40的第二表面设置第二金属层42,芯片40第一表面的焊盘采用倒置方式。芯片40的第一表面的焊盘上设金属连接通过导电材料与第一金属层20电性连接,其中第一金属层20可设有多个金属连接区域,凸起结构11位于其中一金属连接区域,芯片40的多个焊盘41可分别与不同的金属连接区域电性连接。
另外,若凸起结构11数量为两个以上,分别位于不同金属连接区域,则不同焊盘41可通过连接第一金属层的对应金属连接区域,实现与不同凸起结构11电性连接。
绝缘材料表面的部分金属结构与第一金属层20的相同或不同金属连接区域电性连接,部分金属结构与芯片第二表面的第二金属层42电性连接。
对应的一种功率器件的三维互连结构的制作方法,其主要步骤与实施例一相同,区别在于:在步骤4)中将芯片40第一表面通过导电材料30与第一金属层20贴合。
在步骤5)中,制作绝缘材料50包覆外露的第一金属层20、导电材料30和芯片40,并开孔露出芯片40的第二表面和第一金属层20的局部,填充工艺可以为印刷或塑封,且可通过曝光进行开孔。
上述仅为本发明的具体实施方式,但本发明的设计构思并不局限于此,凡利用此构思对本发明进行非实质性的改动,均应属于侵犯本发明保护范围的行为。

Claims (9)

1.一种功率器件的三维互连结构,包含至少一个芯片,该芯片具有第一表面和第二表面,第一表面设有焊盘,其特征在于:还包括载板、第一金属层和金属结构;该载板上设有至少一个凸起结构;该第一金属层沿载板表面延伸至凸起结构表面;芯片的第二表面或焊盘通过导电材料与第一金属层粘结,且芯片和凸起结构被绝缘材料包封;该绝缘材料表面制备有金属结构,且部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘或第二表面电性连接,所述金属结构包括金属再布线层和多个信号端口,该金属再布线层表面制备有绝缘层;该信号端口与金属再布线层电性连接。
2.如权利要求1所述的一种功率器件的三维互连结构,其特征在于:所述凸起结构为聚合物或金属或基体本身材料。
3.一种功率器件的三维互连结构,包含至少一个芯片,芯片具有第一表面和第二表面,第一表面设有焊盘,其特征在于:还包括载板、第一金属层和金属结构;该载板表面设有第一金属层;该第一金属层设有至少一个凸起结构;芯片的第二表面通过导电材料与第一金属层粘结,且芯片和凸起结构被绝缘材料包封;该绝缘材料表面制备有金属结构,部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘电性连接,所述金属结构包括金属再布线层和多个信号端口,该金属再布线层表面制备有绝缘层;该信号端口与金属再布线层电性连接。
4.如权利要求1或3所述的一种功率器件的三维互连结构,其特征在于:所述凸起结构高度大于、等于或小于所述芯片高度;或者所述凸起结构高度为大于20um。
5.如权利要求1或3所述的一种功率器件的三维互连结构,其特征在于:所述载板为有机基板、硅、玻璃或者陶瓷。
6.如权利要求1或3所述的一种功率器件的三维互连结构,其特征在于:所述芯片的第二表面还设有第二金属层。
7.一种功率器件的三维互连结构制作方法,用于制作权利要求1至6中任一所述的一种功率器件的三维互连结构,其特征在于:包括如下步骤:
1)在载板上制作凸起结构,在载板和凸起结构上表面制作第一金属层;或者在载板表面制作具有凸起结构的第一金属层;
2)在第一金属层上制作导电材料;
3)将芯片的第二表面通过导电材料与第一金属层贴合;
4)采用绝缘材料包覆凸起结构和芯片,并开孔露出芯片焊盘和凸起结构的局部;
5)在绝缘材料表面制作金属结构,并使部分金属结构与第一金属层电性连接,部分金属结构与芯片的焊盘电性连接。
8.如权利要求7所述的一种功率器件的三维互连结构制作方法,其特征在于:在步骤3)-步骤5)中,可将芯片的第一表面的焊盘采用倒置方式与第一金属层电性连接,并使部分金属结构与芯片第二表面电性连接。
9.如权利要求7所述的一种功率器件的三维互连结构制作方法,其特征在于:采用印刷或者塑封制作所述绝缘材料。
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