TWI621157B - 共形摻雜的方法與設備 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
在此提供用於處理基材的方法與設備。一些實施例中,摻雜基材的方法可包括以下步驟:透過使用電漿摻雜製程將一或多種摻質元素佈植進入基材的摻質區域而在該基材上形成該摻質區域;在該摻質區域頂上形成覆蓋層;形成該覆蓋層後退火該摻質區域;以及退火該摻質區域後移除該覆蓋層。
Description
本發明的實施例大體上關於半導體製造,詳言之,關於用於摻雜基材的方法。
用於目標為共形FINFET、共形DRAM與共形快閃記憶體摻雜應用的N型佈植製程之典型摻質包括砷與磷。在習知上,離子束佈植製程用於摻雜基材,稱為束線(beamline)製程。在束線製程中,必須使用各種基材傾斜的組合以確保基材上形成的特徵結構的側壁表面能令人滿意地受到佈植。然而,在基材的高傾斜角度下,緊密封裝的側壁可能不會完全暴露至離子束,此現象會非所期望地導致摻質材料不均勻分佈。此狀況已知為遮蔽效應。
因此,發明人已提供改善的共形摻雜方法。
在此提供用於共形摻雜基材的方法與設備。一些實施例中,本發明之方法可有利地限制摻質損失並且達成強化的摻質擴散。在此提供用於處理基材的方法與設備。一些實施例中,摻雜基材的方法可包括以下步驟:透過使用電漿摻雜製程將一或多種摻質元素佈植進入基材的
摻質區域而在該基材上形成該摻質區域;在該摻質區域頂上形成覆蓋層;形成該覆蓋層後退火該摻質區域;以及退火該摻質區域後移除該覆蓋層。
一些實施例中,一種摻雜基材的方法可包含以下步驟:透過在電漿摻雜製程中將一或多種摻質元素佈植進入基材的摻質區域而在該基材上形成該摻質區域;在該摻質區域頂上形成覆蓋層;減少該覆蓋層的厚度;減少該覆蓋層的厚度後退火該摻質區域;以及退火該摻質區域後從該摻質層頂上移除該覆蓋層。
下文中將描述本發明的其他與進一步的實施例。
本發明的實施例提供用於摻雜基材的改善方法。本發明的實施例可有利地限制摻質損失且可達成強化的摻質擴散。可使用本發明的實施例的示範性(但為非限制性)應用範例包括邏輯、DRAM、快閃記憶體與FINFET結構與元件的製造。改善的共形摻雜製程的示範性(但為非限制性)目標區域的範例可包括多晶矽、超淺接面(USJ)、源汲區域與矽深溝槽區域。
發明人已經觀察到,由於電漿摻雜技術簡單且具高生產力,故電漿摻雜技術是一項吸引人的傳統束線離子佈植的替代方案。然而,發明人已觀察到,電漿摻雜的基材傾向具有非常高表面濃度的摻質。所以,發明人相信
該等摻質在後摻雜處理(例如,在長時間暴露至高溫的時候)中可能會損失。摻質的損失可能取決於許多因素,該等因素包括摻雜與後續製程(諸如退火製程)之間的時間延遲、退火溫度與周圍大氣。此外,發明人相信含砷(As)或磷(P)的表面膜會對安全有害,此狀況是由於該等元素的高毒性與前述的摻質損失問題結合所致。例如,砷佈植的基材暴露至大氣時,將會驅除氣體並且釋放砷化氫(AsH3),該砷化氫具有低於50 ppb的門檻極限值(threshold limit value(TLV))。
發明人已經進一步觀察到,在摻雜的基材上執行退火製程之後,除去(或大幅限制)了驅除氣體的風險,因此使得砷與磷摻雜的基材能更安全地受到操作。此外,發明人已經觀察到,退火過的基材在暴露到大氣時,不會損失摻質。
第1圖描繪根據本發明一些實施例用於摻雜基材的方法100。第2A圖至第2C圖根據本發明一些實施例說明第1圖中所繪的本發明之方法100的不同階段期間基材的剖面視圖。
方法100大體上始於102,其中摻質區域202形成在基材200上,如第2A圖所繪。摻質區域202可以透過在佈植製程(諸如電漿輔助佈植製程)中將一或多種摻質佈植進入基材200而形成。以替代方式或結合之方式,也可透過沉積摻質前驅物於基材200的表面上而執行摻雜製程。任一製程皆可在任何適合的摻雜腔室(例如第
一處理腔室)中執行,該摻雜腔室諸如為電漿輔助摻雜腔室。適合的摻雜腔室的範例包括電漿離子浸潤佈植反應器,該反應器包括可購自美國加州聖克拉拉市的應用材料公司的CONFORMATM反應器,但不以此為限。在下文中,將針對第3圖描述一種此類適合的處理腔室。儘管可在此提供特定的處理腔室以說明本發明的實施例,然而,應考量也可使用其他適合的處理腔室,包括來自其他製造商的處理腔室。
基材200可包含適合用於製造半導體元件的材料。例如在一些實施例中,基材可包含半導體材料及/或半導體材料與非半導體材料的組合,以用於形成半導體結構及/或元件。例如,該基材可包含一或多種含矽材料,諸如結晶矽(例如Si<100>或Si<111>)、氧化矽、應變矽、多晶矽、矽晶圓、玻璃、藍寶石或類似物。該基材可進一步具有任何期望的幾何形狀,諸如200或300 mm的晶圓、方形或矩形的平板或類似物。在一些實施例中,基材200可以是半導體晶圓(例如200 mm、300 mm或類似的矽晶圓)。
一些實施例中,基材可為無摻雜,或可含有後續將受到摻雜的無摻雜區域。如在此所用,無摻雜意味著在該區域中不含有n型或p型摻質。或者,在一些實施例中,該基材可以受到摻雜,且待執行進一步地摻雜該基材或該基材的幾個部分。基材200可包含一或多層,且在一些實施例中,基材200可進一步包括配置在該基材中或
上的完成的或部分完成的電子元件。
當摻雜基材時,基材的整個表面可受到摻雜,或者若基材的一些選擇區域待受摻雜時,可沉積圖案化遮罩層(諸如圖案化光阻層)於基材頂上以保護基材不受摻雜的區域。例如在一些實施例中,可提供遮罩層(諸如一層光阻)並且將該遮罩層圖案化,使得摻質區域202僅在部分的基材200上形成。
待佈植的一或多種摻質可包含一般用在半導體摻雜製程中的任何適合的一或多種元素。適合的摻質的範例包括一或多種三族元素或五族元素,在非限制性的範例中,該適合的摻質包括砷(As)、硼(B)、銦(In)、磷(P)、銻(Sb)或類似元素。N型摻質的範例可包括磷、砷或類似元素之至少一者。例如,砷化氫(AsH3)、氟化二砷(As2F5)、磷化氫(PH3)或三氟化磷(PF3)是一般用於目標為共形FINET(FIN場效電晶體)、共形DRAM(動態隨機存取記憶體)與共形快閃記憶體摻雜應用的n型佈植製程的典型摻質前驅物。對於p型摻雜而言,可使用含硼前驅物,諸如三氟化硼(BF3)、二硼烷(B2H6)或類似物。其他適合用於基材(或基材的幾個部分)的材料修飾的摻質之範例包括鍺烷(GeH4)、甲烷(CH4)、二氧化碳(CO2)、四氟化碳(CF4)、矽烷(SiH4)、四氟化矽(SiF4)、氮氣(N2)與氧氣(O2)。
一些實施例中,可透過使用低能量的佈植製程在非常低的壓力下以最小氣體流量佈植該一或多種摻質。此類
製程可有利地增加中性離子在佈植期間的分佈,此舉減緩投劑速率。或者,可增加佈植壓力且可減少處理氣體流量,以增加在低能量佈植製程中摻質離子的滯留時間。
例如,可以透過提供包含一或多種前驅物氣體的第一處理氣體形成摻質區域202。該一或多種前驅物氣體包含待佈植的元素,例如前文所述的任何摻質元素。可以適合的流率提供第一處理氣體,該流率例如為約0.5 sccm至約400 sccm。一些實施例中,第一處理氣體可進一步包含載氣,例如惰氣,包括氬氣、氦氣、氮氣或類似氣體,但不以此為限。提供載氣的實施例中,載氣可構成高達約90百分比的第一處理氣體,或者是構成約1%至約99%之間的第一處理氣體。
可從第一處理氣體生成電漿以將一或多種摻質佈植進入基材而形成摻質區域,或者將一或多種摻質沉積在基材頂上而形成摻質區域。電漿可透過以下步驟形成:施加適合形成電漿的頻率(例如在MHz或GHz範圍)的源功率。
基材200可在佈植及/或沉積期間受到偏壓,以控制離子朝向基材200的通量,且在一些實施例中,控制離子滲透進入基材200的深度。例如,一些實施例中,可提供高達約50至3000瓦的基材偏壓功率,該基材偏壓功率的頻率介於約0.5 MHz至約60 MHz之間或約2 MHz。佈植及/或沉積期間,源RF功率可以是約100至3000瓦,而頻率介於約0.5 MHz至約60 MHz之間,或約13.5
MHz。
可在低壓製程中形成電漿,因而減少基材200中雜質誘發缺陷的可能性及/或任何下伏層(諸如含矽層)不定形化的可能性。例如,一些實施例中,可在約1 mTorr至約500 mTorr之間的壓力下執行離子佈植。再者,透過使用遠端電漿源(或視情況透過脈衝該電漿源功率),可進一步限制或防止甚至在如此低壓的層級下可能發生的離子轟擊誘導的缺陷。
以替代方式取代佈植製程,或除了佈植製程之外以結合方式,可沉積該一或多種摻質於基材200的頂部上以形成摻質區域202。例如在適合執行前述佈植製程的相同腔室中,可將該一或多種摻質沉積在基材200頂上。例如,透過減少或消除基材偏壓電壓,可將一或多種摻質沉積在基材頂部上。沉積膜的厚度可由無(或減少的)基材偏壓電壓之製程歷時、一或多種摻質之流率、處理腔室中的壓力以及電漿源功率層級控制。
接著,在104,覆蓋層204沉積成覆於摻質區域202上,如第2B圖所繪。發明人已經觀察到,當用電漿技術佈植摻質時,摻質傾向損失劑量,此狀況是由於後續退火期間摻質與周圍大氣交互作用所致。例如,退火期間,在氧氣(O2)的周圍環境中可能損失大約50%的劑量,且在氮氣(N2)的周圍環境中可能損失大約90%的劑量。因此,覆蓋層204可有利地做為摻質區域202與大氣之間的物理阻障物,以防止源自摻質區域202的摻質損
失。摻質包含毒性或其他不安全材料的實施例中,覆蓋層使基材能安全地受到操作。
一些實施例中,覆蓋層204是由含矽膠材料形成,該材料諸如為二氧化矽(SiO2)、矽烷(SiH4)、碳化矽(SiC)或類似材料。一些實施例中,覆蓋層204可具有範圍高達約100埃之厚度。可透過任何適合的製程沉積覆蓋層204,該製程諸如為化學氣相沉積(CVD)、物理氣相沉積(PVD)或類似製程。覆蓋層204可以在沉積腔室中形成。一些實施例中,沉積腔室可以是摻質區域202所形成的第一處理腔室,即覆蓋層204可以原位形成。或者,覆蓋層204可在摻質區域202所形成的腔室之外的不同處理腔室中形成。在此類實施例中,基材可被傳送到覆蓋層沉積腔室,同時例如透過使用下文中針對第4圖所述的群集工具維持在真空下。
接著,在106可視情況而定蝕刻覆蓋層204以減少覆蓋層204的厚度。減少覆蓋層的厚度有助於更容易且更快速地在退火基材(如下文所討論)後移除覆蓋層204。覆蓋層204可在蝕刻腔室中受到蝕刻。該蝕刻腔室可以是覆蓋層204所形成的相同處理腔室(例如,第一處理腔室或覆蓋層沉積腔室)或不同的處理腔室。一些實施例中,因為覆蓋層204保護摻質區域202免於驅除氣體及/或與大氣反應,基材200可傳送到處理腔室以供蝕刻而無須維持在真空下。
在摻雜製程期間使用遮罩層保護基材200的實施例
中,遮罩層可在退火基材200之前移除。例如,一些實施例中,基材200可在真空下傳送至遮罩移除腔室,在該腔室中,可移除遮罩層。一些實施例中,可在電漿摻雜腔室中或蝕刻腔室(例如,用於蝕刻覆蓋層204的蝕刻腔室)中原位將遮罩層從基材200移除,而無須將基材200傳送到另一腔室。一些實施例中,因為覆蓋層204保護摻質區域202免於驅除氣體及/或與大氣反應,基材200可傳送到遮罩移除腔室而無須維持在真空下。
一些實施例中,遮罩層可包含一層光阻。可例如透過暴露至電漿而剝除該遮罩層,該電漿包含氧氣(O2)、三氟化氮(NF3)、四氟化碳(CF4)、氫氣(H2)或氮氣(N2)之一或多者。取決於任何對遮罩層的損害、電漿化學性質與電漿密度,可在類似摻雜腔室(例如P3I處理腔室)的腔室中移除該遮罩層。例如,可經調整以助於遮罩層移除的處理參數可包括RF源功率(例如提供給電漿的RF功率)、氣體流量、腔室壓力與時間。遮罩移除腔室可以是任何能夠執行視情況任選的遮罩移除製程的腔室。此類適合的腔室的非限制性範例包括前述的P3I處理腔室或Axiom處理腔室,該處理腔室也可購自應用材料公司。也可使用包括可購自其他製造商的其他處理腔室。
接著,在108,將基材200退火以活化配置在摻質區域中的摻質。在一或多種摻質沉積在摻質區域202頂上的實施例中,該製程可助於將該一或多種摻質驅入基材
200。可在摻質活化腔室中退火基材。在一些實施例中,可在真空下傳送基材至摻質活化腔室,在該腔室中,該基材可被退火以活化佈植在基材中或配置在基材上的摻質。一些實施例中,因為覆蓋層204保護摻質區域202免於驅除氣體及/或與大氣反應,基材200可傳送到摻質活化腔室而無須維持在真空下。
一些實施例中,可透過將基材加熱到第一溫度而退火基材,該第一溫度介於約攝氏600至1300度之間,或為約攝氏1000度。一些實施例中,可在兩個步驟的製程中退火基材,該製程包含首先將基材加熱到約攝氏200度至約攝氏800度的第一溫度達第一段時間,該第一段時間是從約1秒至數小時。之後,可加熱基材到更高的第二溫度。該第二溫度可以是約攝氏800度至約攝氏1300度,並且可有約1秒至約數小時的歷時。退火製程期間,基材可暴露至惰氣,該惰氣諸如為氮氣(N2)、氬氣(Ar)、氦氣(He)或類似氣體、氫氣(H2)、氨氮(NH3)、氧氣(O2)或前述氣體之組合。若基材不具有保護摻雜區域的圖案化遮罩,可在摻雜製程後直接從摻雜腔室傳送基材到摻質活化腔室。發明人已經發現,摻質損失與介電膜的堆積(例如由於暴露至濕氣所造成的諸如氧化硼之介電膜的堆積)可透過原位摻質活化(例如退火)及透過不將基材暴露至大氣而減少。摻質活化製程可以是高溫製程(諸如退火),且可以在任何適合的處理腔室中執行,該處理腔室諸如但不限於RTP RADIANCE®處理
腔室,或是在CENTURA®平台中的任何其他退火工具中執行,前述之處理腔室與平台皆可購自應用材料公司。
接著,在110,如第2C圖所示,移除覆蓋層204。可以在任何適合的處理腔室中移除覆蓋層204,該處理腔室諸如為前文所述在106用於減少覆蓋層204之厚度的處理腔室。可使用任何適合的蝕刻製程移除覆蓋層204。例如,可使用氟前驅物(諸如三氟化氮(NF3))移除矽類的覆蓋層204。一旦在110移除覆蓋層204,方法100大體上終結,而基材可持續如期望般處理以完成製造程序。根據對結構化晶圓的穿透式電子顯微鏡(TEM)分析,已證實(1)佈植的砷膜與覆蓋膜是共形的,且在頂部表面上有減少的沉積(例如,已提供更加共形且均勻的膜輪廓)以及(2)剝除覆蓋層後,對結構無損害。
參考第3圖,前文參考的申請案中揭示的該種環形(toroidal)源電漿浸潤離子佈植(P3i)反應器300具有圓柱狀真空腔室302,該腔室302被圓柱狀側壁304以及碟形頂壁306界定。位在腔室底壁的基材支撐件308支撐待處理的基材310。位在頂壁306上的氣體分配盤或噴頭312在自身的氣體歧管314中接收來自氣體分配平板316的處理氣體,氣體分配平板316的氣體輸出可以是源自一或多種個別氣體供應器318的一種氣體或多種氣體之混合物。真空泵320耦接抽吸環(pumping annulus)322,該抽吸環322被界定在基材支撐件308與側壁304之間。處理區域324被界定在基材310與氣
體分配盤312之間。
一對外部凹曲導管326、328建立凹曲環形路徑以供通過處理區域324的電漿流所用,並且該等環形路徑在處理區域324中交錯。每一導管326、328具有一對端部330,該等端部330耦接腔室的相對側。每一導管326、328是中空導通管。每一導管326、328具有D.C.絕緣圈332,該D.C.絕緣圈332防止導管兩端之間形成封閉迴路導通路徑。
每一導管326、328的環狀部分被環狀磁性核心334環繞。環繞核心334的激發線圈336經由阻抗匹配裝置340耦接RF功率源338。耦接核心336之各別一者的兩個RF功率源338可以具有兩種稍微不同的頻率。由RF功率生成器338耦合的RF功率產生延伸經由各別導管326、328並且經由處理區域324的封閉環狀路徑的電漿離子流。該等離子流以各別RF功率源338的頻率震盪。藉由偏壓功率生成器342經由阻抗匹配電路344及/或藉由DC功率源350施加偏壓功率予以基材支撐件308。
電漿的形成是透過以下步驟執行:將處理氣體(或處理氣體混合物)經由氣體分配盤312導進腔室324,並且從生成器338施加充分的源功率至凹曲導管326、328,而在導管與處理區域324中建立環狀電漿流。
接近基材表面的電漿通量是由基材偏壓電壓所確定,該基材偏壓電壓是由RF偏壓功率生成器342施加。電漿速率或通量(每平方公分每秒取樣基材表面的離子數)
是由電漿密度確定,而電漿密度是由RF源功率生成器338施加的RF功率層級所控制。基材310上的累積離子劑量(每平方公分的離子數)是由通量以及維持通量的總時間所確定。
倘若基材支撐件308是靜電夾盤,則將嵌埋的電極346設在基材支撐件的絕緣盤348內,且嵌埋的電極346透過阻抗匹配電路344耦接偏壓功率生成器342或者DC功率源350。
在操作上(且舉例而言),可將基材310放置在基材支撐件308上,且可將一或多種處理氣體導進腔室302以從處理氣體點燃電漿。
在操作上,電漿可由反應器300內的處理氣體生成,以選擇性修飾基材310的表面,如前文所討論。根據前述的製程,電漿是在處理區域324中形成,此舉是透過以下步驟完成:從生成器338施加充分的源功率給凹曲導管326、328,以在導管326、328中及處理區域324中建立電漿離子流。一些實施例中,由RF偏壓功率生成器342遞送的基材偏壓電壓可經調整以控制離子至基材表面的通量,且可能控制以下一或多者:基材上形成的層厚度,或基材表面上嵌入的電漿物種濃度。
第4圖描繪適合用於執行本發明幾個部分的群集工具。大體而言,群集工具是一種模組化系統,包含執行各種功能的多個腔室,該等功能包括:找尋基材中心及定向基材、覆蓋化、退火、沉積及/或蝕刻。根據本發明
的實施例,群集工具可包括退火處理腔室、覆蓋處理腔室、蝕刻處理腔室以及層沉積處理腔室,該等腔室設以執行本發明的方法100所述的發明性步驟。群集工具的多個處理腔室裝設至中央傳送腔室,該中央傳送腔室容納適以在腔室之間接駁基材的機器人。傳送腔室一般是被維持在真空條件下,並且提供從一個腔室接駁基材至另一腔室及/或至裝載閉鎖室(定位在群集工具的前端)的中間階段。一種此類階段式真空基材處理系統的細節揭示在美國專利案第5,186,718號,該專利發明名稱為「Staged-Vacuum Substrate Processing System and Method」,在1993年2月16日頒發給Tepman等人。但是,可變更精確的腔室排列方式與組合方式,以為執行製造製程的特定步驟,所述製造製程包括用於限制摻質損失且達成強化摻質擴散的本發明之共形摻雜方法。
透過說明的方式,特定的群集工具480顯示於第4圖的平面視圖中。群集工具480大體上包含複數個腔室與機器人,且該群集工具480較佳為裝配有微處理器控制器440,該控制器440經程式化以操作在群集工具480中所執行的各處理方法。圖中圖示前端環境483經定位以和一對裝載閉鎖室484選擇性連通。配置在前端環境483中的晶圓盒(pod)裝載器485能夠線性及旋轉移動(箭號482),以在裝載閉鎖室484與複數個晶圓盒487(裝設在前端環境483上)接駁基材之晶圓匣。裝載閉鎖室484提供前端環境483與傳送腔室488之間的第一
真空介面。設置兩個裝載閉鎖室484以透過選擇地與傳送腔室488和前端環境483連通而增加處理量。因此,在一個裝載閉鎖室484與傳送腔室488連通的同時,第二裝載閉鎖室484與前端環境483連通。機器人489配置在傳送腔室488中央,以將基材從裝載閉鎖室484傳送到各處理腔室490與維護腔室491之一者。處理腔室490可以執行任何數量的製程(諸如物理氣相沉積、化學氣相沉積與蝕刻),而維護腔室491適於去氣、定向、冷卻及類似製程。
本發明的實施例中,處理腔室490中至少一者設成電漿摻雜處理腔室(諸如於第3圖說明的腔室300)或可購自應用材料公司的P3i腔室;且處理腔室490中至少一者設成退火處理腔室490。一些實施例中,電漿摻雜腔室可用於在基材200上形成摻質區域202、在摻質區域202頂上形成覆蓋層204以及移除覆蓋層204。摻質活化腔室可用於在覆蓋層204形成後退火摻質區域202。在群集工具480上納入兩種腔室使得基材200得以維持免受污染並且防止基材暴露到大氣,而防止摻質損失。
一些實施例中,第一處理腔室490A(例如電漿摻雜腔室)用於在基材200上形成摻質區域202,第二處理腔室490B(例如沉積腔室)用於在摻質區域202頂上沉積覆蓋層204,第三處理腔室490C(例如摻質活化腔室)用於在形成覆蓋層204後退火摻質區域202,以及第四
處理腔室490D(例如蝕刻腔室)用於在退火摻質區域202後移除覆蓋層204。或者,該蝕刻腔室及/或摻質活化腔室之至少一者可配置在群集工具480之遠端。
在退火摻質區域202前減少覆蓋層204的厚度的實施例中,覆蓋層204的蝕刻可以在電漿摻雜腔室中執行,或者是在耦接群集工具480的分開的蝕刻腔室中執行。
一些實施例中,在基材200上形成摻質區域202以及在摻質區域202頂上形成覆蓋層204可發生在群集工具480中,而退火摻質區域202前減少覆蓋層厚度、在形成覆蓋層204後退火摻質區域202以及移除覆蓋層204可發生在一或多個配置在群集工具遠端且分開的處理腔室中。
控制器440大體上包含中央處理單元(CPU)442、記憶體444與支援電路446,並且該控制器直接(如第4圖所圖示)或者透過電腦(或控制器)耦接且控制群集工具480和支援系統430,該電腦(或控制器)與處理腔室及/或支援系統相連。
控制器440可含有電腦可讀媒體,該電腦可讀媒體具有儲存在控制器440上面的指令,以用於執行前文所述根據本發明實施例的方法。當控制器讀取電腦可讀媒體時,控制器440直接或者透過電腦(或控制器)發送執行本發明之方法的指令給處理腔室490,該電腦(或控制器)與處理腔室490及/或該等電腦之支援系統相連。或者,用於執行本發明之方法的電腦可讀媒體可被包括
在與處理腔室490相連的控制器上。
因此,在此提供了用於限制摻質損失以及達成強化的摻質擴散的方法。雖然前述內容涉及本發明的實施例,可不背離本發明之基本範疇而設計本發明的其他與進一步的實施例。
100‧‧‧方法
102-110‧‧‧步驟
200‧‧‧基材
202‧‧‧摻質區域
204‧‧‧覆蓋層
300‧‧‧反應器
302‧‧‧圓柱狀真空腔室
304‧‧‧圓柱狀側壁
306‧‧‧碟形頂壁
308‧‧‧基材支撐底座
310‧‧‧基材
312‧‧‧氣體分配盤或噴頭
314‧‧‧氣體歧管
316‧‧‧氣體分配平板
318‧‧‧個別氣體供應器
320‧‧‧真空泵
322‧‧‧抽吸環
324‧‧‧處理區域
326、328‧‧‧外部凹曲導管
330‧‧‧端部
332‧‧‧D.C.絕緣圈
334‧‧‧環狀磁性核心
336‧‧‧激發線圈
338‧‧‧RF功率源
340‧‧‧阻抗匹配裝置
342‧‧‧偏壓功率生成器
344‧‧‧阻抗匹配電路
346‧‧‧嵌埋的電極
348‧‧‧絕緣盤
350‧‧‧DC功率源
430‧‧‧支援系統
440‧‧‧控制器
442‧‧‧中央處理單元
444‧‧‧記憶體
446‧‧‧支援電路
480‧‧‧群集工具
482‧‧‧箭號
483‧‧‧前端環境
484‧‧‧裝載閉鎖室
485‧‧‧晶圓盒裝載器
487‧‧‧晶圓盒
488‧‧‧傳送腔室
489‧‧‧機器人
490A-D‧‧‧處理腔室
491A-B‧‧‧維護腔室
透過參考附圖中所繪的本發明之說明性實施例,可瞭解在發明內容中簡短總結及在實施方式中詳細描述的本發明之實施例。然而應注意,附圖僅說明此發明的典型實施例,因此不應將該等附圖視為限制本發明之範疇,因本發明可容許其他等效的實施例。
第1圖是根據本發明一些實施例的方法的流程圖,該方法限制摻質損失並且達成強化的摻質擴散。
第2A圖至第2C圖描繪根據本發明一些實施例處理的不同階段期間基材的說明性剖面圖。
第3圖描繪根據本發明一些實施例電漿浸潤離子佈植處理腔室。
第4圖描繪根據本發明一些實施例的適合用於執行本發明幾個部分的群集工具。
為了助於瞭解,如可能則使用相同元件符號指定共通於各圖的相同元件。該等圖式並未按照比例尺繪製,且為了簡明起見而經過簡化。應考量一個實施例的元件與
特徵可有利地在其他實施例中結合而無須進一步記敘。
Claims (15)
- 一種摻雜一基材的方法,該方法包含以下步驟:透過使用一電漿摻雜製程將一或多種摻質元素佈植進入一基材的一摻質區域而在該基材上形成該摻質區域;在該摻質區域頂上形成一覆蓋層,該覆蓋層做為該摻質區域與大氣之間的物理阻障物;減少該覆蓋層的一厚度;減少該覆蓋層的厚度後退火該摻質區域;以及退火該摻質區域後移除該覆蓋層。
- 如請求項1所述的方法,其中在該基材上形成該摻質區域進一步包含以下步驟:將一含砷摻質元素或一含磷摻質元素之至少一者佈植進入該基材的該摻質區域。
- 如請求項1所述的方法,其中在該基材上形成該摻質區域進一步包含以下步驟:將三氟化硼(BF3)、二硼烷(B2H6)、甲烷(CH4)、四氟化碳(CF4)、三氟化磷(PF3)、氟化二砷(As2F5)、銻(Sb)或銦(In)之至少一者佈植進入該基材的該摻質區域。
- 如請求項1至請求項3之任一項所述的方法,其中在該基材上形成該摻質區域進一步包含以下步驟:施加一基材偏壓電壓至該基材,同時形成該摻質區域。
- 如請求項1至請求項3之任一項所述的方法,其中在該電漿摻雜製程期間施加零電壓功率至該基材。
- 如請求項1至請求項3之任一項所述的方法,其中形成該覆蓋層進一步包含以下步驟:沉積一含矽材料於該摻質區域頂上。
- 如請求項6所述的方法,其中該含矽材料包含二氧化矽(SiO2)或碳化矽(SiC)之至少一者。
- 如請求項1至請求項3之任一項所述的方法,其中將該覆蓋層沉積至高達約100埃的厚度。
- 如請求項1至請求項3之任一項所述的方法,該方法進一步包含以下步驟:在攝氏約600度至約1300度的溫度下退火該摻質區域。
- 如請求項1至請求項3之任一項所述的方法,其中執行形成該摻質區域與在該摻質區域頂上形成該覆蓋 層之步驟而不暴露該基材至大氣。
- 如請求項10所述的方法,其中在相同的處理腔室中執行形成該摻質區域與在該摻質區域頂上形成該覆蓋層之步驟。
- 如請求項10所述的方法,該方法進一步包含以下步驟:只在該覆蓋層形成於該摻質區域頂上之後暴露該基材至該大氣。
- 如請求項1至請求項3之任一項所述的方法,該方法進一步包含以下步驟:使用一群集工具的一第一處理腔室在該基材上形成該摻質區域以及在該摻質區域頂上形成該覆蓋層;使用該群集工具上的一第二處理腔室或一遠端處理腔室在形成該覆蓋層後退火該摻質區域;以及使用該第一處理腔室在退火該摻質區域後移除該覆蓋層。
- 如請求項1至請求項3之任一項所述的方法,該方法進一步包含以下步驟:使用一群集工具的一第一處理腔室在該基材上 形成該摻質區域;使用該群集工具上的一第二處理腔室在該摻質區域頂上形成該覆蓋層;使用該群集工具上的一第三處理腔室或一遠端處理腔室在形成該覆蓋層後退火該摻質區域;以及使用該群集工具的一第四處理腔室移除該摻質區域頂上的該覆蓋層。
- 如請求項1至請求項3之任一項所述的方法,其中在相同的處理腔室中執行形成該摻質區域、形成該覆蓋層、減少該覆蓋層之該厚度與移除該覆蓋層之步驟。
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WO2012125317A3 (en) | 2012-12-06 |
WO2012125317A9 (en) | 2013-04-04 |
TW201239954A (en) | 2012-10-01 |
WO2012125317A2 (en) | 2012-09-20 |
US8501605B2 (en) | 2013-08-06 |
US20120238074A1 (en) | 2012-09-20 |
KR20140012727A (ko) | 2014-02-03 |
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