TWI480958B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI480958B
TWI480958B TW101123980A TW101123980A TWI480958B TW I480958 B TWI480958 B TW I480958B TW 101123980 A TW101123980 A TW 101123980A TW 101123980 A TW101123980 A TW 101123980A TW I480958 B TWI480958 B TW I480958B
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fin
active
gate
active region
semiconductor structure
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TW101123980A
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TW201332021A (zh
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Shao Ming Yu
Chang Yun Chang
Chih Hao Chang
Hsin Chih Chen
Kai Tai Chang
Ming Feng Shieh
Kuei Liang Lu
Yi Tang Lin
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體結構及其製造方法
本發明係關於半導體製作，且特別是關於一種半導體結構及其製造方法。
於積體電路工業之先進技術中，使用了應變半導體結構以增加通道內之載子遷移率而增強了電路表現。磊晶成長(epitaxy growth)為形成應變結構的方法之一。然而，磊晶成長對於主動區的結構及相關環境極為敏感。例如，會形成有晶面缺陷(facet defects)並限制了磊晶成長。因此，便需要一種積體電路結構及其製造方法，以解決上述問題。
因此，本發明提供了一種半導體結構，包括：一半導體基板；一隔離元件，形成於該半導體基板內；一第一主動區與一第二主動區，形成於該半導體基板內，其中該第一主動區與該第二主動區沿一第一方向沿伸並為該隔離元件所相分隔；以及一假閘極，設置於該隔離元件上，其中該假閘極沿著該第一方向自一側延伸至該第一主動區處以及自另一側延伸至該第二主動區處。
於一實施例中，上述半導體結構，更包括：一第一功能性閘極，設置於該第一主動區上以形成一第一場效電晶體；以及一第二功能性閘極，設置於該第二主動區上以形成一第二場效電晶體。
於另一實施例中，上述半導體結構更包括複數個第一磊晶元件，形成於該第一主動區上並為該第一功能性閘極 所相分隔。於又一實施例中，該半導體基板包括矽；該些第一磊晶元件包括矽鍺；以及該第一場效電晶體包括一P型場效電晶體與一N型場效電晶體其中之一，其中該些第一磊晶元件與該假閘極之間係為該半導體基板之一部所分隔。
於另一實施例中，上述半導體結構更包括複數個第二磊晶元件，形成於該第二主動區上並為該第二功能性閘極所相分隔。於又一實施例中，該些第二磊晶元件包括碳化矽；以及該第二場效電晶體包括包括該P型場效電晶體與該N型場效電晶體其中之另一，其中該些第二磊晶元件與該假閘極係藉由該半導體基板之另一部所分隔。
於又一實施例中，第一功能性閘極與該第二功能性閘極包括一高介電常數介電材料層以及位於該高介電常數介電材料層上之一金屬層。
於又一實施例中，該隔離元件係為依該第一方向沿伸一第一尺寸S1之一淺溝槽隔離元件。於另一實施例中，該第一主動區與該第二主動區為對準該第一方向之鰭樣主動區；以及該假閘極對準於垂直於該第一方向之一第二方向且於該第一方向上跨越有一第二尺寸S2，其中該第二尺寸大於該第一尺寸。
於又一實施例中，該假閘極沿伸至該第一主動區處並具有該第一方向上之一第一覆蓋尺寸Z1；以及該假閘極沿伸至該第二主動區處並具有該第一方向上之一第二覆蓋尺寸Z2，其中該S1、S2、Z1、Z2之間具有S2=S1+Z1+Z2之一關係。於又一實施例中，該假閘極包括一主閘堆疊物 以及設置於該主閘堆疊物之兩側之一閘間隔物；該主閘堆疊物具有於該第一方向上之一寬度W，且該閘間隔物具有一厚度T；以及該第二尺寸S2係等於W+2T。
本發明亦提供了另一實施例之一種半導體結構，包括：一矽基板；複數個第一鰭樣主動區，形成於該矽基板內並面向一第一方向；複數個第二鰭樣主動區，形成於該矽基板內且面向該第一方向；一淺溝槽隔離元件，形成於該矽基板內且設置於該些第一鰭樣主動區與該些第二鰭樣主動區之間；以及一假閘極，位於該淺溝槽隔離元件之上，其中該假閘極依該第一方向沿伸以自一側覆蓋該些第一鰭樣主動區及自另一側覆蓋該些第二鰭樣主動區。
於上述半導體結構之一實施例中，該些第一鰭樣主動區分別包括接觸該淺溝槽隔離元件之一第一端，而該些第二鰭樣主動區分別包括接觸該淺溝槽隔離元件之一第二端。
於另一實施例中，該淺溝槽隔離元件具有一第一方向上之一第一尺寸S1；該些第一端與該些第二端具有該第一方向上之一第一距離，其中該第一距離係等於該第一尺寸；以及該假閘極於該第一方向上跨越了一第二尺寸S2，而S2大於S1。
於又一實施例中，該假閘極與該些第一鰭樣主動區重疊，具有於該第一方向上之第一重疊尺寸Z1；該假閘極與該些第二鰭樣主動區重疊，具有於該第一方向上之第二重疊尺寸Z2；以及S1、S2、Z1與Z2之間具有S2=S1+Z1+Z2之一關係。
於又一實施例中，該淺溝槽隔離元件包括低於該些第一鰭樣主動區與該些第二鰭樣主動區之頂面之一頂面。
本發明亦提供了另一實施例之一種半導體結構之製造方法，包括：形成一隔離元件於一半導體基板內；形成一第一鰭樣主動區與一第二鰭樣主動區於該半導體基板內並為該隔離元件所分隔；以及形成一假閘極於該隔離元件上，其中該假閘極自一側沿該第一方向沿伸至該第一鰭樣主動區處以及自另一側沿該第一方向沿伸至該第二鰭樣主動區處。
於一實施例中，上述方法更包括形成磊晶成長之源極元件與汲極元件於該第一鰭樣主動區內。於另一實施例中，形成該假閘堆疊物包括形成具有多晶矽之第一閘極以及採用金屬以取代該多晶矽。
於又一實施例中，形成該第一鰭樣主動區與該第二鰭樣主動區於該半導體基板內包括：使用一第一光罩以定義一主動區；以及使用一第二光罩以定義一切割元件，以形成一硬罩幕，其中該硬罩幕包括定義該些第一鰭樣主動區與該些第二鰭樣主動區之數個開口。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了元件與設置情形之特定範例。然而，此些 元件與設置情形僅作為範例之用而非用於限制本發明。此外，本發明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。再者，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。
第1圖顯示了依據本發明之一實施例之一種半導體結構50之上視圖。第2圖為依據本發明之一實施例之半導體結構50之一局部上視圖。以下藉由第1圖與第2圖以解說半導體結構50及其製造方法。
於一實施例中，半導體結構50為一半導體晶圓之一部，或特別地為一半導體晶粒(或晶片)之一部。半導體結構50包括了一半導體基板52。於一實施例中，半導體基板52包括矽。或者，半導體基板52包括鍺或矽鍺。於其他實施例中，半導體基板52可使用其他半導體材料，例如鑽石、碳化矽、砷化鎵、GaAsP、AlInAs、AlGaAs、GaInP、或上述材料之適當組合。再者，半導體基板52可包括一塊狀半導體(bulk semiconductor)，例如塊狀矽，以及形成於此塊狀矽上之一磊晶矽層。
請參照第1圖，半導體結構50更包括數個主動區54，例如主動區54a與54b。於本實施例中，主動區54為鰭樣結構(fin-like structure)，以用於形成鰭樣場效電晶體(fin-like FETs)。於一特定實施例中，半導體結構50包括平 行地設置之數個鰭樣主動區，例如數個第一鰭樣主動區54a以及數個第二鰭樣主動區54b。此些第一鰭樣主動區54a與第二鰭樣主動區54b係為隔離元件(isolation features)所相分隔。於圖示之一範例中，此些第一鰭樣主動區54a係用於n型鰭樣場效電晶體(nFinFET)，而此些第二鰭樣主動區54b係用於p型鰭樣場效電晶體(pFinFET)。如淺溝槽隔離元件(STI features)之數種隔離元件可於形成鰭樣主動區時之製程中形成於半導體基板52上。
此些鰭樣主動區54係藉由適當技術所形成。於一範例中，鰭樣主動區的形成包括：形成數個淺溝槽隔離元件以定義出主動區之數個區域、蝕刻此些主動區內之半導體材料(例如矽)、以及於此些主動區內磊晶成長一半導體材料(例如矽)以形成此些鰭樣主動區54。於另一範例中，此些鰭樣主動區的形成包括：形成數個淺溝槽隔離元件以定義出此些主動區之數個區域，以及蝕刻並凹陷此些淺溝槽隔離元件，以突出此些而形成此些鰭樣主動區54。
於鰭樣主動區54上形成有數個閘堆疊物(gate stacks)。此些閘堆疊物包括用於場效電晶體之一或多個功能性閘堆疊物(functional gate stack)以及設置於隔離元件之上一假閘堆疊物(dummy gate strack)。於本實施例中，半導體結構50包括設置於此些第一鰭樣主動區54a上之一第一閘堆疊物56以及設置於此些第二鰭樣主動區54b上之一第二閘堆疊物58。第一閘堆疊物56與第二閘堆疊物58的設置係用於形成個別之場效電晶體(FET)，例如一n型場效電晶體與一p型場效電晶體。再者，半導體結構50包括設置 於淺溝槽隔離元件上且經過沿伸而部分地位於主動區54上之一假閘堆疊物60。特別地，假閘堆疊物60係設置於淺溝槽隔離元件上而覆蓋了此些主動區54之數個末端部，如第1圖所示。換句話說，此些鰭樣主動區54係沿伸至假閘堆疊物60處，進而使得此些鰭樣主動區54之末端部係位於假閘堆疊物60之下方。於本實施例中，此些第一鰭樣主動區54a係自一側而沿伸至假閘堆疊物60處，而此些第二鰭樣主動區54b係自另一側沿伸至假閘堆疊物60處，如此假閘堆疊物60覆蓋了此些第一鰭樣主動區54a之一端以及此些第二鰭樣主動區54b之一端。
於一實施例中，此些閘堆疊物56、58、60分別包括一主閘極62以及形成於對應之每一主閘極62的側壁上一閘間隔物64。閘堆疊物56、58、60之每一主閘極包括了一閘介電元件以及設置於此閘介電元件上之一閘電極。此閘介電元件包括一或多個介電材料，而此閘電極包括一或多個導電材料。上述閘間隔物包括一或多個介電材料。
請參照第2圖，以詳細解說假閘堆疊物之型態。基於簡化的目的，第2圖為第1圖內之半導體結構50之一部之一上視圖。於本實施例中，此些鰭樣主動區54係對準於一第一方向X，而此些閘堆疊物係對準於垂直此第一方向之一第二方向Y。閘堆疊物60包括了主閘極62以及位於側壁上之閘間隔物64。主閘極62包括了於第一方向上之一寬度X。閘間隔物64包括如第2圖所示之位於每一側之一厚度T。此些鰭樣主動區54a具有埋設於(位於其下)之假閘堆疊物60之數個末端部。此些第一鰭樣主動區54a之每一 埋設之末端部具有於第一方向上之一尺寸ZL。此些鰭樣主動區54b埋設於(位於其下)之假閘堆疊物60之數個末端部。此些第二鰭樣主動區54b之每一埋設之末端部具有於第一方向上之一尺寸ZR。此些第一鰭樣主動區54a與此些第二鰭樣主動區54b於第一方向上具有相分隔之一間隔尺寸S。上述定義之不同參數之間則滿足了一方程式S1+ZL+ZR=X+2T。於一實施例中，鰭樣主動區54之埋入端部之上述尺寸ZL與ZR約介於5-10奈米。於其他實施例中，假閘堆疊物60具有一寬度不同於功能性閘堆疊物之，例如功能性閘堆疊物56與58。此些參數ZL與ZR定義出了鰭樣主動區(54a或54b)與假閘堆疊物60之間的重疊情形。此些參數ZL與ZR亦定義了假閘堆疊物60之一一邊與位於假閘堆疊物60下方之隔離元件之一邊間的偏差值(offsets)。
第3圖為依據本發明之一實施例之半導體結構50沿著第1圖內線段AA’之一剖面圖。藉由下文以描述第3圖內之更多元件。半導體結構50包括了功能性閘堆疊物56與58，且更包括了設置於功能性閘堆疊物之間之一假閘堆疊物60。此假閘堆疊物60係形成於隔離元件68之上，並沿著第一方向X沿伸至此些鰭樣主動區54之末端部。
可藉由如離子佈值之適當技術於半導體基板52內設置多個摻雜元件(doping features)。舉例來說，可於主動區內形成一或多個摻雜井區70。於一實施例中，係於第一鰭樣主動區54a內形成一第一井區70a，以及於第二鰭樣主動區54b內形成一第二井區70b。於本實施例中，第一井區 70a包括了用於n型場效電晶體之p型摻質，而第二井區70b包括了用於p型場效電晶體之n型摻質。
半導體結構50包括用於應變效應之一或多個磊晶成長形成之半導體元件(磊晶元件)72，以增強電路表現。於一實施例中，半導體結構50包括了設置於第一功能性閘極56兩側之磊晶元件72a與72b。於另一實施例中，半導體結構50包括了設置於第二功能性閘極58兩側之磊晶元件72c與72d。於本實施例中，則顯示了磊晶元件72a、72b、72c、72d。特別地，磊晶元件72a與72b包括了形成於主動區54a內之具有可加強n型場效電晶體表現之應變效應之磊晶成長的碳化矽，而磊晶元件72c與72d包括形成於主動區54b內之具有可加強p型場效電晶體表現之應變效應之磊晶成長的矽鍺。由於假閘堆疊物60與隔離元件68間之偏差(offset)情形，此些磊晶元件可沿伸至假閘堆疊物60處但為隔離元件68所相分隔。
此些磊晶元件的形成包括：蝕刻半導體基板以形成數個凹口，以及磊晶成長如矽鍺或碳化矽以形成相關之磊晶元件。於一實施例中，磊晶元件72可經過成長並突出於半導體基板52之表面。
於形成凹口之蝕刻程序中，此些凹口係由於假閘堆疊物60而與隔離元件68產生偏差，因而不會露出了隔離元件68的側壁，如此使得凹口具有僅為半導體材料之表面(於本實施例中為矽)。如此，磊晶成長可大體發生於凹口內的表面進而可消除晶面缺陷。
而於既存方法之中，此些凹口係露出了隔離元件(淺溝 槽隔離元件)的表面。由於磊晶成長並不會於如氧化矽之介電材料的隔離元件的表面成長。因此，於磊晶元件與隔離元件之間會形成孔洞缺陷(void defects)。此些孔洞缺陷可稱為晶面缺陷(facet defects)。相反的，在此揭示之半導體結構50及其相關方法則消除了上述晶面缺陷。
半導體結構50更包括形成於主動區54(例如54a與54b)內且分別設置於對應之功能性閘堆疊物(56或58)的側壁上之數個源極與汲極元件74。此些源極與汲極元件74包括了大體對準於對應之主閘堆疊物之數個輕度摻雜汲極(LDD)元件以及對準於對應之閘間隔物64之數個重度摻雜源極/汲極。此淺摻雜汲極元件與重度摻雜源極汲極元件統稱為源極與汲極元件74。此些源極與汲極元件74係藉由多個離子佈植步驟所形成。於本實施例中，位於第一主動區54a內之源極與汲極元件74具有例如磷之n型摻質，以形成n型場效電晶體。於第二主動區54b內之源極與汲極元件74具有如硼之p型摻質，以形成p型場效電晶體。
此些閘堆疊物(包括功能性閘堆疊物56與58以及假閘堆疊物60)包括了主閘極62以及閘間隔物64。每一主閘極包括了一閘介電元件62a以及設置於閘介電元件62a上之一閘電極62b。閘介電元件62a包括設置於半導體基板52上之一或多個介電材料。閘電極62b包括一或多個導電材料。於一實施例中，閘介電元件62a包括氧化矽，而閘電極62b包括多晶矽，其藉由包括沉積與圖案化之一程序所形成。而上述圖案化包括了微影製程與蝕刻製程。
於另一實施例中，閘介電元件62a包括一高介電常數 介電材料層，而閘電極62b包括一金屬層，因而可稱為一高介電常數金屬閘(high k metal gate)。高介電常數金屬閘可藉由適當技術所形成，例如一閘極最後(gate last)製程，其首先形成多晶矽之閘堆疊物，並接著採用蝕刻沉積與研磨而取代多晶矽材料。於本實施例中，閘介電元件62a可於半導體基板與高介電常數介電材料層之間額外地設置一中間層。依據電晶體之類型(n型或p型)，閘電極62b可包括具有適當功函數之一金屬層，以針對個別電晶體而調整臨界電壓，進而其可稱為一功含數金屬。於上述情形中，用於n型場效電晶體之功函數金屬不同於用於p型場效電晶體之功函數金屬。
於又一實施例中，功能性閘堆疊物56與58包括了用於閘介電層之高介電常數介電層以及用於閘電極之金屬層，但假閘堆疊物60則包括用於閘介電層之氧化矽以及用於閘電極之多晶矽。
第4圖為一流程圖，顯示了依據本發明之一或多個實施例之形成半導體結構50之一種方法100。方法100係參照第1-4圖等圖式而進行說明。
方法100起始於一步驟102，其提供一半導體基板52。半導體基板52包括矽或其他之適當半導體材料。
方法100接著繼續步驟104，形成數個鰭樣主動區54。於一實施例中，此些鰭樣主動區54係藉由包括形成淺溝槽隔離物以定義出用於此些主動區之區域以及回蝕刻淺溝槽隔離物以突出此些主動區而形成此些鰭樣主動區54之一程序。
於此實施例中，將藉由以下第5圖之流程圖以說明依據本發明之不同實施例之形成鰭樣主動區54之一較詳細實施例，以形成鰭樣主動區。
如步驟112中，於半導體基板上形成一硬罩幕(hard mask)。於一範例中，硬罩幕包括一氧化矽薄膜(墊氧化物)與位於墊氧化物上之一氮化矽薄膜。硬罩幕層可藉由適當技術形成。於一範例中，氧化矽係由熱氧化法所形成，而氮化矽係由化學氣相沉積所形成。
於步驟114中，圖案化此硬罩幕層以形成數個開口。經圖案化之硬罩幕層定義出用於隔離元件之數個區域以及用於主動區之數個區域。特別的，經圖案化之硬罩幕層內之此些開口定義出此些隔離元件之數個區域。硬罩幕層係藉由微影與蝕刻製程而圖案化。
為了降低導線末端縮短(line end shortening)與邊角圓滑化(corner rounding)問題，可使用兩道光罩以圖案化此硬罩幕層。採用第一光罩以定義出鰭樣導線(fin lines)，以及採用第二光罩以定義出導線末端切割圖案並形成了末端與端之間的間距。如第6圖顯示了一硬罩幕層之一上視圖，第一光罩定義出了數個鰭樣元件126，而第二光罩定義出導線末端切割元件128，以形成半導體結構50之鰭樣主動區54。於一範例中，此第一光罩定義出對準於一第一方向X之數個鰭樣元件，而第二光罩定義出對準於垂直於第一方向X之一第二方向Y之一導線末端切割元件128。
於一實施例中，上述兩光罩係於一雙重曝光程序中所應用。於硬罩幕層上塗佈一阻劑層。分別利用此第一光罩 與第二光罩依序施行兩次曝光。接著顯影經過兩次曝光之此阻劑層，以形成具有數個開口定義於其內之圖案化阻劑層。接著施行一蝕刻程序以穿過圖案化阻劑層之此些開口以蝕刻硬罩幕層。上述微影程序包括其他步驟，例如軟烤、曝光後烘烤、及/或硬烤。上述蝕刻製程可包括兩蝕刻步驟，以分別蝕刻氮化矽與氧化矽。
於另一實施例中，上述兩光罩可應用於一雙重曝光與雙重蝕刻程序中。使用此第一光罩圖案化(包括塗佈、曝光與顯影)一第一阻劑層。接著進行一蝕刻程序以穿透第一阻劑層之開口而蝕刻硬罩幕層。同樣地，採用此第二光罩圖案化一第二阻劑層。接著施行一蝕刻製程以穿透第二阻劑層之此些開口而蝕刻硬罩幕層。
於步驟116中，穿透硬罩幕層之開口而蝕刻半導體基板，以於半導體溝槽內形成數個溝槽。進而將硬罩幕層之圖案轉移至半導體基板處。
於步驟118中，半導體基板之溝槽為一或多個介電材料所填入，以形成數個淺溝槽隔離元件。於一實施例中，此些淺溝槽隔離元件包括氧化矽。此氧化矽可藉由一化學氣相沉積程序而填入於溝槽中。於不同實施例中，氧化矽可藉由高密度電漿化學氣相沉積(HDPCVD)所形成。氧化矽亦可藉由高深寬比程序(HARP)所形成。於其他實施例中，此些溝槽隔離元件可包括多膜層結構。於實施例中，此些淺溝槽隔離元件包括其他適當材料，例如氮化矽或氮氧化矽。
於一實施例中，接著施行如化學機械研磨(CMP)之一 研磨程序，以移除位於半導體基板上之過量材料並平坦化此半導體基板。
於步驟120中，接著回蝕刻此些淺溝槽隔離元件，以凹陷此些淺溝槽隔離元件，並使得數個半導體部(即矽部)相對於經凹陷之淺溝槽隔離元件為突出的，進而形成數個鰭樣主動區。如此，此些淺溝槽隔離元件之頂面係低於此些鰭樣主動區之頂面。
請再次參照第4圖，於步驟104中形成數個鰭樣主動區之後，方法100可接著繼續施行步驟106以形成數個閘堆疊物，其包括數個功能性閘堆疊物(56與58)與一假閘堆疊物60。如第3圖所示，此些閘堆疊物(包括功能性閘堆疊物56與58與假閘堆疊物60)包括了主閘極62以及閘間隔物64。每一主閘極62包括一閘介電元件62a以及設置於此閘介電元件62a上之一閘電極62b。於不同實施例中，閘堆疊物可包括用於閘電極之多晶矽或金屬材料，以及包括用於閘介電層之氮化矽及/或高介電常數介電材料。當閘堆疊物包括高介電常數介電材料與金屬(通稱為高介電常數金屬閘)時，此高介電常數金屬閘的形成可採用閘極先行形成製程(gate-first process)，其為於此步驟中直接設置與圖案化一高介電常數介電材料與一金屬。或者，可藉由其他技術形成高介電常數金屬閘，例如於其他實施例中此用閘極最後製程(gate-last process)或高介電常數最後製程(high-k-last process)。
方法100接著進行步驟108，於主動區54(例如54a與54b)內形成源極與汲極元件74。此些源極與汲極元件分別 設置於相對應之功能性閘堆疊物(56或58)的側邊。於一實施例中，源極與汲極元件74包括大體對準於相對應之主閘堆疊物之數個輕度摻雜汲極(LDD)元件以及對準於相對應之閘間隔物64之重度摻雜源極與汲極(S/D)。此些源極與汲極元件74係藉由適當技術(例如離子佈值)所形成，並接著施行一熱回火以活化之。於本實施例中，於第一主動區54a內之源極與汲極元件74包括了用於形成n型場效電晶體之n型摻質。於第二主動區54b內之源極與汲極元件74包括了用於形成p型場效電晶體之p型摻質。
閘堆疊物的形成以及源極與汲極元件的形成可整合於單一步驟內。舉例來說，重度摻雜源極與汲極可於形成閘間隔物之後形成。本方法之一實施例為如下所述之形成閘堆疊物與源極/汲極元件。
於基板上形成閘材料層且於經過圖案化形成閘堆疊物。上述閘材料層包括了一中間層(如氧化矽)、設置於中間層上之一高介電常數介電材料層、以及位於高介電常數介電材料層上之一多晶矽層。上述圖案化之技術包括了微影製程與蝕刻。可使用一硬罩幕做為蝕刻罩幕以圖案化上述閘材料層。
接著藉由離子佈值形成淺摻雜汲極(LDD)元件，並接著施行熱回火以活化之。藉由沈積與乾蝕刻等製程於閘堆疊物的側壁上形成閘間隔物。特別地，假閘堆疊物60(包括閘間隔物)係形成於淺溝槽隔離元件68之上並延伸以覆蓋鰭樣主動區54之末端部。於本實施例中，假閘堆疊物60覆蓋了位於一側之鰭樣主動區54a的末端部，以及覆蓋了 另一側之鰭樣主動區54b之末端部。
接著蝕刻半導體基板以形成數個凹口。於本實施例中，採用適當蝕刻化學品蝕刻矽基板。此些凹口係形成於矽基板內，並與淺溝槽隔離元件68之間藉由矽所分隔。淺溝槽隔離元件68之一邊與假閘堆疊物60之一邊之間的偏差值分別為ZL與ZR，如第2圖所示。經過設計，此些偏差值ZL與ZR需為足夠使得此些凹口不會碰觸與露出淺溝槽隔離元件68。
接著施行磊晶成長(或磊晶地成長)以形成一磊晶成長元件，其具有不同於基板之半導體材料，提供適當之應變效果以增強通道遷移率。於一實施例中，於此些凹口內磊晶地成長用於p型場效電晶體之矽鍺。於另一實施例中，於此些凹口內磊晶地成長用於n型場效電晶體之碳化矽。
上述磊晶成長可成長其表面大體水平於或高於矽表面之磊晶元件，因而使得磊晶元件可為突出。於磊晶成長之後可藉由離子佈值形成重度摻雜源極與汲極。
於另一實施例中，可移除凹口蝕刻所使用之閘間隔物，並於閘堆疊物的側壁上形成一第二閘間隔物。因此，可調整第二閘間隔物以偏移重度摻雜源極與汲極，而第一閘間隔物則可調整鰭樣端部與假閘堆疊物間之重疊偏差情形。
於又一實施例中，可於磊晶成長時形成重度摻雜源極與汲極，其中磊晶成長元件係於磊晶成長時臨場地(in-situ)被摻雜。磊晶成長的前驅物包括了於磊晶成長時可同時導入摻質之化學品。
於方法100的施行之前、之中或之後可施行其他製程步驟。於一實施例中，可於基板與閘堆疊物之上形成一層間介電層(ILD)。此層間介電層係藉由一適當技術沈積，例如化學氣相沈積。此層間介電層包括一介電材料，例如氧化矽、低介電常數介電材料或其組合。接著可施行一化學機械研磨以平坦化此層間介電層的表面。於一範例中，於上述化學機械研磨製程後將露出閘堆疊物，以用於後續製程步驟。於形成高介電常數金屬閘之一閘極最後製程中，於形成層間介電層之後，藉由一或多個金屬層以替代多晶矽層。更精確地說，於閘堆疊物內之多晶矽層係藉由蝕刻而移除，進而形成了閘溝槽。接著利用一或多個金屬材料以填滿此些閘溝槽，以形成金屬閘堆疊物。於本實施例中，於閘溝槽內沈積具有一適當功函數之一第一金屬，以及於第一金屬之上沈積一第二金屬以填滿閘溝槽。此第一金屬亦稱之為一功函數金屬。第二金屬可包括鋁或鎢。
於高介電常數最後(high-k last)製程中，係藉由蝕刻而同時移除閘介電材料與多晶矽。接著，填入高介電常數介電材料與金屬以形成高介電常數金屬閘堆疊物。
於另一範例中，可更於基板之上形成一內連結構，而此內連結構係用於耦接數個電晶體與其他元件以形成功能性電路。上述內連結構包括了多個導電元件，例如用於水平連接之金屬導線以及用於垂直連接之接觸物/內連物。此些內連元件可採用包括銅、鎢與矽化物之多種導電材料。於一範例中，可使用一鑲嵌製程以形成銅基多重膜層內連結構。於另一實施例中，係於接觸孔內使用鎢以形成鎢插 拴。
雖然未於圖式中顯示，可更形成用於接觸之矽化物以及多膜層內連物等多種裝置元件及其相關製作。於一範例中，矽化物之接觸膜層包括鎳矽化物、鈷矽化物、鎢矽化物、鉭矽化物、鈦矽化物、鉑矽化物、鉺矽化物、鈀矽化物或其組合。閘間隔物可具有一多層膜層夠且可包括氧化矽、氮化矽、氮氧化矽或其他介電材料。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。舉例來說，半導體結構50包括鰭樣主動區。然而，本發明亦適用於二維電路，其中主動區與淺溝槽隔離元件為大體共平面的。如前所示，可採用假閘堆疊物與主動區之末端部的重疊情形以當於場效電晶體中使用用於應變效應之磊晶成長元件時降低晶面缺陷。於另一範例中，假閘堆疊物60具有不同於功能性閘堆疊物之一寬度，使得介於假閘堆疊物與主動區間之重疊情形為可調整以有效地避免晶面問題。於又一範例中，於功能性閘堆疊物包括高介電常數介電材料與金屬時，假閘堆疊物包括如氧化矽與多晶矽之不同材料。於另一實施例中，僅於p型場效電晶體內形成矽鍺磊晶元件，而n型場效電晶體具有形成於矽基板內之源極與汲極元件。
50‧‧‧半導體結構
52‧‧‧半導體基板
54‧‧‧鰭樣主動區
54a‧‧‧第一鰭樣主動區
54b‧‧‧第二鰭樣主動區
56‧‧‧第一閘堆疊物
58‧‧‧第二閘堆疊物
60‧‧‧假閘堆疊物
62‧‧‧主閘極
62a‧‧‧閘介電元件
62b‧‧‧閘電極
64‧‧‧閘間隔物
68‧‧‧隔離元件
70‧‧‧摻雜井區
70a‧‧‧第一井區
70b‧‧‧第二井區
72a、72b、72c、72d‧‧‧磊晶元件
74‧‧‧源極與汲極元件
100‧‧‧半導體結構之製造方法
102、104、106、108、112、114、116、118、120‧‧‧步驟
126‧‧‧鰭樣元件
128‧‧‧導線末端切割元件
ZL、ZR‧‧‧尺寸
X‧‧‧第一方向
Y‧‧‧第二方向
T‧‧‧厚度
第1圖為一上視圖，顯示了依據本發明之一實施例之 一種半導體結構；第2圖為一局部上視圖，顯示了依據本發明之一實施例之如第1圖所示之半導體結構；第3圖為一剖面圖，顯示了依據本發明之一實施例之第1圖內AA’線段所示之半導體結構；第4圖為一流程圖，顯示了第1圖所示之半導體結構之製造方法；第5圖為一流程圖，顯示了第1圖所示之半導體結構內之一鰭樣主動區之製造方法；以及第6圖為一示意圖，顯示了用於形成於第1圖所示半導體結構內之鰭樣主動區之一硬罩幕。
50‧‧‧半導體結構
52‧‧‧半導體基板
54a‧‧‧第一鰭樣主動區
54b‧‧‧第二鰭樣主動區
56‧‧‧第一閘堆疊物
58‧‧‧第二閘堆疊物
60‧‧‧假閘堆疊物
62‧‧‧主閘極
64‧‧‧閘間隔物

Claims (10)

  1. 一種半導體結構，包括：一半導體基板；一隔離元件，形成於該半導體基板內；一第一主動區與一第二主動區，形成於該半導體基板內，其中該第一主動區與該第二主動區沿一第一方向沿伸並為該隔離元件所相分隔；一第一井區形成於該第一主動區內與一第二井區形成於該第二主動區內，其中該第一井區與該第二井區包括不同類型之摻質；以及一假閘極，設置於該隔離元件上，其中該假閘極沿著該第一方向自一側延伸至該第一主動區處以及自另一側延伸至該第二主動區處。
  2. 如申請專利範圍第1項所述之半導體結構，更包括：一第一功能性閘極，設置於該第一主動區上以形成一第一場效電晶體；以及一第二功能性閘極，設置於該第二主動區上以形成一第二場效電晶體。
  3. 如申請專利範圍第2項所述之半導體結構，其中該第一功能性閘極與該第二功能性閘極包括一高介電常數介電材料層以及位於該高介電常數介電材料層上之一金屬層。
  4. 如申請專利範圍第1項所述之半導體結構，其中該隔離元件係為依該第一方向沿伸一第一尺寸S1之一淺溝槽隔離元件。
  5. 如申請專利範圍第4項所述之半導體結構，其中：該第一主動區與該第二主動區為對準該第一方向之鰭樣主動區；以及該假閘極對準於垂直於該第一方向之一第二方向且於該第一方向上跨越有一第二尺寸S2，其中該第二尺寸大於該第一尺寸。
  6. 如申請專利範圍第5項所述之半導體結構，其中：該假閘極沿伸至該第一主動區處並具有該第一方向上之一第一覆蓋尺寸Z1；以及該假閘極沿伸至該第二主動區處並具有該第一方向上之一第二覆蓋尺寸Z2，其中該S1、S2、Z1、Z2之間具有S2=S1+Z1+Z2之一關係。
  7. 一種半導體結構，包括：一矽基板；複數個第一鰭樣主動區，形成於該矽基板內並面向一第一方向；複數個第二鰭樣主動區，形成於該矽基板內且面向該第一方向；一第一井區形成於該些第一主動區內與一第二井區形成於該些第二主動區內，其中該第一井區與該第二井區包括不同類型之摻質；一淺溝槽隔離元件，形成於該矽基板內且設置於該些第一鰭樣主動區與該些第二鰭樣主動區之間；以及一假閘極，位於該淺溝槽隔離元件之上，其中該假閘極依該第一方向沿伸以自一側覆蓋該些第一鰭樣主動區及 自另一側覆蓋該些第二鰭樣主動區。
  8. 如申請專利範圍第7項所述之半導體結構，其中該些第一鰭樣主動區分別包括接觸該淺溝槽隔離元件之一第一端，而該些第二鰭樣主動區分別包括接觸該淺溝槽隔離元件之一第二端。
  9. 如申請專利範圍第8項所述之半導體結構，其中：該淺溝槽隔離元件具有一第一方向上之一第一尺寸S1；該些第一端與該些第二端具有該第一方向上之一第一距離，其中該第一距離係等於該第一尺寸；以及該假閘極於該第一方向上跨越了一第二尺寸S2，而S2大於S1。
  10. 一種半導體結構之製造方法，包括：形成一隔離元件於一半導體基板內；形成一第一鰭樣主動區與一第二鰭樣主動區於該半導體基板內並為該隔離元件所分隔；形成一第一井區於該第一主動區內與一第二井區於該第二主動區內，其中該第一井區與該第二井區包括不同類型之摻質；以及形成一假閘極於該隔離元件上，其中該假閘極自一側沿該第一方向沿伸至該第一鰭樣主動區處以及自另一側沿該第一方向沿伸至該第二鰭樣主動區處。
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