TWI456691B - 基板之處理方法，電子裝置之製造方法及程式 - Google Patents

基板之處理方法，電子裝置之製造方法及程式 Download PDF

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TWI456691B
TWI456691B TW095104740A TW95104740A TWI456691B TW I456691 B TWI456691 B TW I456691B TW 095104740 A TW095104740 A TW 095104740A TW 95104740 A TW95104740 A TW 95104740A TW I456691 B TWI456691 B TW I456691B
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insulating film
forming
low dielectric
film
photoresist layer
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Eiichi Nishimura
Kenya Iwasaki
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Tokyo Electron Ltd
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Claims (12)

  1. 一種基板之處理方法，係具有含碳之低介電率絕緣膜，該低介電率絕緣膜係具有碳濃度比該低介電率絕緣膜減低之表面損傷層的除去基板之上述低介電率絕緣膜之上述表面損傷層的處理方法，具備以下步驟：表面損傷層暴露步驟，使上述表面損傷層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及表面損傷層加熱步驟，使暴露於上述混合氣體環境之表面損傷層加熱至特定溫度。
  2. 如申請專利範圍第1項之基板之處理方法，其中上述表面損傷層暴露步驟，係對上述基板施予無電漿蝕刻處理。
  3. 如申請專利範圍第1項之基板之處理方法，其中上述表面損傷層暴露步驟，係對上述基板施予乾燥洗淨處理。
  4. 如申請專利範圍第1項之基板之處理方法，其中上述混合氣體中上述氟化氫對上述氨之體積流量比為1~1/2，上述特定壓力為6.7×10-2 ~4.0Pa。
  5. 如申請專利範圍第1項之基板之處理方法，其中上述特定溫度為80~200℃。
  6. 如申請專利範圍第1項之基板之處理方法，其中另具有：生成物產生條件決定步驟，用於測定具有上述表面損傷層之低介電率絕緣膜之形狀，依該測定之形狀決定上述混合氣體中上述氟化氫對上述氨之體積流量比與 上述特定壓力之中至少之一。
  7. 一種基板之處理方法，係具有至少由光阻劑膜或硬質遮罩膜構成之遮罩膜，該遮罩膜具有表面損傷層的除去基板之上述遮罩膜之上述表面損傷層的處理方法，具備以下步驟：表面損傷層暴露步驟，使上述表面損傷層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及表面損傷層加熱步驟，使暴露於上述混合氣體環境之表面損傷層加熱至特定溫度。
  8. 一種電子裝置之製造方法，具備以下步驟：低介電率絕緣膜形成步驟，在半導體基板上所形成由下部電極、容量絕緣膜及上部電極構成之電容器上，形成含碳之低介電率絕緣膜；光阻層形成步驟，於上述形成之低介電率絕緣膜上形成特定圖案之光阻層；電漿加工形成步驟，使用該形成之光阻層，藉由電漿處理，於上述低介電率絕緣膜加工成形到達上述上部電極之連接孔；連接孔表面暴露步驟，使上述加工成形之連接孔表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及連接孔表面加熱步驟，使暴露於上述混合氣體環境之連接孔表面加熱至特定溫度。
  9. 一種電子裝置之製造方法，具備以下步驟： 層間絕緣膜形成步驟，在半導體基板上形成含碳之低介電率絕緣膜，於該低介電率絕緣膜上形成碳濃度低於上述低介電率絕緣膜的其他絕緣膜而形成層間絕緣膜；電漿加工形成步驟，藉由電漿處理於上述層間絕緣膜加工成形配線溝；配線溝表面暴露步驟，使至少上述低介電率絕緣膜中之配線溝表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；配線溝表面加熱步驟，使暴露於上述混合氣體環境之配線溝表面加熱至特定溫度；其他絕緣膜除去步驟，除去上述其他絕緣膜；及配線形成步驟，於上述配線溝導入導電材料而形成配線。
  10. 如申請專利範圍第9項之電子裝置之製造方法，其中具有：光阻層形成步驟，於上述其他絕緣膜上形成光阻層；及去灰步驟，除去該形成之光阻層；於該去灰步驟，使上述光阻層於特定壓力下暴露於含氨及氟化氫之混合氣體環境中，使暴露於上述混合氣體環境之上述光阻層加熱至特定溫度。
  11. 一種電子裝置之製造方法，具備以下步驟：導電膜形成步驟，於半導體基板上形成含矽之導電 膜；低介電率絕緣膜形成步驟，在該形成之導電膜上，形成含碳之低介電率絕緣膜；光阻層形成步驟，於上述形成之低介電率絕緣膜上形成特定圖案之光阻層；電漿加工形成步驟，使用該形成之光阻層，藉由電漿處理，於上述低介電率絕緣膜加工成形到達上述上部電極之連接孔；連接孔表面暴露步驟，使上述加工成形之連接孔表面，於特定壓力下暴露於含氨及氟化氫之混合氣體環境中；及連接孔表面加熱步驟，使暴露於上述混合氣體環境之連接孔表面加熱至特定溫度；去灰步驟，除去上述光阻層；及配線形成步驟，於上述連接孔導入導電材料而形成配線。
  12. 一種電子裝置之製造方法，具備以下步驟：導電膜形成步驟，於半導體基板上形成含矽之導電膜；低介電率絕緣膜形成步驟，在該形成之導電膜上，形成含矽之低介電率絕緣膜；反射防止膜形成步驟，在該形成之低介電率絕緣膜上，形成反射防止膜；光阻層形成步驟，於該形成之反射防止膜上形成對應 所期望之閘門形狀之圖案的光阻層；反射防止膜除去步驟，使用該形成之光阻層，藉由蝕刻上述反射防止膜進行部份地除去，使上述低介電率絕緣膜露出；低介電率絕緣膜除去步驟，使用上述形成之光阻層，藉由電漿處理除去上述露出之低介電率絕緣膜，使上述導電膜露出；低介電率絕緣膜側面暴露步驟，於特定壓力下，將於上述低介電率絕緣膜除去步驟中未被除去之上述光阻層下的於上述低介電率絕緣膜除去步驟中未被除去之上述光阻層下的上述低介電率絕緣膜之部份的側面暴露於含氨及氟化氫之混合氣體環境中；低介電率絕緣膜側面加熱步驟，使暴露於上述混合氣體環境之上述低介電率絕緣膜之部份的側面加熱至特定溫度；導電膜除去步驟，藉由蝕刻除去未被覆蓋於上述導電膜中上述未被除去之低介電率絕緣膜之部份的導電膜。
TW095104740A 2005-02-14 2006-02-13 基板之處理方法，電子裝置之製造方法及程式 TWI456691B (zh)

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