TW504799B - Copper line fabrication method - Google Patents

Abstract

The present invention relates to a fabrication method for copper line in semiconductor devices. An amorphous silicon material is used to form the structure of metal lines and inter-metal plugs of a manufactured device. A copper contact displacement technique is employed to substitute the amorphous silicon material and, thus, to form the copper structure containing copper lines and copper via plugs. In accordance to the present invention, a development bottleneck of the dual damascene process can be overcome, plugs of high aspect ratio can be formed easily, copper barrier layer is no longer deposited, and dishing defect of copper line planarization by chemical mechanical polishing can be resolved.

Description

504799 A7 B7 V. Description of the Invention (1) Field of the Invention The present invention relates to a method for manufacturing a copper wire, and more particularly to a method for manufacturing a copper wire using copper contact replacement technology. BACKGROUND OF THE INVENTION Generally speaking, the operating speed of an integrated circuit chip decreases as the multiplied value of the resistance value of the connecting wires between the components and the dielectric value between the wires increases, the so-called RC delay. Low resistance, so using copper as the interconnect wire can have higher chip operation speed. In addition, copper has a higher electron migration resistance, which can improve the life and stability of the components it forms. Due to the characteristics of copper metal, it is not yet possible to form so-called copper metal lines by traditional metal etching methods. Most of the industry uses the dual damascene process of copper wires developed by IB M company to form copper. The structure of the wire. The copper wire dual damascene process is used to replace the current process using aluminum-copper alloy as the metal wire. It belongs to the back-end process of wafer manufacturing (Back_End Of Line; BEOL). plug), and depending on the number of metal line layers of the component design, it may need to be repeated several times. Figures 1 (a) to 1 (f) are the structural diagrams of the conventional copper wire double-inlaying process at each step. In FIG. 1 (a), a semiconductor device 10 includes a substrate 102, a first nitride layer 104, a first dielectric layer 106, a second silicon nitride layer 108, and a second dielectric. Layer 110. The substrate 102 can be a wafer (interlayer dielectric) (ILD) contact plug structure (not shown), or a wafer can be subjected to multiple interconnection processes (multilevel H: \ HU \ TYS \ NDL said \ Revised 75134.DOC _ 4 — This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 504799 A7 B7 V. Description of invention (2)

The structure in Interconnects), that is, the structure of a certain Inter Metal Dielectric (IMD) and its via plug. The first dielectric layer 106 and the second dielectric layer 110 may be composed of a low-k dielectric material. The low-k dielectric material may be an inorganic material, such as Porous oxidized particles, or organic polymer polymers, can be formed by chemical vapor deposition (CVD) or spin on methods. In FIG. 1 (b), a photoresist (not shown in the figure) is used to define the interlayer hole area between the metal layers, and the second dielectric layer 1 10, the second silicon nitride layer 108, the first silicon nitride layer are sequentially etched. A dielectric layer 106 and the first silicon nitride layer 104 are stopped on the surface of the substrate 102. Next, another trench (not shown) is used to define the trench region of the metal line, and the second dielectric layer 1 1 0 is etched and stopped at the second silicon nitride layer 108. The second silicon nitride layer 108 is used as an etch stop layer. In FIG. 1 (c), a copper barrier layer 112 and a copper seed layer of a button or a nitride button are deposited by physical vapor deposition (PVD) or CVD. 1 1 4. The copper barrier layer 112 can prevent copper metal from entering the first dielectric layer 106 and the second dielectric layer 1 10 through diffusion to cause leakage current of the device, and the copper seed layer 1 1 4 is used as an electrode for subsequent copper plating. In FIG. 1 (d), a copper metal layer 1 1 6 is plated. In FIG. 1 (e), a planarization process is performed by a chemical mechanical polishing (CMP) method, and the copper metal layer 1 1 6, the copper seed layer 1 1 4, and the copper barrier are polished away. Layer 1 1 2. In Fig. 1 (f), a silicon nitride layer 1 1 8 is used as a barrier layer by C V D method. H: \ HU \ TYS \ NDL said \ Has been corrected 75134.DOC 1 5 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 504799 A7

The technical development bottlenecks of the copper wire after double inlaying process are as follows: (1) As the width of the wire of the element gradually decreases, the aspect ratio of the interlayer hole between the wires gradually increases, thus increasing its micro Difficulties in shadow and etching processes. (2) For different low-k dielectric materials, different etching processes must be used, and after the dielectric material is etched, the photoresist ashing and residue removal cleaning processes are easily caused. The dielectric characteristics of the dielectric material are deteriorated. In addition, for the currently developed organic dielectric materials, a hard mask is required for etching. (3) The coating of the copper barrier layer 112 and the copper seed layer 114 and the subsequent copper plating process, Both increase the difficulty of uniform coverage with the vias and trenches of high aspect ratio. For example, the copper seed layer 1 1 4 generally formed by the p V D method has a characteristic of thinner sidewalls. (4) The rate of copper electroplating will change with the thickness of the copper seed layer 114. Therefore, if the control is not proper, it is easy to seal the hole of the interlayer hole and leave holes in the interlayer hole, causing filling. Poor question. (5) When chemical mechanical polishing is performed, problems such as shallow dishing of the surface of the steel metal layer 6 and excessive erosion of the second dielectric layer 11 may be caused. (6) For a porous dielectric material with a lower dielectric constant, it is easy to form a first dielectric layer 106 and a second dielectric layer 1 10 composed of the dielectric material after engraving. HAHU \ TYS \ NDL said that the side walls caused porosity and increased the coverage. \ 75134.DOC-g-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm).

Binding

Wire 504799 A7 B7 Five invention descriptions (4 The difficulty of the copper barrier layer 1 12 and the copper seed layer 1 丨 4. Brief description of the invention The purpose of the present invention is to provide a copper wire manufacturing method to overcome the current copper wire double Difficulties encountered in the damascene process. The present invention uses a conventional copper contact replacement technology to integrate into the copper wire process to replace the current copper electrical bonding method. The steel contact replacement technology is disclosed in "Selective Copper Metallization by Electrochemical Contact Displacement with Amorphous Silicon Film11 ^ Electrochemical and Solid-State Letters »4 (7) C 4 7-C 4 9 '2 0 01, which uses a copper sulfate Solution, soak the wafer at room temperature, and replace an amorphous silicon layer with a copper metal layer. The buffer oxide etching solution is composed of a mixed solution of hydrofluoric acid (HF) and ammonia fluoride (NH4F) i The advantages of the present invention are as follows: (1) The structure of the via hole plug and the metal wire with the required high aspect ratio can be easily achieved without requiring difficult etching. (2) The present invention Using silicon nitride to form a silicon nitride layer as a copper barrier layer can easily overcome problems such as uniformity encountered when covering the copper barrier layer. (3) Replace copper plating and chemical mechanical polishing with copper contact replacement technology The manufacturing process can avoid the problems of poor filling and uniformity of copper electroplating, as well as the shallow dishing of the surface of steel wires caused by chemical mechanical polishing. HAHU \ TYS \ NDL said \ corrected 75134.DOC This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 5. Description of the invention (5) ⑷ Porous dielectric materials with low dielectric constant can be used. ⑺ Can form homogeneous dielectric The quality layer, that is, no need to engrav the stop layer between the two dielectric layers in the double damascene process of steel wires, can reduce the adhesion problem caused by different materials and the interface leakage between copper wires. Copper of the invention A method for making a wire includes: ⑴ deposition-a barrier layer on a substrate surface; ⑺ cover-an amorphous layer; (meaning at least-a via hole region, etching the amorphous silicon layer outside the via hole region; (4 Define at least one gold Belonging to the line area 4, the amorphous layer and the early P resist layer outside the metal line area are etched away, (5) the amorphous silicon layer is nitrided to form at least one silicon nitride layer; (6) a dielectric layer is covered A dielectric layer; (i) planarizing and removing a portion of the dielectric =, the nitride nitride layer, and the amorphous chip layer until the surface of the amorphous layer is exposed; and (ii) replacing the amorphous with a copper metal layer Silicon layer. The manufacturing method of the above copper wire is to selectively nitride the surface of the amorphous hard layer by using an ammonia gas plasma, and to use an solution containing copper sulfate, hydrogen acid, and a gasification gas to electrolyze the amorphous layer. The silicon layer is replaced with the copper metal layer. In addition, when the dielectric layer is composed of silicon oxide, in order to avoid the erosion of the dielectric layer by hydrofluoric acid when the amorphous silicon layer is replaced with the M copper metal layer, another surface of the dielectric layer is formed. An organic dielectric layer is covered to protect the dielectric layer composed of silicon oxide. Xia's Simple Army The present invention will be described with reference to the following drawings, in which FIG. 1 (a) to (f) are the conventional double-inlay manufacturing process of copper wires;

504799

Figures 2 (a) to 2 (g) are the manufacturing process of the copper wire of the present invention; Figures 1 2 to 3 are the test results of the component leakage current of the present invention; Figures 4 (a) to 4 (g) are the other of the present invention A copper wire manufacturing process. Element symbol 102 substrate 106 first dielectric layer 110 second dielectric layer 1 copper seed layer 118 silicon nitride layer 202 barrier layer 206 copper metal layer 22, 42 semiconductor element 10 semiconductor element 104 first nitride Silicon layer 1 0 8 Second nitride layer 1 12 Copper barrier layer 116 Copper metal layer 20 Substrate 204 Dielectric layer 208 Silicon nitride layer 210 Barrier layer 214 Silicon nitride layer 218 Copper metal layer 402 Barrier layer 406 organic dielectric layer 410 silicon nitride layer 4 14 amorphous layer 418 porous silicon oxide layer 422 copper metal layer. Figure 2 (a) shows & nitride buttons Figure 2 (a) to Figure 2 (g) are the copper wire manufacturing process of the present invention showing the initial structure of the manufacturing process, a substrate 2 0 includes a H: \ HU \ TYS \ NDL says \ Fixed 75134 D〇c

1 12 Amorphous chip layer 216 Dielectric layer 40 Substrate 2 404 Porous oxide layer 408 Copper metal layer 3 12 Barrier layer 416 Silicon nitride layer 420 Organic dielectric layer Description of preferred embodiments 504799 A7 B7

V. Description of the invention (7 composition of P early layer 202 and a dielectric layer 204, a copper metal layer composed of copper metal wires and copper via hole plugs 2 0 6 and The silicon nitride layer 208 is one of the dielectric layer 204 and the copper metal layer 206. The nitride layer 208 serves as a copper barrier layer to prevent copper metal from diffusing. In FIG. 2 (b), A semiconductor element 22 is deposited on the surface of the substrate 20 by pVd or nitrided barrier layer 210, and then an CVD silicon layer 2 12 is deposited by CVD. In FIG. 2 (c), A photoresist (not shown) defines a via hole area, and the amorphous silicon layer 2 etched outside the via area is etched to an appropriate depth. Then another photoresist (not shown) is used to define a metal Line, and etch the amorphous silicon layer 2 丨 2 outside the metal line area and the barrier layer 2 10 of the button or nitride surface. In FIG. 2 (d), an ammonia plasma is used to selectively The surface of the amorphous broken layer 2 1 2 is nitrided to form a silicon nitride layer 2 4 as a copper barrier layer to prevent copper metal from diffusing. In FIG. 2 (e), it is coated by CVD or spin coating. 1 Dielectric Layer 216. In FIG. 2 (f), the surface of the amorphous silicon layer 2 12 is exposed by using CMP or dry etching etch back to planarize. In FIG. 2 (g), it is contacted with copper. In the replacement technology, a copper metal layer 218 is used to replace the amorphous silicon layer 212. In this embodiment, the wafer is subjected to a multi-connection process as an example, so the substrate 20 includes a structure of an intermetallic interlayer and a wire therebetween. Of course, the present invention can also be applied to the wafer after the inner dielectric contact plug is completed. At this time, the starting structure of the manufacturing process must include the inner dielectric and the structure of the contact plug. The present invention uses a nitrogen The siliconized layer 2 08 replaces the conventional samarium or nitrided button layer as a copper barrier layer, which can be formed by using ammonia (leg 3), nitrogen oxide (n2〇) or nitrogen (N2) plasma for 3 minutes. , Its leakage current through 22 5．〇 ， 4Mv / cm

Hold

The line HAHU \ TYS \ NDL says \ corrected 75134D0c 504799 A7 B7 V. Description of the invention (8) Bias Thermal Stress (BTS) test did not deteriorate for 2 hours. The result is shown in Figure 3. In addition, if the dielectric layer 2 丨 6 is composed of an inorganic porous silicon oxide layer, since the porous silicon oxide layer will be attacked by hydrofluoric acid during the copper contact replacement step, the present invention uses another An organic dielectric layer and an inorganic dielectric layer overcome the disadvantage that the porous silicon oxide layer is easily eroded by hydrofluoric acid. The manufacturing process is shown in Figs. 4 (a) to 4 (g). In FIG. 4 (i), the initial structure of the manufacturing process is shown. A substrate 40 includes a barrier layer 4 made of a button or a nitride button, a porous silicon oxide layer 4 and a low α-private organic dielectric layer 406, a copper metal layer 4 composed of copper metal wires and copper via hole plugs, and interposed between the porous silicon oxide layer 404 and the organic dielectric layer 4 One of the silicon nitride layer 410 between 〇6 and the copper metal layer 408 serves as a copper barrier layer to prevent the diffusion of copper metal. In FIG. 4 (b), a semiconductor element 42 is on the surface of the substrate 40 to A barrier layer 4 12 of a button or a nitride button is deposited by PVD, and then an amorphous silicon layer 4 M is deposited by CVD. In FIG. 4 (0, a photoresist is used (not shown) Define a via hole area, etch the amorphous silicon layer 4 丨 4 to an appropriate depth outside the via hole area, then define a metal line area with another photoresist (not shown), and etch the metal line area The amorphous silicon layer 414 and the barrier layer 412 composed of rhenium or nitride button are then removed, and then the organic dielectric layer 406 is removed by etching or oxidation. In FIG. 4 (a), the surface of the amorphous silicon layer 4 丨 4 is selectively nitrided by using ammonia gas polymerization to form a silicon nitride layer 4 16 as a copper barrier layer to prevent copper metal from diffusing. In the CVD method, the porous oxygen-cut layer with low dielectric constant is covered, and I said that \ 13475.DOC — ^ — This paper standard is applicable to f ® National Standard (CMS) A4 specification (21GX297 male D ---------- — 504799 A7 ----————_____ B7 V. Description of the invention (9) ---- Expose part of the nitrided fragmentation layer 4 丨 6 by etchback method Then, the organic dielectric layer 420 is covered again. In FIG. 4 (f), planarization is performed by CMP or etch-back to expose the surface of the amorphous silicon layer 414. In FIG. 4 (§), the The copper contact replacement technology replaces the amorphous silicon layer 4 1 4 with a steel metal layer 422, because the organic dielectric layer 42 forms a protective layer for the porous silicon oxide layer 4 1 8 at this time, which can prevent copper from being carried. During contact replacement, hydrofluoric acid causes damage to the porous silicon oxide layer 4 1 8. The technical content and technical features of the present invention are disclosed above, but are familiar with this technology. Scholars may still make various substitutions and modifications that do not depart from the spirit of the invention based on the teachings and disclosures of the invention. Therefore, the scope of protection of the invention should not be limited to those disclosed in the embodiments, but should include, without departing from, the following: The replacement and modification are covered by the following patent application parks. 12-

H: \ HU \ TYS \ NDL said \ Has been corrected 75134.DOC This paper size applies Chinese National Standard (CNS) Α4 specification (210X297 public love)

Claims (1)

/ yy A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and applied for patents. The method of making copper wires includes the following steps: depositing a metal barrier layer on the surface of a substrate; covering an amorphous layer Layer; defining at least one via hole region; etching the amorphous silicon layer outside the via hole region; defining at least one metal wire region; engraving the Γ-absent amorphous silicon layer and the metal resistor outside the metal wire region Barrier layer; forming a copper barrier layer on the surface of the amorphous silicon layer after etching; covering a dielectric layer; planarizing the surface until the amorphous layer is exposed; and replacing the amorphous silicon layer with a copper metal layer . 2. The copper wire manufacturing method according to item i in the patent application, wherein the metal barrier layer is formed by depositing Zhao metal by means of physical vapor deposition. The method for manufacturing a copper wire claimed in item 1 of the patent In, wherein the metal barrier layer is formed by depositing tantalum nitride by physical vapor deposition. 4. The copper wire manufacturing method as described in the first item of the patent application. The broken layer is formed by chemical vapor deposition. For example, it is called the copper wire manufacturing method of item 丨 of the patent. The material of the barrier layer is silicon nitride. Jun claims the copper wire manufacturing method of item 5 of the patent scope. P Early layer system # 1] is formed by nitriding with an ammonia plasma. HAHUVrY_DL said \ has been corrected 75134 Canton 5's scale is applicable where the amorphous, the copper resistance, which the copper resistance W 1 * ti, / ------------------- -Order -------! Wire -®- (Please read the notes on the back before filling this page) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8, Patent Application Scope 7 · For the copper wire manufacturing method in the first patent application scope, The dielectric layer is formed by depositing a dielectric with a low dielectric constant by means of chemical vapor deposition. 8. The method for manufacturing a copper wire according to item i of the application, wherein the dielectric layer is formed by covering a dielectric 2 with a low dielectric constant by a spin coating method. 9. The copper wire manufacturing method according to item 1 of the scope of patent application, wherein the flattening step is performed by chemical mechanical polishing. 10 · As described in the copper wire manufacturing method in item 1 of the patent application, the step of flattening in the device is performed by dry etching and etch back. u · The copper wire manufacturing method according to item 1 of the patent application park, wherein the step of replacing the amorphous silicon layer by the copper metal layer is formed by electrochemical T < 1 2 · The copper wire manufacturing method according to item 丨 丨 in the scope of patent application, wherein the electrochemical method uses a mixed solution of copper sulfate, ammonia fluoride and hydrofluoric acid for the reaction. 1 3. A method for manufacturing a copper wire, comprising the following steps: depositing a metal barrier layer on a substrate surface; covering an amorphous chip layer; defining at least one via hole region; and engraving the amorphous layer outside the via hole region Broken layer; defining at least one metal line area; etching away the amorphous silicon layer and the metal barrier layer outside the metal line area; j ^ \ HU \ TYS \ NDL said \ corrected 75 丨 34.DOC-4 M Zhang Zhongguan Family Fresh (CNS) A4 Specification (210mm Ding ----------- I «I ------ Order --------- ^ (please first Read the notes on the back and fill out this page) ^ 04799 6. The scope of the patent application forms a copper barrier layer on the surface of the amorphous silicon layer after etching; covers the silicon oxide layer; covers an organic dielectric layer; planarizes the surface until the amorphous silicon layer is exposed; and A copper metal layer replaces the amorphous silicon layer. 14. The method for manufacturing a copper wire according to item 13 of the scope of patent application, wherein the silicon oxide layer is formed by depositing a porous oxide chip by means of chemical vapor deposition. 15 · The copper wire manufacturing method according to item 13 of the patent application park, wherein the organic dielectric layer is formed by covering a low dielectric constant organic dielectric with a spin coating method. 16 · The copper wire manufacturing method according to item 13 of the scope of patent application, wherein the organic dielectric layer is formed by depositing an organic dielectric with a low dielectric constant using a chemical vapor deposition method. (Please read the precautions on the back before filling this page) # Order --------— line, printed by H: \ HU \ TYS \ NDL printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs \ Modified 75134DOC -15 A paper size applies to China National Standard (CNS) A4 (210 X 297 mm)