461051 A7 B7 五、發明說明（) 發明背景： (1) 發明範疇 (請先閱讀背面之注意事項再填寫本頁) 本發明與一般分閘式快閃記憶元件（split_gate flash memory devices)有關’特別是與高密度、高速和低功率分閘式快閃 記憶元件有關。 (2) 習知技藝描述 快閃記憶元件是利用富勤-諾得漢穿透（Fowler-Nordheim tunneling)或熱載子注入方法將電荷由半導體基板穿或跨越 —薄介電層至一隔離閘（俗稱漂浮閘），並儲存於其中，並利 用富勤-諾得漢穿透方法將儲存於隔離閘的電荷移或擦洗至 半導體基板或控制閘。基本上，記憶細胞元必需縮小以利高 密度大量儲存之應用，並且元件結構需朝向低電壓、低電流 和高速操作且兼具高的耐用度（endurance)及續存度 (retention) 〇 經濟部智慧財產局員工消費合作社印製 根據元件的結構，過去習知的技藝基本上可以區分成兩類 :疊堆閘式（stack-gate)結構及分閘式（split-gate)結構。圖一 顯示傳統疊堆閘式快閃記憶元件的一個典型結構，其中元件 閘長度主要受所使用技術之最小線寬的限制，此元件因之被 公認是一個電晶體的元件。圖二顯示傳統分閘式快閃記億元 件的一個典型結構，其中元件的閘長度包括漂浮閘長度和控 制閘長度，此元件因之被公認是1.5個電晶體的元件。圖一 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 1051 A7 — ___B7_____^_ 五、發明說明（） (請先閲讀背面之注意事項再填寫本頁) 所示之疊堆閘式快閃記憶元件包括一個P型基板1 00及在P 型基板內之Π +型源極擴散區101，及一個n +型洩極擴散區103 置放於一個型洩極擴散區102的雙擴散洩極（double-diffused drain)。一個具有約100埃厚度的薄穿透氧化層104 置於P型基板1〇〇之表面上。一個複晶矽層105置於薄穿透 氧化層104之上，作爲漂浮閘（floating gate)。一個夾在間間 的0N0結構介電層106將漂浮閘105及矽化複晶矽控制閘 (control gate)107 隔開。 圖一所示之疊堆閘式快閃記憶元件的寫（程式）動作是在控 制閘上加上一相對高的正電壓及在細胞元之源極加上一中庸 的正電壓，洩極則接地。通常，元件是操作在飽和區，接近 源極之通道調變（channel modulation)區內之高電場用來產生 熱載子，其中能量高於薄穿透氧化層與半導體基板傳導帶間 之接面能障（約3.15電子•伏特）的熱電子會注入到漂浮閘並 儲存其中，產生的熱電洞形成基片電流。因爲大部份的通道 電荷均由正電壓的源極所吸收，注入效率很差且大部份的洩 極電流均被浪費掉。再者，寫入之功率大，造成高密度大量 儲存應用的進一步障礙。 經濟部智慧財產局員工消費合作杜印製 圖一所示之疊堆閘式快閃記憶元件的擦洗動作是在洩極加 上一相對高的正電壓，而控制閘極接地，源極通常浮接。儲 存於漂浮閘的電子，經由跨於薄穿透氧化層的高電場穿透到 洩極。上述的擦洗法可以稍加修改，將洩極與基板間的電壓 降低，控制閘極的電壓由接地改爲負電壓。洩極與基板間電 壓的降低主要在於消除洩極與基板間產生的帶對帶穿透效應 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 46 105 1 A7 _ B7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) (band-to-band _ tunneling)，以避免不必要的_熱電洞注入到漂 浮閘或深陷於薄穿透氧化層內。很顯然地，較深的雙擴散洩 極接面能提供薄透穿氧化層較大的重疊面積，以增加擦洗的 電流，進而消除帶對帶穿透效應，但閘-洩重疊電容和洩-基 板接面電容大幅增加，造成低的讀速率和進一步微縮的障 礙。再者，將漂浮閘儲存的電荷擦洗至重疊的洩擴散區並非 是自動限制，以致造成超擦洗（over-erase)的問題，進而需要 複雜電路和軟體來執行一系列的擦洗和驗証步驟。 圖二所示之分閘式快閃記憶元件包括一 P型基板11 0及置 於P型基板110內之n +型源極和洩極擴散區11 8.和117 。 經濟部智慧財產局員工消費合作社印製 一層大約1〇〇埃厚度的穿透氧化層Π1置於一部份P型基板 110上及在複晶矽漂浮閘113之下的一部份n +型源極擴散區 118。漂浮閘113重疊一部份的n +型源極擴散區118及通道》 利用傳統局部氧化矽（LOCOS)的技術，一個特殊形狀的複晶 矽氧化層114置於複晶矽漂浮閘113之上。一薄介電層115 將控制閘Π 6與複晶矽漂浮閘11 3之邊牆隔開’一部份的複 晶矽漂浮閘疊在稍厚一點的氧化層.112上。控制閘116經由 稍厚一點的氧化矽層112重疊一部份的洩極擴散區117及一 部份通道。很顯然地’以光蝕刻的觀點而言，除了 1 _1個電 晶體的自然限制外，控制閘之光蝕刻對準容忍度的限制造成 元件進一步微縮的一個障礙。因此，圖二所示之傳統分閘式 快閃記憶元件的結構，以每一位元的成本來看’是不太適合 高密度大量儲存的應用。再者’源極-基板接面電容較大， 形成高速讀取操作的主要障礙。 1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 461051 A7 _____B7 _ 五、發明說明（） 圖二所示之分閘式快閃記憶元件的寫動作是在控制閘上加 —相對低的正電壓（控制鬧電晶體的臨界電壓），源極加上相 對高的正電壓，洩極則接地。控制閘下之通道電子經由控制 閘與標浮閘間之空隙下面所產生的橫向高電場來加速’以產 生熱載子。凡能量超過薄氧化層與基板傳導帶之介面能障（約 3. 15電子•伏特）的熱電子可以注入到漂浮閘並儲存於其中’ 熱電洞則形成基板電流。很顯然地，由於—部份的外加源極 電壓會降在控制閘下之通道和漂浮閘下的通道’傳統分閘式 快閃記憶元件需要比疊堆聞式快閃記憶元件高的源極電壓。 然而，寫動作之通道電流是由控制閘來控制’傳統分閘式快 閃記憶元件之寫的電流比圖一所示之疊堆閘式快閃記憶元件 小得很多，此爲分閘式快閃記憶元件的優點之—。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 圖二所示之傳統分閘式快閃記憶元件的擦洗是在控制閘加 一相對高的正電壓，而源及洩極均接地。擦洗的動作是由漂 浮閘邊牆上端的尖端以富勒-諾得漢穿透方法將漂浮閘所儲 存的電子穿透至控制閘。分閘式的擦洗法"會在漂浮閘的尖端 累積正電荷來降低尖端的電場，擦洗會自動限制，因此不會 造成超擦洗的問題，擦洗的電路較爲簡單，此爲分閘式快閃 記憶元件的優點。然而，複晶矽漂浮閘邊牆的氧化會產生控 制閘複晶矽的微笑效應（smiling effect)，因而造成逆向穿透 的干擾。因此，複晶矽漂浮閘之邊牆需要成長較厚的複晶矽 氧化層來降低逆向穿透的干擾，以致造成邊牆擦洗電極之穿 透機率的降低，因而高的控制閘電壓是無可避免。 根據上述的分析，疊堆閘式結構可以利用所使用技術的最 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） _____^7____ 6 1051 A7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) 小線寬加予微縮，，但寫的效率差，大部份寫的洩極電流均浪 費掉，超擦洗需要複雜電路來克服。再者’傳統疊堆閘式快 閃記憶元件之漂浮閘與雙擴散洩極間的重疊區需要變大’以 增加擦洗電流及避免帶對带穿透效應’但通道的微縮將受到 限制。.傳統分閘式快閃記憶元件之細胞元尺寸較大’不容易 加予微縮，寫與洗的電壓較高’但寫的效率較高且所需的洩 極電流較小，擦洗能自動限制，擦洗的電路較簡單。 基於此，本發明主要針對高密度、高速及低功率大量儲存 的應用提供一可微縮化分閘式快閃記憶元件來克服傳統分閘 式快閃記憶元件的缺點。 發明槪述： 經濟部智慧財產局員工消費合作社印製 本發明揭示在修改型局部氧化矽（modified LOCOS)或淺 凹槽隔離（shallow-trench-isolation)技術所形成的前進隔離結 構上製造一種可微縮化分閘式快閃記憶元件。可微縮化分閘 式快閃記憶元件是利用墊層形成的技術來製造，因此不受傳 統光蝕刻之限制，其中漂浮閘元件.和控制閘元件的通道長度 能分別加予控制，使其長度甚小於所用技術之最小線寬。因 此，製造完成的分閘式快閃記憶元件之整個通道長度’可以 小於所使用技術的最小線寬，且主要由複晶矽墊層的組合寬 度來決定。本發明利用薄複晶矽層作爲漂浮閘’無需’額外製 程步驟即可在其邊牆形成一個邊牆擦洗電極。此具有一個邊 牆擦洗電極之可微縮化分閘式快閃記憶元件製造在兩種具有 雙邊擦洗電極和高耦合比的前進高密度隔離結構上’以形成 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 461051 A7 __ B7 五、發明說明（） 具有三邊擦洗電極之可微縮化分閘式快閃記憶元件，以獲得 能自動限制之漂浮鬧對控制閫的高效率擦洗。另外，本發明 將自動對準砂化（self-aligned silicidation)技術應用於可微縮 化分閘式快閃記憶元件的控制閘、源極/共同埋層源極擴散 區及洩極擴散區，以降低接觸及連線的電阻，並且利用氮化 矽墊層置於元件邊牆的技術完成自動對準接觸，以縮小接觸 點間的間距。基於此，本發明可以用來製造大量儲存應用所 需之高密度、高速及低功率分閘式快閃記憶陣列及系統。 圖示的簡要說明： 圖一揭示傳統疊堆閘式快閃記憶元件之部份剖面結構； 圖二揭示傳統分閘式快閃記憶元件之部份剖面結構； 圖三至圖十五揭示本發明之具有一個邊牆擦洗電極的可 微縮分閘式快閃記憶元件和周邊互補式金氧半（CMOS)元件 之結構及製程的.剖面圖； 圖十六至圖十九揭示本發明之具有雙邊擦洗電極和可調 變耦合比的淺凹槽隔離技術之結構和製程的剖面圖； 圖二十至圖二十二揭示本發明之具有雙邊擦洗電極和高 耦合比的修改型局部氧化矽隔離技術之結構和製程的剖面 圖。 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · I I I V----訂·-----461051 A7 B7 V. Description of the invention () Background of the invention: (1) The scope of the invention (please read the notes on the back before filling this page) This invention is related to the general split_gate flash memory devices (split_gate flash memory devices). It is related to high-density, high-speed and low-power open flash memory elements. (2) Description of conventional techniques Flash memory devices use Fowler-Nordheim tunneling or hot carrier injection to pass or cross charge from a semiconductor substrate—a thin dielectric layer to an isolation gate (Commonly known as floating gate), and stored in it, and the charge stored in the isolation gate is transferred or scrubbed to the semiconductor substrate or control gate using the Fuqin-Nordheim penetration method. Basically, the memory cell must be reduced to facilitate high-density mass storage applications, and the device structure must be oriented towards low voltage, low current, and high-speed operation, and have both high endurance and retention. Ministry of Economic Affairs According to the structure of the components, the Intellectual Property Bureau employee consumer cooperatives can basically be divided into two categories: stack-gate structure and split-gate structure. Figure 1 shows a typical structure of a conventional stacked gate flash memory device. The gate length of the device is mainly limited by the minimum line width of the technology used. This device is considered to be a transistor device. Figure 2 shows a typical structure of a traditional split-type flash-memory device. The gate length of the element includes the length of the floating gate and the length of the control gate. Therefore, this element is recognized as a component of 1.5 transistors. Figure 1 3 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 6 1051 A7 — ___ B7 _____ ^ _ V. Description of the invention () (Please read the notes on the back before filling this page) The stacked gate type flash memory device includes a P-type substrate 100, a Π + -type source diffusion region 101 in the P-type substrate, and an n + -type drain diffusion region 103 placed in a type-type drain diffusion. The region 102 has a double-diffused drain. A thin penetrating oxide layer 104 having a thickness of about 100 angstroms is placed on the surface of the P-type substrate 100. A polycrystalline silicon layer 105 is placed on top of the thin penetrating oxide layer 104 as a floating gate. An interposed 0N0 structure dielectric layer 106 separates the floating gate 105 and the silicided polycrystalline silicon control gate 107. The write (program) action of the stacked gate flash memory element shown in Figure 1 is to apply a relatively high positive voltage to the control gate and a moderate positive voltage to the source of the cell. Ground. Generally, the device operates in the saturation region, and a high electric field near the channel modulation region of the source is used to generate hot carriers, where the energy is higher than the interface between the thin penetrating oxide layer and the conduction band of the semiconductor substrate The thermal electrons of the energy barrier (approximately 3.15 electrons • volts) are injected into the floating gate and stored therein, and the generated thermal holes form a substrate current. Because most of the channel charge is absorbed by the positive voltage source, the injection efficiency is poor and most of the drain current is wasted. In addition, the high writing power causes further obstacles to high-density mass storage applications. The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed the stacked gate flash memory device shown in Figure 1. The scrubbing action is to add a relatively high positive voltage to the drain electrode, and to control the gate to ground, the source usually floats. Pick up. The electrons stored in the floating gate penetrate to the drain electrode through a high electric field across a thin penetrating oxide layer. The above scrubbing method can be slightly modified, reducing the voltage between the drain electrode and the substrate, and controlling the gate voltage from ground to negative voltage. The reduction of the voltage between the drain electrode and the substrate is mainly to eliminate the band-to-belt penetration effect between the drain electrode and the substrate. 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 46 105 1 A7 _ B7 V. Description of the invention () (Please read the precautions on the back before filling in this page) (band-to-band _ tunneling) to avoid unnecessary _ thermal holes injected into the floating gate or deep in the thin penetrating oxide layer Inside. Obviously, the deeper double-diffusion drain junction can provide a larger overlapping area of thin through-thickness oxide layer to increase the scrub current, thereby eliminating the band-to-band penetration effect, but the gate-drain overlap capacitance and the drain- Substrate capacitance increased significantly, causing low read rates and obstacles to further scaling. Furthermore, scrubbing the charge stored in the floating gate to the overlapping leak-diffusion area is not automatically limited, which causes an over-erase problem, which requires complicated circuits and software to perform a series of scrubbing and verification steps. The split-type flash memory element shown in FIG. 2 includes a P-type substrate 110 and n + -type source and drain diffusion regions 118 and 117 disposed in the P-type substrate 110. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a layer of penetrating oxide with a thickness of about 100 angstroms. Π1 is placed on a part of the P-type substrate 110 and a part of the n + type under the polycrystalline silicon floating gate 113. Source diffusion region 118. The floating gate 113 overlaps a part of the n + -type source diffusion region 118 and the channel. "Using traditional local silicon oxide (LOCOS) technology, a special-shaped polycrystalline silicon oxide layer 114 is placed on the polycrystalline silicon floating gate 113. . A thin dielectric layer 115 separates the control gate Π 6 from the side wall of the polycrystalline silicon floating gate 113, and a part of the polycrystalline silicon floating gate is stacked on a slightly thicker oxide layer 112. The control gate 116 overlaps a part of the drain diffusion region 117 and a part of the channel via the slightly thicker silicon oxide layer 112. Obviously, from the point of view of photo-etching, in addition to the natural limitation of 1_1 transistors, the limit of the tolerance for controlling the photo-etching alignment of the gate causes an obstacle to further shrinking of the device. Therefore, the structure of the conventional split-type flash memory device shown in FIG. 2 is not suitable for high-density mass storage applications at a cost per bit. Furthermore, the source-substrate interface has a large capacitance, which constitutes a major obstacle to high-speed reading operations. 1 This paper size applies to China National Standard (CNS) A4 (210 X 297 Gongchu) 461051 A7 _____B7 _ 5. Description of the invention () The write action of the split flash memory element shown in Figure 2 is on the control brake Add-a relatively low positive voltage (controls the critical voltage of the alarm crystal), the source plus a relatively high positive voltage, and the drain is grounded. Channel electrons under the control gate are accelerated 'by the lateral high electric field generated under the gap between the control gate and the standard floating gate to generate hot carriers. Hot electrons whose energy exceeds the interface barrier of the thin oxide layer and the conduction band of the substrate (approximately 3. 15 electrons • volts) can be injected into the floating gate and stored in it. The thermal holes form the substrate current. Obviously, because-part of the applied source voltage will drop in the channel under the control gate and the channel under the floating gate, the traditional split-gate flash memory element requires a higher source than the stacked stack-type flash memory element. Voltage. However, the channel current of the write action is controlled by the control gate. The write current of the traditional open-type flash memory element is much smaller than that of the stacked-type flash memory element shown in Figure 1. The advantages of flash memory components-. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) The scrubbing of the traditional flash memory device shown in Figure 2 is a relatively high positive voltage applied to the control gate. The source and drain are grounded. The scrubbing action is to use the Fuller-Nordheim penetrating method to penetrate the electrons stored in the floating gate to the control gate by the tip on the side wall of the floating gate. Split-type scrubbing method " will accumulate a positive charge at the tip of the floating gate to reduce the electric field at the tip. Scrubbing will be automatically limited, so it will not cause the problem of over scrubbing. The scrubbing circuit is relatively simple. Advantages of flash memory components. However, the oxidation of the polycrystalline silicon floating gate side wall will produce a smiling effect that controls the polycrystalline silicon, which will cause the interference of reverse penetration. Therefore, the side wall of the polycrystalline silicon floating gate needs to grow a thicker polycrystalline silicon oxide layer to reduce the interference of reverse penetration, so that the penetration probability of the scrub electrode of the side wall is reduced, so a high control gate voltage is impossible. avoid. According to the analysis above, the stack gate structure can use the most 6 paper sizes of the technology used. The Chinese paper standard (CNS) A4 (210 X 297 mm) is applicable. _____ ^ 7____ 6 1051 A7 V. Description of the invention () ( Please read the precautions on the back before filling in this page.) The small line width is reduced, but the writing efficiency is poor. Most of the write leakage current is wasted. Super scrubbing requires complicated circuits to overcome. Furthermore, 'the overlapping area between the floating gate and the double diffusion drain of the conventional stacked gate flash memory element needs to be increased' to increase the scrub current and avoid the band-to-band penetration effect ', but the channel shrinkage will be limited. .The cell size of the traditional flash-type flash memory element is large 'not easy to be miniaturized, and the voltage of writing and washing is high', but the writing efficiency is high and the required drain current is small. The scrubbing can be automatically limited. The scrubbing circuit is simpler. Based on this, the present invention mainly provides a miniaturized split-type flash memory element for high-density, high-speed, and low-power mass storage applications to overcome the shortcomings of the conventional split-type flash memory element. Description of the invention: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics This invention discloses that an advanced isolation structure formed by modified LOCOS or shallow-trench-isolation technology can be used Miniature open-type flash memory element. The miniaturizable split-type flash memory device is manufactured by using the technology of cushion formation, so it is not limited by the traditional photolithography. The floating gate element and the channel length of the control gate element can be controlled separately to make their length Much smaller than the minimum line width of the technology used. Therefore, the entire channel length of the completed split-type flash memory element can be smaller than the minimum line width of the technology used, and is mainly determined by the combined width of the polycrystalline silicon cushion layer. The present invention uses a thin polycrystalline silicon layer as a floating gate to form a side wall scrubbing electrode on its side wall without additional process steps. This miniaturized open-type flash memory element with a side wall scrubbing electrode is manufactured on two advanced high-density isolation structures with a bilateral scrubbing electrode and a high coupling ratio to form 7 paper sizes that are applicable to Chinese national standards (CNS ) A4 specification (210 X 297 mm) 461051 A7 __ B7 V. Description of the invention () Miniatable micro-open flash memory element with three-side scrubbing electrodes to obtain the high limit of floating and auto-limiting control Efficient scrubbing. In addition, the present invention applies a self-aligned silicidation technology to a control gate, a source / common buried layer source diffusion region, and a drain diffusion region of a miniaturizable split-type flash memory element, so as to Reduce the contact and connection resistance, and use the technology of silicon nitride pad layer placed on the side wall of the device to complete the automatic alignment of contacts to reduce the distance between the contact points. Based on this, the present invention can be used to manufacture high-density, high-speed, and low-power split-type flash memory arrays and systems required for mass storage applications. Brief description of the figures: Figure 1 reveals a partial cross-sectional structure of a conventional stacked gate flash memory device; Figure 2 discloses a partial cross-sectional structure of a conventional split-gate flash memory device; Figures 3 to 15 disclose the present invention Sectional view of the structure and manufacturing process of a scalable flash memory device with a side wall scrubbing electrode and a peripheral complementary metal-oxide-semiconductor (CMOS) device; Figures 16 to 19 reveal the invention has a bilateral Cross-sectional views of the structure and process of the scrub electrode and the shallow groove isolation technology with adjustable coupling ratio; Figures 20 to 22 reveal the modified partial silicon oxide isolation technology with bilateral scrub electrode and high coupling ratio of the present invention Sectional view of the structure and process. The size of wood paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) · I I I V ---- Order · -----
-A 經濟部智慧財產局員工消費合作社印製 461〇51 A7 B7 五、發明說明（ 圖號對照說明： 20單晶矽基板 2 1 b η 井 23第 25第一 27光阻 29逆向 31 第二 33第 經濟部智慧財產局員工消費合作社印製 34第二 34b 第二 35 第二 37低濃 38b第三 40光阻 41b低濃 43a第四 44第一 45高濃 47光阻 49a高濃 49c高濃 複晶砍層 罩幕氮化矽層 罩幕 調光阻罩幕 熱二氧化矽層 良好覆蓋性複晶矽層 良好覆蓋性複晶矽層 複晶矽左墊層 罩幕氮化矽層 度源和洩擴散區 熱複晶矽氧化層 罩幕 度洩擴散區 熱複晶矽氧化層 良好覆蓋性氮化矽層 度源和洩擴散·區 罩幕 度源擴散區 度源和洩擴散區 21a P 井 22第一熱二氧化矽層 24第一介電層 26光阻罩幕 28 η通道離子佈植區 30 Ρ通道離子佈植區 32第一熱複晶矽氧化層 33a第一複晶矽墊層 34a 第二 34c 第一 36光阻 38a 第二 39光阻 4 1 a低濃 4 2低濃 43b第五 44a 第一 46光阻 48第三 49b高濃 50光阻 複晶矽右墊層 複晶矽閘層 罩幕 熱複晶矽氧化層 罩幕 度源擴散區 度源和洩擴散區 熱複晶政氧化層 氮化矽墊層 罩幕 熱二氧化矽層 度洩擴散區 罩幕 請 先 閱 讀 背 之 注, 意 事 項 再 填 窝 本 頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 1051 A7 B7 經濟部智慧財產局員工消費合作社印製 5 1矽化鈦層 53光阻罩幕 55薄氮化鈦層 57 Ml金屬層 59光阻罩幕 61第六熱複晶矽氧化層 63第三良好覆蓋性複晶矽層 64第四罩幕氮化矽層 66第二良好覆蓋性氮化矽層 67第七熱複晶矽氧化層 68a第三氮化矽墊層 五、發明說明（ 5 2氮化鈦層 5 4厚介電層 56鎢層 58第三罩幕氮化矽層 60第四熱二氧化矽層 62良好覆蓋性厚二氧化矽層 63a第三複晶矽墊層 65第一罩幕二氧化矽層 66a第二氮化矽墊層 6 8第三良好覆蓋性氮化矽層 69通道禁通區 發明之詳細說明： 參考圖.三至圖十五，這些圖揭示本發明.第一部份內涵。 在850°C之乾氧環境下，矽單晶基板20之P井21a上·成長 第一熱二氧化矽層22，厚度約85至110埃之間。然後，利 用低壓化學沈積法，在550°C至630°C之間的溫度將矽烷 (silane)熱分解，堆積第一複晶矽層23，厚度約3 00至600 埃之間。在第一複晶矽層23之上形成第一介電層24,其等 效二氧化矽厚度約150至220埃之間。第一介電層24可以 是一個二氧化矽-氮化矽·二氧化矽（ΟΝΟ)複合層或將第一 複晶矽層23的表面成長熱複晶矽氧化矽層。ΟΝΟ複合層是 先成長一熱複晶矽氧化層，再堆積氮化矽層，然後將氮化矽 層氧化。利用低壓化學氣相沈積成長法，將雙氯矽烷（dichloro 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------—訂—— II----蜂 4 6 1051 7 A7 __；_B7___ 五、發明說明（) (請先閱讀背面之注意事項再填寫本頁) -silane)與氨氣於720°C下反應，在第一介電層24之上成 長第一罩幕氮化矽層25，厚度約1 000至2000埃之間。利 用傳統微影蝕刻技術定義快閃記憶元件之虛擬通道長度，如 圖三所示，其中虛擬通道長度等於二個元件漂浮閘長度和一 個共同源擴散寬度。定義完成的罩幕光阻26作爲罩幕，非 等向性地蝕刻第一罩幕氮化矽層25，第一介電層24和第一 複晶矽層23，然後將罩幕光祖26去除。値得注意的是’此 項鈾刻步驟完全去除原擬製造其他半導體元件如互補式金氧 半（CMOS)元件之半導體區上之第一罩幕氮化矽層25/第一 介電層24/第一複晶矽層23所組成之疊堆結構。 經濟部智慧財產局員工消費合作社印製 利用光阻罩幕27蓋住η并上之所有P通道金氧半元件， 跨過第一熱二氧化矽層22佈植受體（acceptor )雜質於Ρ井 21a之半導體區25，以調整η通道金氧半元件和快閃記憶元 件的臨界電壓（threshold'voltage.)和抵穿電壓（punch-through voltage)，如圖四所示，然後去除罩幕光阻27。利用逆向諷 (reverse: tone )罩幕光阻29’.跨過第一熱二氧化砍層22佈 植施體（donor)雜質於η井21b之半導體區30，以調整P 通道金氧半元件的臨界電壓和抵穿電壓，如圖五所示。將逆 向調罩幕光阻29去除後，在溫度約8 50°C至1000°C之間的 乾氧環境下，氧化第一複晶货層23之邊牆和單晶矽基板20 上之η井和P井之表面，成長厚度約200至400埃之間的第 二熱二氧化矽層31於單晶矽基板20上之η井和Ρ井表面， 厚度約100至250埃之間的第一熱複晶矽氧化層32於第一 複晶矽23的邊牆。利用低壓化學氣相沈積法，在580°C至-A Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives 461051 A7 B7 V. Description of the invention (Comparison of drawing number: 20 Monocrystalline silicon substrate 2 1 b η Well 23 25th 27 Photoresist 29 Reverse 31 Second 33 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economy 34 Second 34b Second 35 Second 37 Low Concentration 38b Third 40 Photoresist 41b Low Concentration 43a Fourth 44 First 45 High Concentration 47 Photoresistor 49a High Concentration 49c High Concentrated polycrystalline slicing mask, silicon nitride mask, dimming mask, thermal silicon dioxide layer, good coverage, polycrystalline silicon layer, good coverage, polycrystalline silicon layer, polycrystalline silicon, left cushion, silicon nitride layer Source and drain diffusion regions Thermally complex silicon oxide layer covers the drain diffusion region Good coverage of the thermal polycrystalline silicon oxide layer Covers the silicon nitride layer Source and drain diffusion area mask source Source diffusion region Source and drain diffusion region 21a P well 22 First thermal silicon dioxide layer 24 First dielectric layer 26 Photoresist mask 28 η channel ion implantation area 30 P channel ion implantation area 32 First thermal polycrystalline silicon oxide layer 33a First polycrystalline silicon Cushion layer 34a second 34c first 36 photoresist 38a second 39 photoresist 4 1 a low concentration 4 2 low concentration 43b fifth 44a first 46 Photoresist 48 Third 49b High-concentration 50 Photoresistance Polycrystalline silicon Right underlay Polycrystalline thyristor mask Thermal polycrystalline silicon oxide layer Curtain source Diffusion region Diffusion source and drain diffusion region Thermal complex crystal oxide layer Nitriding Silicon cushion cover curtain, thermal silicon dioxide layer, leakage diffusion area cover curtain, please read the back note first, and then fill in the pages on this page. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 6 1051 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 1 Titanium silicide layer 53 Photoresist mask 55 Thin titanium nitride layer 57 Ml Metal layer 59 Photoresist mask 61 Sixth thermal polycrystalline silicon oxide layer 63 Third Good coverage polycrystalline silicon layer 64 Fourth mask silicon nitride layer 66 Second good covering silicon nitride layer 67 Seventh thermal polycrystalline silicon oxide layer 68a Third silicon nitride pad layer 5. Description of the invention (5 2 Titanium nitride layer 5 4 thick dielectric layer 56 tungsten layer 58 third mask silicon nitride layer 60 fourth thermal silicon dioxide layer 62 good coverage thick silicon dioxide layer 63a third polycrystalline silicon underlayer 65 first Mask silicon dioxide layer 66a, second silicon nitride pad layer 6 8 third good coverage silicon nitride layer 69 channel forbidden area invention details Ming: Refer to Figures 3 to 15. These figures reveal the connotation of the first part of the present invention. Under the dry oxygen environment at 850 ° C, the first thermal dioxide is grown on the P well 21a of the silicon single crystal substrate 20 The silicon layer 22 has a thickness of about 85 to 110 angstroms. Then, using a low-pressure chemical deposition method, the silane is thermally decomposed at a temperature between 550 ° C and 630 ° C to deposit a first polycrystalline silicon layer 23, The thickness is between about 300 and 600 Angstroms. A first dielectric layer 24 is formed on the first polycrystalline silicon layer 23 and has an equivalent silicon dioxide thickness between about 150 and 220 angstroms. The first dielectric layer 24 may be a silicon dioxide-silicon nitride-silicon dioxide (ONO) composite layer or a surface of the first polycrystalline silicon layer 23 may be a thermal polycrystalline silicon oxide layer. 〇ΝΟ composite layer is to grow a thermal polycrystalline silicon oxide layer, then deposit a silicon nitride layer, and then oxidize the silicon nitride layer. Using low pressure chemical vapor deposition growth method, dichlorosilane (dichloro paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page)) ------— Order—— II ---- Bee 4 6 1051 7 A7 __; _B7___ 5. Description of the invention () (Please read the notes on the back before filling this page) -silane) and ammonia The reaction is performed at 720 ° C, and a first mask silicon nitride layer 25 is grown on the first dielectric layer 24 to a thickness of about 1,000 to 2000 angstroms. The traditional lithographic etching technology is used to define the virtual channel length of the flash memory device, as shown in Figure 3, where the virtual channel length is equal to the length of the two device floating gates and a common source diffusion width. The completed mask photoresist 26 is defined as the mask, and the first mask silicon nitride layer 25, the first dielectric layer 24, and the first polycrystalline silicon layer 23 are anisotropically etched, and then the mask photoresist 26 Remove. It should be noted that 'this uranium etch step completely removes the first masked silicon nitride layer 25 / the first dielectric layer 24 on the semiconductor region of other semiconductor devices that are intended to be manufactured, such as complementary metal-oxide-semiconductor (CMOS) devices. / A stacked structure composed of the first polycrystalline silicon layer 23. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints all P-channel metal-oxide half-elements covered with η using a photoresist mask 27, and implants acceptor impurities across the first thermal silicon dioxide layer 22 The semiconductor region 25 of the well 21a is used to adjust the threshold voltage and punch-through voltage of the η-channel metal-oxide half-element and the flash memory element, as shown in FIG. 4, and then the mask is removed. Photoresistance 27. Use a reverse: tone mask 29 '. A donor impurity is implanted across the first thermal dioxide cutting layer 22 in the semiconductor region 30 of the η well 21b to adjust the P-channel metal-oxide half-element. The critical voltage and breakdown voltage are shown in Figure 5. After removing the inversion mask curtain photoresist 29, the η on the side wall of the first polycrystalline cargo layer 23 and the single crystal silicon substrate 20 is oxidized in a dry oxygen environment at a temperature of about 8 50 ° C to 1000 ° C. On the surface of the wells and P wells, a second thermal silicon dioxide layer 31 having a thickness of about 200 to 400 angstroms is grown on the surface of the n well and the P well on the single crystal silicon substrate 20, and the first and second wells having a thickness of about 100 to 250 angstroms A thermal polycrystalline silicon oxide layer 32 is on a side wall of the first polycrystalline silicon 23. Low pressure chemical vapor deposition at 580 ° C to
II 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公釐） A7 461051 _____B7_____ 五、發明說明（） 650°C之間的溫度將矽烷熱分解，堆積第一良好覆蓋性複晶 .矽層33，如圖五所示。此第一良好覆蓋性複晶矽層33業經 自然摻雜（in-situ doped)磷，雜質濃度約1〇18至5xl0i9/cm3 之間，並非等向性地蝕刻來形成第一複晶矽墊層33a，如圖 六所示。然後，利用高溫磷酸去除第一罩幕氮化矽層25。 再次利用低壓化學氣相沈積法，在580°C至650°C之間的溫 度熱分解矽烷，堆積厚度約500至2000埃之間的第二良好 覆蓋性複晶矽層34,此第二良好覆蓋性複晶矽層34業經自 然摻雜磷，其濃度約1〇18至5xl〇l9/Cm3之間。接著利用低 壓化學氣相沈積法，在約720°C溫度將雙氯矽烷與氨氣反應， 成長厚度約5Ό0至2000埃之間的第二罩幕氮化矽層35。然 後，跨過第二罩幕氮化矽層35佈植磷於第二良好覆蓋性複 晶矽層34，雜質之濃度約1〇15至5¥1〇15/〇〇13之間（未特別 以分立圖標示）。利用罩幕光阻36定義η及P通道金氧半元 件之閘長度，如圖七所示，接著乾式飩刻第二罩幕氮化矽層 35及非等向蝕刻第二良好覆蓋性複晶矽層34，以形成第二 複晶矽墊層34a和34b於第一複晶矽墊層33a的兩側，並同 時完成η和p通道金氧半元件複晶矽閘層34c的蝕刻，如圖 八所示。値得注意的是，複晶矽墊層34a和3 4b的寬度主要 由堆積良好覆蓋性複晶矽層< 34的厚度來控制。因此，漂浮 閘元件之通道長度和控制閘元件之通道長度是經由堆積良好 覆蓋性複晶矽層的厚度控制加予微縮化。 利用罩幕光阻（未圖示），跨過第二熱二氧化矽層31自動 對準佈植硼雜質，劑量約1〇13至l〇l4/cm2之間，以形成p 12 本紙張尺度適用令國國家標準（CNS)A4規格（210 297公釐） ------------- 一 裝------ I 訂----------岣、 ~/1' ίV (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6 1 0 5 1 A7 ____________ B7_______ 五、發明說明（） 通道金氧半元件的低濃度源和洩擴散區37，然後將罩幕光 阻去除。在溫度約900°C至1050°C之間的乾氧或水氣環境 下，氧化暴露的第二複晶矽墊層34a和34b及η和p通道金 氧半元件之複晶矽閘34c之邊牆，成長厚度約200至300埃 之間的第二和第三熱複晶矽氧化矽層38a和38b。接著利用 一非嚴謹對準之罩幕光阻39及活性離子蝕刻，將第一介電 層24和第一複晶矽層23去除，如圖八所示。再利用罩幕光 阻40，佈植磷雜質，以形成快閃記憶元件的低濃度源擴散 區41a和洩擴散區41b及η通道金氧半元件之低濃度源和洩 , · · 擴散區42,摻雜質劑量約1〇13至l〇l4/Cm2之間，如圖九所 示。將罩幕光阻40去除之後，η和p通道金氧半元件之第 —複晶矽閘層34c上的第二罩幕氮化矽層35利用乾式蝕刻 去除，然後再氧化第一複晶矽閘34c，以形成第四熱複晶矽 氧化層43a，並同時將蝕刻後之第一複晶矽層23邊牆氧化， 以形成第五熱複晶矽氧化層43b。第四和第五熱複晶矽氧化 層43a和43b是利用溫度約850°C至1 050°C之間的乾氧環 境下成長，厚度約1〇〇至150埃之.間。 利用低壓化學氣相沈積法，將四烯氧矽烷與氨氣在750°C 下反應，堆積厚度約500至1 000埃之間的第一良好覆蓋性 氮化矽層44，接著非等向蝕刻第一良好覆蓋性氮化矽層44， 在快閃記憶元件和η及p通道金氧半元件之側牆形成第一氮 化矽墊層44a。利用罩幕光阻46，佈植硼雜質，形成ρ通道 金氧半元件之高濃度源和洩擴散區45，佈植劑量約1〇15至 5xl015/cm2之間，如圖十所示* 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) ----------訂·!ιι! 經濟部智慧財產局員工消費合作社印製 161051 A7 B7 五、發明說明（ 利用罩幕光阻47 ’快閃記憶元件之低濃度源擴散區上之 熱氧化矽層和場氧化物層可藉緩衝氫氟酸自動對準方式蝕 刻，如圖十一所示。將罩幕光阻4 7去除後，暴露之半導體 表面加以氧化，在溫度約850°C至1050。(：之間的乾氧環境 下成長厚度約100至150埃之間的第三熱二氧化矽層48於 快閃記憶元件之間。利用罩幕光阻50，佈植砷雜質，以形 成快閃記憶元件之高濃度源擴散區49a和洩擴散區49b及η 通道金氧半元件之高濃度源和洩極擴散區49c，佈植劑量約 1〇15至5xl〇l5/cm2之間，如圖十二所示。然後去除罩幕光 阻5〇，利用爐管或快速熱退火系統，將佈植之雜質活性化， 並且將佈植產生的晶體瑕疵去除，退火的溫度約900°C至 1 000°C之間。利用稀釋氫氟酸或緩衝氫氟酸等濕式化學品快 速泡洗或利用非等向乾式蝕刻，將快閃記憶元件及η和p通 道金氧半元件之高濃度源和洩擴散區上之熱二氧化矽層及複 晶矽閘上之熱複晶矽氧化層去除。 利用濺鍍系統，堆積一層鈦金屬薄膜，厚度約500至1000 埃厚度之間，並在溫度約600°C之氮氣環境下快速退火，在 複晶矽閘和單晶矽基板之高濃度擴散區上形成鈦化矽層51， 並在所有結構的表面形成氮化矽層52，如圖十三所示。利 用圖案化罩幕光阻53，氮化鈦層52可以利用氨水：雙氧水： 水（1 : 1 : 5)溶液加予選擇性蝕刻，以形成不同金屬層間 之連線所需之接觸面積，然後將罩幕光阻53去除。完成的 結構經氩氣的爐管退火，以降低鈦化矽和氮化矽的電阻’如 圖十四所示。 參紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · I--- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 461051 A7 __：_B7_________ 五、發明說明（） 利用電.漿增強（plasma-enhanced)化學氣相沈積法，成長 —厚介電層54，如硼磷氧化矽玻璃（BPSG)，接著利用化學 -機械磨平（CMP)法將整個結構的表面平坦化。再利用罩 幕光阻，微影蝕刻接觸洞，然後去除罩幕光阻，在850°C下 流動厚介電層54之洞口，使其圖形化。再利用濺鍍或化學 氣相沈積法，堆積約100至200埃厚度之薄氮化鈦層55， 此膜作爲上下金屬連線間之障礙金屬（barrier metal )。利用 低壓化學氣相沈積法，將氯化鎢於250至500°C之間的氫氣 環境下還原成鎢層56 ,並添滿接觸洞，再經化學-機械磨平 法將厚介電層54表面之多餘的氮化鈦和鎢去餘。然後，利 用濺鍍法，堆積一層約5000至10000埃厚度的Ml金屬層57， 再利用微影蝕刻法將Ml金屬連線形成，如圖十五所示。複 層連線可以經由金屬連線間介電層的堆積、CMP平坦化、挖 上下連線洞（via)、障礙金屬膜及鎢堆積、〇厘？平坦化、金 屬連線堆積與微影蝕刻，及重複上述步驟完成。最後，堆積 一層厚的保護介電層，利用微影蝕刻保護介電層，以露出銲 線墊。 上述所採用之鈦金屬可以由其他己知之折光金屬 (refractory metal)取代，如钽、鈷或鉬等；不同金屬層間 的介電層可以是化學氣相沈^之二氧化矽或其他低介電常數 的介電層；連線金屬可以是鋁、鋁矽銅合金或銅。 現在參考圖十六至圖十九，其中揭示本發明的第二部份 內涵。本發明之第二部份內涵包括將本發明之第一部份內涵 所揭不之可微縮化分閘式快閃記憶元件陣列的通道寬度利用 15 本紙張尺度適用尹國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------!訂·--------- 4 6 1 05 1 A7 五、發明說明（） 新的淺凹槽隔離（shallow-trench isolation)技術加以製造。. 圖十六至圖十九揭示本發明所述之快閃記憶元件陣列之通道 寬度方向的剖面圖。與圖三所示的結構相似，第一熱二氧化 矽層22成長於p型（1〇〇)單晶矽基板20內之p井21a區 上。在第一熱二氧化矽層22之上堆積第一複晶矽層23。利 用低壓化學氣相沈積法，將雙氯矽烷與氮氣於720°C反應， 堆積第三罩幕氮化矽層58，其厚度用來調整快閃記憶元件 之漂浮閘的耦合比。然後利用罩幕光阻59定義快閃記憶元 件陣列之通道寬度，如圖十六所示，並利用非等向蝕刻第三 罩幕氮化矽層58和第一複晶矽層23及部份p井21a內的單 晶矽，被蝕刻之單晶矽的厚度約2000埃。將罩幕光阻59去 除，接著在850°C乾氧環境下氧化鈾刻後之第一複晶矽23 的邊牆和蝕刻後之單晶矽凹槽的表面，成長厚度約100至150 埃的第四熱二氧化矽層61和第六熱複晶矽氧化層60。然後， 利用高密度電漿化學氣相沈積（HDPCVD)法，將矽烷或四 乙烯氧矽烷與氧反應，堆積一層良好覆蓋性厚二氧化矽膜62 並添滿凹槽，接著利用化學-機械磨平法將表面平坦化，如 圖十七所示。利用高溫磷酸，將第三罩幕氮化矽層58去除， 接著利用低壓化學氣相沈積法，在溫度約580°C至65 0°C之 間將矽烷熱分解，堆積第三良好覆蓋性複晶矽層63，厚度 約3 00至500埃之間。然後，非等向蝕刻第三良好覆蓋性複 晶矽層63,在平坦化二氧化矽層62之邊牆形成第三複晶矽 墊層63 a。接著將本發明第一部份內涵所述之第一介電層24 置於全部的結構上，如圖十八所示，然後將本發明第一部份 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)II This paper size applies to Chinese national standard (CNSM4 specification (210 X 297 mm) A7 461051 _____B7_____ V. Description of the invention) The silane is thermally decomposed at a temperature between 650 ° C, and the first good covering compound crystal is deposited. Silicon layer 33, as shown in Fig. 5. This first good covering polycrystalline silicon layer 33 is in-situ doped with phosphorus, and the impurity concentration is about 1018 to 5xl0i9 / cm3, which is not isotropically etched. The first polycrystalline silicon pad layer 33a is formed, as shown in Fig. 6. Then, the first mask silicon nitride layer 25 is removed by using high-temperature phosphoric acid. The low pressure chemical vapor deposition method is used again at 580 ° C to 650 ° C. Thermally decomposed silane at a temperature between 50 and 2000 Angstroms, a second good covering polycrystalline silicon layer 34 having a thickness of about 500 to 2000 angstroms. This second good covering polycrystalline silicon layer 34 is naturally doped with phosphorous and has a concentration of about 1 〇18 to 5xl109 / Cm3. Then use low pressure chemical vapor deposition method to react the dichlorosilane with ammonia gas at a temperature of about 720 ° C to grow a second mask nitrogen with a thickness of about 50 to 2000 angstroms. Silicon layer 35. Phosphorus is then implanted across the second mask silicon nitride layer 35 to the second good. Covering polycrystalline silicon layer 34, the impurity concentration is about 1015 to 5 ¥ 1015/0013 (not specifically shown by a separate icon). The mask photoresist 36 is used to define the η and P-channel metal-oxygen half. The gate length of the device is as shown in FIG. 7. Then, the second mask silicon nitride layer 35 and the second good coverage polycrystalline silicon layer 34 are anisotropically etched to form a second polycrystalline silicon pad layer 34 a. And 34b are on both sides of the first polycrystalline silicon pad layer 33a, and the etching of the η and p-channel metal-oxide-semiconductor half-element polycrystalline silicon gate layer 34c is completed at the same time, as shown in Fig. 8. It should be noted that the polycrystalline silicon The widths of the cushion layers 34a and 34b are mainly controlled by the thickness of the well-covered polycrystalline silicon layer < 34. Therefore, the channel length of the floating gate element and the length of the control gate element are controlled by the well-covered polycrystalline silicon The thickness of the layer is controlled to reduce the thickness. Using a mask photoresist (not shown), the boron impurity is automatically aligned across the second thermal silicon dioxide layer 31 at a dose of about 1013 to 1014 / cm2. In order to form p 12 this paper size is applicable to the national standard (CNS) A4 specification (210 297 mm) ------------- one pack ------ Order I ---------- 岣, ~ / 1 'ίV (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 1 0 5 1 A7 ____________ B7_______ 5. Description of the invention () Pass the low-concentration source of the metal-oxygen half-element and the leakage diffusion region 37, and then remove the mask photoresist. In a dry oxygen or water gas environment between about 900 ° C and 1050 ° C, The exposed second polycrystalline silicon pads 34a and 34b and the sidewalls of the polycrystalline silicon gate 34c of the eta and p-channel metal-oxide half-elements are oxidized to grow second and third thermal polycrystals with a thickness of about 200 to 300 angstroms. Silicon oxide layers 38a and 38b. Then, a non-rigidly aligned mask photoresist 39 and active ion etching are used to remove the first dielectric layer 24 and the first polycrystalline silicon layer 23, as shown in FIG. The mask photoresist 40 is used to implant the phosphorus impurities to form the low-concentration source diffusion region 41a and the drain diffusion region 41b of the flash memory element and the low-concentration source and drain of the n-channel metal-oxide half-element, and the diffusion region 42 The dopant dose is between about 1013 and 1014 / Cm2, as shown in Figure IX. After the mask photoresist 40 is removed, the second mask silicon nitride layer 35 on the first and the second polysilicon gate layer 34c of the η and p-channel metal-oxide half-elements is removed by dry etching, and then the first polysilicon is oxidized. The gate 34c is used to form a fourth thermal polycrystalline silicon oxide layer 43a, and at the same time, the side wall of the etched first polycrystalline silicon layer 23 is oxidized to form a fifth thermal polycrystalline silicon oxide layer 43b. The fourth and fifth thermally multicrystalline silicon oxide layers 43a and 43b are grown in a dry oxygen environment at a temperature of about 850 ° C to 1 050 ° C and have a thickness of about 100 to 150 Angstroms. The low-pressure chemical vapor deposition method was used to react tetraenoxysilane with ammonia at 750 ° C to deposit a first good covering silicon nitride layer 44 with a thickness of about 500 to 1,000 angstroms, followed by anisotropic etching. The first well-covered silicon nitride layer 44 forms a first silicon nitride pad layer 44a on the side walls of the flash memory element and the eta and p-channel metal-oxide half-elements. Using a mask photoresist 46, boron impurities are implanted to form a high-concentration source of the p-channel metal-oxide half-element and the leakage diffusion region 45. The implantation dose is between about 1015 and 5xl015 / cm2, as shown in Figure 10 * 13 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ---------- Order ·! Ιι! Ministry of Economy Wisdom Printed by the Consumer Affairs Cooperative of the Bureau of Property Bureau 161051 A7 B7 V. Description of the invention (The thermal silicon oxide layer and field oxide layer on the low-concentration source diffusion area of the 47 'flash memory element using the mask photoresist can be automatically buffered by hydrofluoric acid Alignment etching, as shown in Figure 11. After the mask photoresist 47 is removed, the exposed semiconductor surface is oxidized at a temperature of about 850 ° C to 1050. (The thickness grows in a dry oxygen environment between: A third thermal silicon dioxide layer 48 between 100 and 150 angstroms is between the flash memory elements. Using a mask photoresist 50, arsenic impurities are implanted to form a high-concentration source diffusion region 49a and a leak of the flash memory element. Diffusion zone 49b and high-concentration source of metal oxide half-elements and eta channel diffusion zone 49c, the implantation dose is about 1 15 to 5xlOl5 / cm2, as shown in Figure 12. Then remove the mask photoresistor 50, use the furnace tube or rapid thermal annealing system to activate the implanted impurities, and the crystals produced by the implantation Defects are removed, and the annealing temperature is between about 900 ° C and 1 000 ° C. Using wet chemicals such as diluted hydrofluoric acid or buffered hydrofluoric acid for rapid bubble washing or non-isotropic dry etching, flash memory components and The high-concentration source of the η and p-channel metal-oxide half-elements and the thermal silicon dioxide layer on the diffused diffusion region and the thermal polycrystalline silicon oxide layer on the polycrystalline silicon gate are removed. A titanium metal film is deposited with a sputtering system to a thickness of A thickness of about 500 to 1000 angstroms, and rapid annealing in a nitrogen environment at a temperature of about 600 ° C, forms a silicon titanium layer 51 on the high concentration diffusion region of the polycrystalline silicon gate and the single crystal silicon substrate, and in all structures A silicon nitride layer 52 is formed on the surface, as shown in Figure 13. Using a patterned photoresist 53, the titanium nitride layer 52 can be selectively etched with ammonia: hydrogen peroxide: water (1: 1: 5) solution. To form the contact area required for the connection between different metal layers, and then The photoresist 53 is removed. The completed structure is annealed with an argon furnace tube to reduce the resistance of silicon titanide and silicon nitride 'as shown in Figure 14. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) · I --- Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 461051 A7 __: _B7_________ 5. Invention Explanation () Using electro-plasma-enhanced chemical vapor deposition to grow a thick dielectric layer 54 such as borophosphosilicate glass (BPSG), and then chemical-mechanical smoothing (CMP) The surface of the structure is flattened. The mask photoresist is then used to lithographically etch the contact holes, and then the mask photoresist is removed, and the opening of the thick dielectric layer 54 is flowed at 850 ° C to pattern it. Then, a thin titanium nitride layer 55 with a thickness of about 100 to 200 angstroms is deposited by sputtering or chemical vapor deposition. This film serves as a barrier metal between the upper and lower metal lines. The low-pressure chemical vapor deposition method was used to reduce tungsten chloride to a tungsten layer 56 under a hydrogen atmosphere between 250 and 500 ° C, filled with contact holes, and then chemically-mechanically polished the thick dielectric layer 54 Surface excess titanium nitride and tungsten are removed. Then, a Ml metal layer 57 having a thickness of about 5000 to 10,000 angstroms is deposited by a sputtering method, and then the Ml metal line is formed by a lithographic etching method, as shown in FIG. 15. The multi-layer connection can be made through the deposition of dielectric layers between metal connections, CMP planarization, digging of upper and lower connection holes (via), barrier metal film and tungsten accumulation, 0%? The planarization, metal wiring deposition and lithographic etching are repeated, and the above steps are repeated. Finally, a thick protective dielectric layer is deposited, and the dielectric layer is protected by lithographic etching to expose the bonding pads. The titanium metal used above can be replaced by other known refractory metals, such as tantalum, cobalt, or molybdenum; the dielectric layer between different metal layers can be chemical vapor deposited silicon dioxide or other low dielectric Constant dielectric layer; the connection metal can be aluminum, aluminum silicon copper alloy or copper. Referring now to Figs. 16 to 19, the contents of the second part of the present invention are disclosed. The second part of the present invention includes a channel width of a scalable miniaturized flash memory element array that is not disclosed in the first part of the present invention. The paper size applies to the National Standard of China (CNS) A4. Specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installation --------! Order · --------- 4 6 1 05 1 A7 V. DESCRIPTION OF THE INVENTION () New shallow-trench isolation technology is manufactured. 16 to 19 are cross-sectional views of the channel width direction of the flash memory element array according to the present invention. Similar to the structure shown in FIG. 3, the first thermal silicon dioxide layer 22 is grown on the p-well 21a region in the p-type (100) single crystal silicon substrate 20. A first polycrystalline silicon layer 23 is deposited on the first thermal silicon dioxide layer 22. The low-pressure chemical vapor deposition method was used to react the dichlorosilane with nitrogen at 720 ° C to deposit a third mask silicon nitride layer 58 whose thickness was used to adjust the coupling ratio of the floating gate of the flash memory device. Then use the mask photoresistor 59 to define the channel width of the flash memory element array, as shown in FIG. 16, and use anisotropic etching to etch the third mask silicon nitride layer 58 and the first polycrystalline silicon layer 23 and parts. The thickness of the single crystal silicon in the p-well 21a is about 2000 angstroms. Remove the mask photoresist 59, and then grow the thickness of the side wall of the first polycrystalline silicon 23 and the surface of the etched single crystal silicon groove after the uranium oxide is etched in a dry oxygen environment at 850 ° C, and grow to a thickness of about 100 to 150 Angstroms. The fourth thermal silicon dioxide layer 61 and the sixth thermal polycrystalline silicon oxide layer 60. Then, using high-density plasma chemical vapor deposition (HDPCVD) method, silane or tetravinyloxysilane is reacted with oxygen to deposit a thick silicon dioxide film 62 with good coverage and fill the groove, and then use chemical-mechanical polishing The flat method flattens the surface, as shown in Figure 17. The third mask silicon nitride layer 58 is removed using high-temperature phosphoric acid, and then the silane is thermally decomposed at a temperature of about 580 ° C to 65 ° C by a low-pressure chemical vapor deposition method, and a third good covering property is deposited. The crystalline silicon layer 63 has a thickness between about 300 and 500 angstroms. Then, the third good coverage polycrystalline silicon layer 63 is anisotropically etched to form a third polycrystalline silicon pad layer 63a on the sidewall of the planarized silicon dioxide layer 62. Next, the first dielectric layer 24 described in the first part of the present invention is placed on the entire structure, as shown in FIG. 18, and then the first part 16 of the present invention is applied to the Chinese paper standard (CNS). ) A4 size (210 X 297 mm) (Please read the notes on the back before filling this page)
裝·！ I I 訂·!--I I 經濟部智慧財產局員工消費合作社印製 461051 A7 B7 五、發明說明（） 內涵所述之同樣製程將可微縮化分閘式快閃記憶元件及周邊 互補式金氧半元件製造完成。這裡値得注意的是，若將第一 介電層24變薄且將平坦化二氧化矽層62稍加以蝕刻，則第 三複晶矽墊層63a將成爲良好的配備式雙邊擦洗電極，如 圖十九所示。含蓋所述之配備式雙邊擦洗電極的淺凹槽隔離 技術和本發明之具邊牆擦洗電極的可微縮化快閃記憶元件， 本發明之可微縮化快閃記憶元件將具三邊擦洗電極，以獲得 高速擦洗的功效。 參考圖二十至圖二十二，其中揭示本發明第三部份的內 涵。本發明第三部份的內涵包括揭示一個製造修正型局部氧 化矽隔離的方法，使本發明第一部份內涵所述之具有一個邊 牆擦洗電極的可微縮化分閘式快閃記憶元件陣列能配合製 造。圖二十至圖二十一揭示修正型局部氧化矽隔離在通道寬 度方向的剖面結構。本發明之複層氧化罩結構的形成如下所 述：在P型（100)單晶矽基板20內之p井21a之上成長第一 熱二氧化矽層22,接著堆積第一複晶矽層23’再將第一介 電層（ΟΝΟ層）24置放在第一複晶矽層23上，然後接著堆積 第四罩幕氮化矽層64和第一罩幕二氧化矽層65。利用微影 蝕刻技術定義快閃記憶元件陣列的通道寬度’接著選擇性去 除第一罩幕二氧化矽層65和第四罩幕氮化矽層64 ’然後將 罩幕光阻去除。利用低壓化學氣相沈積法’在蝕刻後的複層 氧化罩結構上堆積第二良好覆蓋性氮化砍層66 ’接著非等 向蝕刻第二良好覆蓋性氮化矽層’在餓刻後的複層氧化罩結 構之邊牆形成第二氮化矽墊層66a，並自動對準餓刻第—介 17 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝----------訂---------嫂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 461051 A7 ____________ B7_. _ 五、發明說明（） 電層24和第一複晶矽層23。這裡値得注意的是，第二氮化 .矽墊層66 a的厚度是用來決定第一複晶矽層23的延伸長度， 進而決定快閃記憶元件漂浮閘的耦合比。在8 5 0 °C左右的乾 氧環境下，將第一複晶矽的邊牆氧化，成長一層約120至200 埃之間的第七熱複晶矽氧化層67。再利用低壓化學氣相沈 積法，在氧化後的複層氧化罩結構表面堆積一層薄的第三良 好覆蓋性氮化矽層68 ’接著非等向蝕刻第三良好覆蓋性氮 化矽層68，在氧化後的複層氧化罩結構邊牆形成一層薄的 第三氮化矽墊層68a。第三氮化矽墊層主要是用來蓋住氧化 後之延伸第一複晶矽的邊牆，以避免場氧化時的再氧化，同 時降低場氧化所形成的鳥嘴延伸入元件的主動區。跨過第一 熱二氧化矽層22，佈植硼雜質入P井21a內之半導體區， 以形成通道禁通區69’佈植的劑量約1〇13至1〇 l4/Cm2之間。 完成的複層氧化罩結構如圖二十所示。利用傳統場氧化的方 法，在溫度約950°C至1050°C之間的氧與水氧環境下成長場 氧化物層（field-oxide)36，並以FOX標示，完成的結構如圖 二十一所示。這裡値得一提的是，.延伸的第一複晶矽可以用 來降低場佈植雜質之侵入和鳥嘴延伸入半導體主動區，並且 形成雙邊擦洗的電極。 利用高溫磷酸，將存留的第四罩幕氮化矽層64及第二和 第三氮化矽墊層66a和68a去除，其中存留於第四罩幕氮化 矽層64之上的第一罩幕二氧化矽層將自動剝落。然後，利 用低壓化學氣相沈積法，將第一罩幕氮化矽層25堆積在全 部的結構表面上。圖二十二顯示本發明所完成之複層結構在 18 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 --In — — — — — —. - — — — fill ^ ·11111!11 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 通道寬度方向的剖面結構，與圖三是一樣的，接著微影蝕刻 第一罩幕氮化矽層25，並利用本發朋第一部份內涵所揭示 的方法製造本發明所述之具有一個邊牆擦洗的可微縮化分閘 式快閃記憶元件列陣和周邊互補金氧半元件。因此，本發明 第三部份內涵所示之具有雙邊擦洗電極和高耦合比的修正型 局部氧化矽隔離可以與本發明第一部份內涵所示之具有一個 . ... 邊牆擦洗電極的可微縮化分閘式快閃記憶元件整合製造，以 實現一個具有三邊擦洗電極之可微縮化分閘式快閃記憶元件 列陣的製造，進而達到快速擦洗的功效。 很顯然地，本發明第一部份內涵所述之具有一個邊牆擦 洗電極的可微縮化分閘式快閃記憶元件的製造方法與本發明 第二部份內涵所述之具有雙邊擦洗電極和可調變耦合比之淺 凹槽隔離的製造方法或與本發明第三部份內涵所述之具有雙 邊擦洗電極和高耦合比之修正型局部氧化矽隔離的製造方法 整合，形成一個具有三邊擦洗電極之可微縮化快閃記億元件 的完整製造方法，達成高密度、高速、低電壓及低功率運作 的快閃記憶系統，並作爲大量儲存之用。 圖三至圖二十二所示的內涵是利用一個具有深離子佈植n 井和深離子佈植P井的P型半導體基板。但對於習知此種技 藝的人亦可瞭解，相反摻雜質亦可以使用於本發明。再者， 本發明所述之分閘式快閃記憶元件亦可製造在η井上，利用 本發明之特色來製造Ρ通道分閘式快閃記憶元件。 本發明雖特別以參考所附內涵來圖示及描述，但對於習 知此種技術的人亦可瞭解，各種不同形成或細節的更動不脫 19 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1— — — — — — — — — L ^ 1 I I Γ I I I ^ <ΙΙΙΙΙΓΙ — I I.' . (請先閱讀背面之注意事項再填寫本頁) 461051 A7 _ B7_ 五、發明說明（） 離本發明的真實精神和範疇均可製造。 (請先閲讀背面之注意事項再填寫本頁) 裝----------訂----- 經濟部智慧財產局員工消費合作社印製 20 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Outfit! Order II !! II Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 461051 A7 B7 V. Description of the invention () The same process as described in the connotation will be able to miniaturize the split-type flash memory element and peripheral complementary metal-oxide semiconductor Component manufacturing is complete. It should be noted here that if the first dielectric layer 24 is thinned and the planarized silicon dioxide layer 62 is slightly etched, the third polycrystalline silicon pad layer 63a will become a good equipped bilateral scrub electrode, such as Figure 19 shows. Covering the shallow groove isolation technology of the equipped double-side scrubbing electrode and the miniaturizable flash memory element with a side wall scrubbing electrode of the present invention, the miniaturizable flash memory element of the present invention will have a three-side scrubbing electrode To get the effect of high-speed scrubbing. Referring to Figures 20 to 22, the content of the third part of the present invention is disclosed. The connotation of the third part of the present invention includes revealing a method for manufacturing a modified partial silicon oxide isolation, so that the miniaturizable split-gate flash memory element array with a side wall scrubbing electrode described in the first part of the present invention. Can cooperate with manufacturing. Figures 20 through 21 show cross-sectional structures of modified partial silicon oxide isolation in the channel width direction. The formation of the multi-layered oxide cap structure of the present invention is as follows: A first thermal silicon dioxide layer 22 is grown on the p-well 21a in the P-type (100) single-crystal silicon substrate 20, and then a first multi-layered silicon layer is deposited. 23 ', the first dielectric layer (ONO layer) 24 is placed on the first polycrystalline silicon layer 23, and then a fourth mask silicon nitride layer 64 and a first mask silicon dioxide layer 65 are deposited. The lithography etching technique is used to define the channel width of the flash memory element array ', and then the first mask silicon dioxide layer 65 and the fourth mask silicon nitride layer 64' are selectively removed, and then the mask photoresist is removed. The low-pressure chemical vapor deposition method was used to deposit a second good covering nitride layer 66 on the multi-layered oxide cap structure after etching. Then, the second good covering silicon nitride layer was anisotropically etched. The side wall of the multi-layered oxide cover structure forms a second silicon nitride cushion layer 66a, and automatically aligns with the first engraved sheet—Introduction 17 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) (please first (Please read the notes on the back and fill in this page.) ------------ Order ------------ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives of the Ministry of Economic Affairs Printed 461051 A7 ____________ B7_. _ 5. Description of the invention () Electrical layer 24 and first polycrystalline silicon layer 23. It should be noted here that the thickness of the second silicon nitride layer 66a is used to determine the extension length of the first polycrystalline silicon layer 23, and then to determine the coupling ratio of the flash memory floating gate. In a dry oxygen environment at about 850 ° C, the side wall of the first polycrystalline silicon is oxidized to grow a seventh thermal polycrystalline silicon oxide layer 67 between about 120 and 200 angstroms. Then, a low pressure chemical vapor deposition method is used to deposit a thin third good coverage silicon nitride layer 68 on the surface of the oxidized multi-layered oxide cap structure. Then, the third good coverage silicon nitride layer 68 is anisotropically etched. A thin third silicon nitride pad layer 68a is formed on the side wall of the oxidized multilayer oxide cap structure. The third silicon nitride pad layer is mainly used to cover the side wall of the first polycrystalline silicon after the oxidation to avoid re-oxidation during field oxidation, and at the same time reduce the bird's beak formed by the field oxidation into the active area of the device. . Crossing the first thermal silicon dioxide layer 22, boron impurities are implanted into the semiconductor region in the P well 21a to form a channel forbidden region 69 '. The implantation dose is between about 1013 and 10 l / Cm2. The completed multi-layer oxidation cover structure is shown in Figure 20. Using the traditional field oxidation method, a field-oxide layer 36 is grown under the environment of oxygen and water oxygen at a temperature of about 950 ° C to 1050 ° C, and is labeled with FOX. The completed structure is shown in Figure 20. As shown. It is worth mentioning here that the first extended polycrystalline silicon can be used to reduce the invasion of field implant impurities and the extension of the bird's beak into the semiconductor active area, and form a bilaterally scrubbed electrode. Using the high-temperature phosphoric acid, the remaining fourth mask silicon nitride layer 64 and the second and third silicon nitride pad layers 66a and 68a are removed. The first mask remaining on the fourth mask silicon nitride layer 64 is removed. The curtain silicon dioxide layer will peel off automatically. Then, the first mask silicon nitride layer 25 is deposited on the entire structure surface by a low-pressure chemical vapor deposition method. Figure 22 shows that the multi-layer structure completed by the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) at 18 paper sizes. --In — — — — — — — — — — fill ^ · 11111! 11 (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention () The cross-sectional structure in the channel width direction is the same as that in Figure 3. Lithographically etching the first mask silicon nitride layer 25, and using the method disclosed in the first part of the present invention to fabricate the micro-divided split-gate flash memory array with a side wall scrubbing according to the present invention Array and peripheral complementary metal-oxide half-elements. Therefore, the modified partial silicon oxide isolation with bilateral scrubbing electrodes and high coupling ratio shown in the third part of the present invention can be separated from the one shown in the first part of the present invention. ... The integrated manufacturing of a micro-scale split-type flash memory element with a side-wall scrubbing electrode to achieve the manufacture of a micro-scale micro-type split-type flash memory element with a three-side scrub electrode Efficacy of quick scrubbing. Obviously, the manufacturing method of a micronizable split-type flash memory device with a side wall scrubbing electrode described in the first part of the present invention and the second part of the present invention The manufacturing method of a shallow groove isolation with a bilateral scrubbing electrode and an adjustable coupling ratio or integration with the manufacturing method of a modified partial silicon oxide isolation with a bilateral scrubbing electrode and a high coupling ratio as described in the third part of the present invention, Form a complete manufacturing method of miniaturized flash memory devices with three-side scrubbing electrodes to achieve high-density, high-speed, low-voltage, and low-power operation of flash memory systems, and for mass storage. Figures 3 to 2 The connotation shown in Figure 12 is to use a P-type semiconductor substrate with a deep ion implanted n-well and a deep ion implanted P-well. However, those skilled in the art can also understand that the opposite dopant can also be used in In addition, the split-type flash memory element described in the present invention can also be manufactured on the η well, and the features of the present invention can be used to manufacture a P-channel split-type flash memory element. Although the Ming is specifically illustrated and described with reference to the attached connotation, those who are familiar with this technology can also understand that various formations or details can be changed. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) 1 — — — — — — — — — — L ^ 1 II Γ III ^ < ΙΙΙΙΙΓΓ—I I. '. (Please read the notes on the back before filling this page) 461051 A7 _ B7_ Five 2. Description of the invention () It can be manufactured without the true spirit and scope of the present invention. (Please read the notes on the back before filling this page) Printed by the Property Bureau's Consumer Cooperatives 20 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)