TWI446847B - 佈線板，其製造方法及半導體封裝 - Google Patents

佈線板，其製造方法及半導體封裝 Download PDF

Info

Publication number
TWI446847B
TWI446847B TW098115511A TW98115511A TWI446847B TW I446847 B TWI446847 B TW I446847B TW 098115511 A TW098115511 A TW 098115511A TW 98115511 A TW98115511 A TW 98115511A TW I446847 B TWI446847 B TW I446847B
Authority
TW
Taiwan
Prior art keywords
wiring
layer
wiring board
wiring layer
disposed
Prior art date
Application number
TW098115511A
Other languages
English (en)
Chinese (zh)
Other versions
TW201002171A (en
Inventor
Toshihisa Yoda
Shunichiro Matsumoto
Masako Sato
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW201002171A publication Critical patent/TW201002171A/zh
Application granted granted Critical
Publication of TWI446847B publication Critical patent/TWI446847B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
TW098115511A 2008-05-15 2009-05-11 佈線板，其製造方法及半導體封裝 TWI446847B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008128196A JP2009277916A (ja) 2008-05-15 2008-05-15 配線基板及びその製造方法並びに半導体パッケージ

Publications (2)

Publication Number Publication Date
TW201002171A TW201002171A (en) 2010-01-01
TWI446847B true TWI446847B (zh) 2014-07-21

Family

ID=41315960

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098115511A TWI446847B (zh) 2008-05-15 2009-05-11 佈線板，其製造方法及半導體封裝

Country Status (5)

Country Link
US (1) US8119927B2 (enExample)
JP (1) JP2009277916A (enExample)
KR (1) KR101550467B1 (enExample)
CN (1) CN101582406A (enExample)
TW (1) TWI446847B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011138868A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板
JP5623308B2 (ja) * 2010-02-26 2014-11-12 日本特殊陶業株式会社 多層配線基板及びその製造方法
TWI419277B (zh) * 2010-08-05 2013-12-11 日月光半導體製造股份有限公司 線路基板及其製作方法與封裝結構及其製作方法
US20120032337A1 (en) * 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
US20120152606A1 (en) * 2010-12-16 2012-06-21 Ibiden Co., Ltd. Printed wiring board
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
JP2013135080A (ja) * 2011-12-26 2013-07-08 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
JP6316609B2 (ja) 2014-02-05 2018-04-25 新光電気工業株式会社 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法
KR20160010960A (ko) * 2014-07-21 2016-01-29 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN106817836A (zh) * 2015-12-02 2017-06-09 富葵精密组件(深圳)有限公司 电路板及其制作方法
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US20240074048A1 (en) * 2022-08-23 2024-02-29 Micron Technology, Inc. Semiconductor packaging with reduced standoff height

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04286392A (ja) * 1991-03-15 1992-10-12 Fujitsu Ltd 印刷回路基板
JPH1126945A (ja) * 1997-07-07 1999-01-29 Toagosei Co Ltd 多層プリント配線板の製造方法
KR20070086860A (ko) * 1998-09-03 2007-08-27 이비덴 가부시키가이샤 다층프린트배선판 및 그 제조방법
JP4127442B2 (ja) * 1999-02-22 2008-07-30 イビデン株式会社 多層ビルドアップ配線板及びその製造方法
JP3232562B2 (ja) 1999-10-22 2001-11-26 日本電気株式会社 電磁干渉抑制部品および電磁干渉抑制回路
JP2002289911A (ja) * 2000-12-06 2002-10-04 Ibiden Co Ltd 光通信用デバイス
JP3910379B2 (ja) * 2001-06-12 2007-04-25 インターナショナル・ビジネス・マシーンズ・コーポレーション ボール・グリッド・アレイ・モジュール用の多層基板の製造方法
JP2003152311A (ja) 2001-11-15 2003-05-23 Ngk Spark Plug Co Ltd 配線基板の製造方法

Also Published As

Publication number Publication date
US8119927B2 (en) 2012-02-21
CN101582406A (zh) 2009-11-18
KR101550467B1 (ko) 2015-09-04
US20090284943A1 (en) 2009-11-19
TW201002171A (en) 2010-01-01
KR20090119704A (ko) 2009-11-19
JP2009277916A (ja) 2009-11-26

Similar Documents

Publication Publication Date Title
TWI446847B (zh) 佈線板，其製造方法及半導體封裝
US6545353B2 (en) Multilayer wiring board and semiconductor device
JP4061318B2 (ja) メッキによるチップ内蔵型プリント回路基板およびその製造方法
US7256495B2 (en) Package substrate manufactured using electrolytic leadless plating process, and method for manufacturing the same
CN102111951B (zh) 多层布线基板
JP2006019441A (ja) 電子部品内蔵基板の製造方法
TWI479972B (zh) Multi - layer flexible printed wiring board and manufacturing method thereof
JP2000165049A (ja) 多層回路基板の製造方法
JP3577421B2 (ja) 半導体装置用パッケージ
CN101325845B (zh) 多层印刷电路板及其制造方法
JP2020088005A (ja) 配線基板及び半導体装置
KR101614856B1 (ko) 반도체 칩의 실장 기판, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
JP2005236067A (ja) 配線基板と配線基板の製造方法、および半導パッケージ
KR101089986B1 (ko) 캐리어기판, 그의 제조방법, 이를 이용한 인쇄회로기판 및 그의 제조방법
JP2010103435A (ja) 配線基板及びその製造方法
TWI651022B (zh) 多層線路結構及其製作方法
EP1708552A2 (en) Method of production of circuit board utilizing electroplating
JP4906903B2 (ja) 電子部品内蔵基板の製造方法
TWI393229B (zh) 封裝基板的製作方法及其結構
KR101068539B1 (ko) 전해 도금을 이용한 배선 기판의 제조 방법
JP2005236220A (ja) 配線基板と配線基板の製造方法、および半導パッケージ
JP3770895B2 (ja) 電解めっきを利用した配線基板の製造方法
KR101501902B1 (ko) 금속 포스트를 구비한 인쇄회로기판 및 이의 제조 방법
US11935822B2 (en) Wiring substrate having metal post offset from conductor pad and method for manufacturing wiring substrate
KR20040076165A (ko) 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법