CN101582406A - 配线基板、配线基板的制造方法以及半导体封装件 - Google Patents

配线基板、配线基板的制造方法以及半导体封装件 Download PDF

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Publication number
CN101582406A
CN101582406A CNA2009101404478A CN200910140447A CN101582406A CN 101582406 A CN101582406 A CN 101582406A CN A2009101404478 A CNA2009101404478 A CN A2009101404478A CN 200910140447 A CN200910140447 A CN 200910140447A CN 101582406 A CN101582406 A CN 101582406A
Authority
CN
China
Prior art keywords
wiring layer
wiring
wiring substrate
external connection
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2009101404478A
Other languages
English (en)
Chinese (zh)
Inventor
依田稔久
松元俊一郎
佐藤雅子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN101582406A publication Critical patent/CN101582406A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
CNA2009101404478A 2008-05-15 2009-05-15 配线基板、配线基板的制造方法以及半导体封装件 Pending CN101582406A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008128196 2008-05-15
JP2008128196A JP2009277916A (ja) 2008-05-15 2008-05-15 配線基板及びその製造方法並びに半導体パッケージ

Publications (1)

Publication Number Publication Date
CN101582406A true CN101582406A (zh) 2009-11-18

Family

ID=41315960

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2009101404478A Pending CN101582406A (zh) 2008-05-15 2009-05-15 配线基板、配线基板的制造方法以及半导体封装件

Country Status (5)

Country Link
US (1) US8119927B2 (enExample)
JP (1) JP2009277916A (enExample)
KR (1) KR101550467B1 (enExample)
CN (1) CN101582406A (enExample)
TW (1) TWI446847B (enExample)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102111952A (zh) * 2009-12-28 2011-06-29 日本特殊陶业株式会社 多层布线基板
CN102376667A (zh) * 2010-08-06 2012-03-14 台湾积体电路制造股份有限公司 封装装置及其制造方法
CN103179811A (zh) * 2011-12-26 2013-06-26 日本特殊陶业株式会社 多层配线基板的制造方法
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9087882B2 (en) 2011-06-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9224680B2 (en) 2011-10-07 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5623308B2 (ja) * 2010-02-26 2014-11-12 日本特殊陶業株式会社 多層配線基板及びその製造方法
TWI419277B (zh) * 2010-08-05 2013-12-11 日月光半導體製造股份有限公司 線路基板及其製作方法與封裝結構及其製作方法
US20120152606A1 (en) * 2010-12-16 2012-06-21 Ibiden Co., Ltd. Printed wiring board
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
JP6316609B2 (ja) 2014-02-05 2018-04-25 新光電気工業株式会社 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法
KR20160010960A (ko) * 2014-07-21 2016-01-29 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN106817836A (zh) * 2015-12-02 2017-06-09 富葵精密组件(深圳)有限公司 电路板及其制作方法
US20180350630A1 (en) * 2017-06-01 2018-12-06 Qualcomm Incorporated Symmetric embedded trace substrate
US20240074048A1 (en) * 2022-08-23 2024-02-29 Micron Technology, Inc. Semiconductor packaging with reduced standoff height

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04286392A (ja) * 1991-03-15 1992-10-12 Fujitsu Ltd 印刷回路基板
JPH1126945A (ja) * 1997-07-07 1999-01-29 Toagosei Co Ltd 多層プリント配線板の製造方法
JP2002289911A (ja) * 2000-12-06 2002-10-04 Ibiden Co Ltd 光通信用デバイス
US20020187585A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Ball grid array module and method of manufacturing same
US20040025333A1 (en) * 1998-09-03 2004-02-12 Ibiden Co., Ltd. Multilayered printed circuit board and manufacturing method therefor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4127442B2 (ja) * 1999-02-22 2008-07-30 イビデン株式会社 多層ビルドアップ配線板及びその製造方法
JP3232562B2 (ja) 1999-10-22 2001-11-26 日本電気株式会社 電磁干渉抑制部品および電磁干渉抑制回路
JP2003152311A (ja) 2001-11-15 2003-05-23 Ngk Spark Plug Co Ltd 配線基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04286392A (ja) * 1991-03-15 1992-10-12 Fujitsu Ltd 印刷回路基板
JPH1126945A (ja) * 1997-07-07 1999-01-29 Toagosei Co Ltd 多層プリント配線板の製造方法
US20040025333A1 (en) * 1998-09-03 2004-02-12 Ibiden Co., Ltd. Multilayered printed circuit board and manufacturing method therefor
JP2002289911A (ja) * 2000-12-06 2002-10-04 Ibiden Co Ltd 光通信用デバイス
US20020187585A1 (en) * 2001-06-12 2002-12-12 International Business Machines Corporation Ball grid array module and method of manufacturing same

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102111952B (zh) * 2009-12-28 2014-06-04 日本特殊陶业株式会社 多层布线基板
CN102111952A (zh) * 2009-12-28 2011-06-29 日本特殊陶业株式会社 多层布线基板
CN102376667A (zh) * 2010-08-06 2012-03-14 台湾积体电路制造股份有限公司 封装装置及其制造方法
US9515038B2 (en) 2011-06-03 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9087882B2 (en) 2011-06-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9741659B2 (en) 2011-10-07 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9224680B2 (en) 2011-10-07 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
CN103179811A (zh) * 2011-12-26 2013-06-26 日本特殊陶业株式会社 多层配线基板的制造方法
US10515917B2 (en) 2012-07-31 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure in semiconductor packaged device
US10163839B2 (en) 2012-07-31 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure in semiconductor packaged device
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9748188B2 (en) 2012-07-31 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9397059B2 (en) 2012-08-17 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US10468366B2 (en) 2012-08-17 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9123788B2 (en) 2012-08-17 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US11088102B2 (en) 2012-08-17 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate

Also Published As

Publication number Publication date
US8119927B2 (en) 2012-02-21
KR101550467B1 (ko) 2015-09-04
TWI446847B (zh) 2014-07-21
US20090284943A1 (en) 2009-11-19
TW201002171A (en) 2010-01-01
KR20090119704A (ko) 2009-11-19
JP2009277916A (ja) 2009-11-26

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Application publication date: 20091118