TWI423430B - 具有三維排列記憶胞之nand快閃記憶體裝置以及其製造方法 - Google Patents

具有三維排列記憶胞之nand快閃記憶體裝置以及其製造方法 Download PDF

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TWI423430B
TWI423430B TW096137829A TW96137829A TWI423430B TW I423430 B TWI423430 B TW I423430B TW 096137829 A TW096137829 A TW 096137829A TW 96137829 A TW96137829 A TW 96137829A TW I423430 B TWI423430 B TW I423430B
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semiconductor layer
source
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plug
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Yang-Soo Son
Young-Seop Rah
Won-Seok Cho
Soon-Moon Jung
Jae-Hoon Jang
Young-Chul Jang
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Samsung Electronics Co Ltd
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Description

具有三維排列記憶胞之NAND快閃記憶體裝置以及其製造方法

本發明是有關於一種半導體裝置的製造方法,且特別是有關於一種具有三維排列記憶胞之NAND快閃記憶體裝置的製造方法。

本申請案主張於2006年10月11日向韓國智慧財產局提出申請之韓國專利申請案第2006-99015號的優先權,該專利申請案所揭露之內容系完整結合於本說明書中。

大多數現代化電子設備都會包括半導體裝置。這些半導體裝置包括一些元件。這些半導體裝置特別包括例如電晶體、電阻器、電容器等等的電子元件。在最佳情況下,這些電子元件在其被設計來執行電子設備的特定功能之後是被集成於半導體基片上。例如,像是電腦與數位相機等電子設備包括用以儲存資訊的記憶晶片以及用以處理資訊的處理晶片。這些記憶晶片與處理晶片包括電子元件,其在分別被設定來執行資訊儲存與處理功能之後被集成於半導體基片上。

為了趕上客戶對於低價、有效率、以及小尺寸的裝置的需求,越來越需要高度集成的半導體裝置。然而,在半導體製程中存在某些會影響高度集成的半導體裝置的效用的缺點。例如,需要用到先進的處理技術,像是微影(lithography)技術。然而,先進的處理技術需要大量資金的支出,而且在其可商業化製造高度集成的半導體裝置之前可能長時間受困於研發週期。

為了在目前的製造技術所定的限制附近運作,已經有人建議在半導體裝置中使用三維排列電晶體。例如,韓國專利申請案第2006-73858號揭露一種具有三維排列電晶體之NAND快閃記憶體裝置。此種半導體裝置的製造方法包括藉由磊晶(epitaxial)技術在作為半導體基片的晶圓上形成單晶半導體層,之後便在半導體層上形成電晶體。

此外,當記憶胞電晶體的源極及汲極電極是三維排列時,需要用連接這些源極及汲極電極的插塞(plugs)來電性存取記憶胞電晶體。然而,可能不易形成這些插塞於三維半導體裝置中。例如,在韓國專利申請案第2006-73858號所揭露的NAND快閃記憶體裝置中,形成於不同層上的記憶體電晶體將經由以不同製程形成的堆疊插塞及區域互連來彼此電性連接。

可能有許多與使用不同程序來製造三維半導體裝置有關的問題。這些問題可能包括例如整個製程的複雜度增加以及製造成本的增加。藉由減少有效晶片面積可能降低半導體裝置的複雜度。然而,晶片面積有效性的損失可能降低半導體裝置的集成密度。這特徵與三維半導體裝置的重要目標之一相反。

在本發明的一方面,提供一種NAND快閃記憶體裝置,包括:下半導體層及位於下半導體層上方的上半導體層;位於下半導體層中的第一汲極區及第一源極區;以及位於上半導體層中的第二汲極區及第二源極區。第一閘極結構位於下半導體層上,而第二閘極結構則位於上半導體層上。位元線(bit line)位於上半導體層的上方,並且至少一個位元線插塞連接在位元線與第一汲極區之間,其中上述至少一個位元線插塞經由位於上半導體層中的汲極通孔(throughhole)延伸。

在本發明的另一方面,提供一種NAND快閃記憶體裝置的製造方法,包括:在下半導體層中形成下源極區及下汲極區;在下半導體層的上方形成上半導體層,上半導體層包括汲極通孔、上源極區、以及上汲極區;以及形成至少一個位元線插塞,其經由汲極通孔延伸且連接上及下汲極區。

以下將參考附圖更詳細地說明本發明的較佳實施例。然而,本發明可能以不同的形式來實施,因此不應視為侷限於在此所述之實施例。相反地,提供這些實施例將使得此揭露更為徹底且完全,並將完整地傳達本發明的觀念給熟習此技藝者

須知當提到一分層(或薄膜)位於另一分層或基片的”上方”時,可能直接位於此另一分層或基片上,或者也可能存在中介層。並且,須知當提到一分層位於另一分層的”下方”時,可能直接位於此分一分層的下方,或者也可能存在一層或多層中介層。此外,須知當提到一分層位於兩分層”之間”時,可能是此兩分層之間的唯一分層,或者也可能存在一層或多層中介層。同樣地,須知當提到一元件”連接”另一元件時,此兩元件可能彼此直接連接,或者可能彼此操作上(例如電性)連接。在圖中,為了清楚起見可能誇大圖中分層及區域的尺寸。在說明書中,雖然術語”第一”、”第二”、”第三”等等用以說明各種區域、分層等等,但是這些區域、分層等等不應受限於這些術語。這些術語僅用以讓這些區域和分層區分彼此。因此,當可稱一實施例中所提及的第一分層為另一實施例中所提及的第二分層。在此所述的每一實施例可能包括其互補實施例。

圖1A至1D是根據較佳實施例之NAND快閃記憶體裝置的記憶胞陣列的平面圖。並且,圖2A至2C是根據較佳實施例之NAND快閃記憶體裝置的記憶胞陣列的斷面圖。尤其,圖2A至2C分別是沿著圖1A至1D的虛線I-I’所截取的斷面圖。

參照圖1A及2A,較佳實施例之NAND快閃記憶體裝置包括下半導體層100,以及位於下半導體層100上的上半導體層200。為求簡潔明暸,將只繪示較佳實施例之一層上半導體層。然而,熟習此技藝者應當理解在不脫離本發明的範疇的情況下可能有多層上半導體層位於下半導體層100上。並且,下半導體層100可能是由單晶半導體材料所構成的晶圓。此外,上半導體層200最好是由單晶半導體材料所構成的,稍後將予以詳述。

下閘極結構120與上閘極結構220分別位於下半導體層100與上半導體層200的上方。並且,下及上閘極結構120及220等兩者都包括字串選擇線(string selection line)SSL、接地選擇線(ground selection line)GSL、以及多條位於字串選擇線SSL與接地選擇線GSL之間的字元線(word line)WL。此外,下閘極絕緣層105可能位於下閘極結構120與下半導體層100之間,且上閘極絕緣層205可能位於上閘極結構220與上半導體層200之間。

在一較佳實施例中,下閘極結構120包括下浮動電極121、下閘極層間絕緣層122、以及下控制電極123,以上皆依序堆疊。同樣地,上閘極結構220包括上浮動電極221、上閘極層間絕緣層222、以及上控制電極223。此外,下及上覆蓋圖案124及224可能附帶地分別位於下及上控制電極123及223上。

在字元線WL中,下及上浮動電極121及221並未分別電性連接下及上控制電極123及223。下及上浮動電極121及221分別與下及上控制電極123及223之間的這種缺乏電性連接是因為下及上閘極層間絕緣層122及222介於其間。相對地,在字串選擇線SSL及接地選擇線GSL中,下及上浮動電極121及221分別電性連接下及上控制電極123及223。為此,可能形成下及上閘極層間絕緣層122及222以使下及上浮動電極121及221的頂面部分曝露出來。

在另一較佳實施例中,下及上閘極結構120及220(以下,稱之為閘極結構)可能具有電荷擷取型快閃記憶體(charge trap type flash memory)的記憶胞閘極結構。例如,閘極結構120及220可能是知名的矽-氧化矽-氮化矽-氧化矽-矽(SONOS)或鉭-氧化鋁-氮化物-氧化物-晶矽層(TANOS)結構。在此例中,可能不需要形成下及上閘極絕緣層105及205。

在下半導體層100中,下雜質區110分別形成於字串選擇線SSL與相鄰的字元線WL之間、字元線WL之間、以及接地選擇線GSL與相鄰的字元線WL之間。並且,在下閘極結構120的任一邊,將形成下源極區110S及下汲極區110D。尤其,下源極區110S將與接地選擇線GSL相鄰,且下汲極區110D將與字串選擇線SSL相鄰。並且,在上半導體層200中,上雜質區210、上源極區210S、以及上汲極區210D分別形成於下雜質區110、下源極區110S、以及下汲極區110D的上方。此外,雜質區具有不同於下及上半導體層100及200的導電類型。

閘極間隙壁(gate spacer)129及229可能位於字串選擇線SSL、接地選擇線GSL、以及字元線WL的每一條線的側邊。在一較佳實施例中,如圖2B所示,閘極間隙壁129及229可能由氧化矽或氮化矽所構成。並且,回到圖2A,下層間絕緣層140形成於下半導體層100與上半導體層200之間,而上層間絕緣層240則形成於上半導體層200上。在一較佳實施例中,下及上層間絕緣層140及240可能包括氧化矽或氮化矽當中至少一種。

並且,上蝕刻終止層(upper etch stop layer)230可能形成於上半導體層200上。尤其,具有預定厚度的上蝕刻終止層230可能覆蓋用以形成上閘極結構220的上半導體層200。上蝕刻終止層230最好由相對於上層間絕緣層240具有蝕刻選擇性的材料所構成。

此外,下蝕刻終止層(lowet etch stop layer)130可能形成於下半導體層100的上方。尤其,具有預定厚度的下蝕刻終止層130可能保形覆蓋用以形成下閘極結構120的下半導體層100。在最佳情況下,下蝕刻終止層130由相對於上層間絕緣層240具有蝕刻選擇性的材料所構成。當下及上蝕刻終止層130及230由彼此不具有蝕刻選擇性的材料所構成時(例如,若其由相同的材料所構成),所形成的上蝕刻終止層230最好是比下蝕刻終止層130厚,以避免造成上半導體層200的蝕刻損害,這些稍後將予以說明。

參照圖1A,多條跨越字元線WL的位元線BL形成於上層間絕緣層240上。此外,與字元線WL平行的共同源極線CSL位於上半導體層200上。依據垂直高度,共同源極線CSL可能位於上半導體層200與位元線BL之間。此外,參照圖2A,位元線BL藉由位元線插塞400電性連接下及上汲極區110D及210D。因此,位元線插塞400穿過下及上層間絕緣層140及240。並且,共同源極線CSL藉由源極插塞300連接下及上源極區110S及210S。源極插塞300穿過下及上層間絕緣層140及240。

如圖2A所示,上層間絕緣層240可能包括圍繞共同源極線CSL的第一上層間絕緣層241,以及位於共同源極線CSL上的第二上層間絕緣層242。並且,在一較佳實施例中,穿過上半導體層200的汲極通孔501與源極通孔502形成於位在下汲極區110D與下源極區110S上方的上半導體層200。並且,位元線插塞400通過汲極通孔501以便連接下汲極區110D,而源極插塞300則通過源極通孔502以便連接下源極區110S。此外,如圖1A所示,一條位元線BL經由一個位元線插塞400連接一個下汲極區110D,而共同源極線CSL與源極插塞卻連接多個下源極區110S。

在一較佳實施例中,位元線插塞400可能由其導電類型與下及上汲極區110D及210D相同的多晶矽所組成。在此例中,位元線插塞400可能在汲極通孔501的側壁與上半導體層200接觸。此時,因為上半導體層200與位元線插塞400具有不同的導電類型,所以其形成PN二極體。此PN二極體可能當作整流器(rectifier)。結果,當施加反向電壓至位元線插塞400時,此電壓並未被施加至上半導體層200。亦即,位元線插塞400與上半導體層200可能是電性獨立的。

在另一較佳實施例中,位元線插塞400可能由金屬材料所構成,例如鎢、鈦、鉭、氮化鈦、氮化鉭、以及氮化鎢。在此例中,為了互相電性隔離位元線插塞400與上半導體層200,如圖2B所示之汲極絕緣層155可能形成於位元線插塞400的側壁上。汲極絕緣層155可能利用知名的間隙壁形成製程來形成。

在一較佳實施例中,位元線插塞400可能分為兩部分,其中一部分是位於上半導體層200上方的上位元線插塞,而另一部分則是穿過上半導體層200的下位元線插塞。並且,所形成的上位元線插塞的寬度可能大於汲極通孔501的寬度G1,如圖1A、1B、1D、以及2A所示。因此,上位元線插塞將連接到形成於汲極通孔501的任一邊的上汲極區210D。此外,所形成的下位元線插塞的寬度可能小於或等於汲極通孔501的寬度G1。並且,下位元線插塞由上位元線插塞的底面接續地延伸以致連接到下汲極區110D。

在另一較佳實施例中,參照圖1C及2C,位元線插塞400可能被設定為具有上位元線插塞402及下位元線插塞401。在此,上位元線插塞402彼此隔離。在此例中,上位元線插塞402電性連接位元線BL與上汲極區210D,而下位元線插塞401則電性連接位元線BL與下汲極區110D。並且,雖然上位元線插塞402與下位元線插塞401在實體上彼此分離,但是因為其共同連接位元線BL所以其形成等電位。

在一較佳實施例中,源極插塞300可能由其導電類型與下及上源極區110S及210S相同的多晶矽所構成。在此例中,源極插塞300可能在源極通孔502的側壁與上半導體層200接觸。因為上半導體層200與源極插塞300具有不同的導電類型,所以其形成當作整流器的PN二極體。因此,當施加反向電壓至源極插塞300時,並未施加此電壓至上半導體層200。亦即,源極插塞300與上半導體層200可能是電性獨立的。

在另一較佳實施例中,源極插塞300可能由例如鎢、鈦、鉭、氮化鈦、氮化鉭、以及氮化鎢的金屬材料之一所構成。在此例中,源極絕緣層156可能形成於源極插塞300的側壁上,以便電性隔離源極插塞300與上半導體層200。源極絕緣層156可能利用知名的間隙壁形成製程來形成。

在另一較佳實施例中,上半導體層200與下半導體層100可能利用下及上源極區110S及210S來形成等電位。在此例中,並未形成源極絕緣層156,而且源極插塞300可能包括位障金屬層以便與下及上半導體層100及200產生歐姆接觸。

在一較佳實施例中,源極插塞300可能分為兩部分,其中一部分是位於上半導體層200上方的上源極插塞,而另一部分則是穿過上半導體層200的下源極插塞。並且,所形成的上源極插塞的寬度可能大於源極通孔502的寬度G2,如圖1A、1B、1D、以及2A所示。因此,上源極插塞將連接到形成於源極通孔502的任一邊的上源極區210S。此外,所形成的下源極插塞的寬度小於或等於源極通孔502的寬度G2。並且,下源極插塞由上源極插塞的底面接續地延伸以便連接到下源極區110S。

在另一較佳實施例中,如圖1C及2C所示,源極插塞300可能被設定為具有多個上源極插塞302及下源極插塞301,其中上源極插塞302彼此隔離。在此例中,上源極插塞302電性連接共同源極線CSL與上源極區210S,而下源極插塞301則電性連接共同源極線CSL與下源極區110S。並且,可能利用鑲嵌製程(damascene process)同時形成共同源極線CSL與下及上源極插塞301及302。在此例中,上源極插塞302與下源極插塞301形成等電位,如圖2C所示。

圖3A至3D是根據一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。以下,將參考圖3A至3D詳細說明形成位元線插塞400及源極插塞300的方法。

參照圖3A,下閘極結構120形成於下半導體層100上。其後,將利用下閘極結構120執行離子植入(ion implantation)製程作為用以形成下半導體層100中的下雜質區110、下源極區110S、以及下汲極區110D的離子光罩(ion mask)。接著,下蝕刻終止層130與下層間絕緣層140依序形成於其中形成下閘極結構120的合成結構上。

此外,上半導體層200形成於下層間絕緣層140上。如上所述,上半導體層200具有汲極通孔501及源極通孔502。在一較佳實施例中,可能利用各種方法來形成上半導體層200。以下,在說明形成位元線插塞400及源極線插塞300的方法之前,將參考圖5A、5B、6A至6C、7A及7B來說明形成上半導體層200的方法。

在一較佳實施例中,可能利用以下半導體層100作為晶種層(seed layer)的磊晶技術(epitaxial technology)來形成上半導體層200。尤其,在形成下層間絕緣層140之後,可能形成種晶孔(seedhole)88於下層間絕緣層140中以使下半導體層100的預定區域曝露出來,如圖1A、1C、5A以及5B所示。在此,圖5A及5B分別是沿著圖1A及1C的虛線I-I’及Ⅱ-Ⅱ’所截取的斷面圖。接著,利用許多磊晶技術當中一種來形成充填種晶孔88的種晶插塞(seed plug)99,以及覆蓋下層間絕緣層140的磊晶半導體層199。並且,磊晶半導體層199由種晶插塞99延伸。磊晶製程的結果是磊晶半導體層199可能具有單晶結構。其後,參照圖5B,將圖案化磊晶半導體層199以形成具有汲極通孔501及源極通孔502的上半導體層200。在一較佳實施例中,在圖案化磊晶半導體層199之前,可能利用例如化學機械研磨(chemical mechanical polishing,CMP)等等的平面化技術來額外執行平面化磊晶半導體層199頂面的製程。

在另一較佳實施例中,可能利用晶圓接合(wafer-bonding)技術來形成上半導體層200。尤其,參照圖6A,在形成下層間絕緣層140之後,由單晶半導體所構成的晶圓WF可能與下層間絕緣層140接合。尤其,可能在晶圓WF與下層間絕緣層140之間額外形成附著層(adhesive layer)以便接合晶圓WF與下層間絕緣層140。並且,參照圖6B及6C,將蝕刻晶圓WF以形成薄半導體層199’,之後將圖案化薄半導體層199’以形成具有汲極通孔501及源極通孔502的上半導體層200。如圖1B及1D所示,在此實施例中並不需要上述磊晶技術所需之用以形成種晶孔88的額外區域。

在另一較佳實施例中,可能利用沈積及結晶製程來形成上半導體層200。尤其,如圖7A所示,將形成鑄模圖案(mold pattern)195以劃定汲極通孔501及源極通孔502的位置。接著,將沈積半導體層198於包括鑄模圖案195的合成結構上。尤其,可能利用化學氣相沈積(chemical vapor deposition,CVD)或(atomic layer deposition,ALD)製程來形成半導體層198。在較佳實施例中,半導體層198可能是非晶矽、多晶矽、以及單晶矽其中之一。並且,可能額外執行預定結晶製程使半導體層198具有單晶結構。其後,參照圖7B,將在半導體層198上執行平面化蝕刻直到使鑄模圖案195的頂面曝露出來為止。因此,上半導體層200形成於鑄模圖案195所劃定的空間。在此例中,因為利用鑄模圖案195作為鑄模來形成上半導體層200,所以不需要額外的圖案化製程就可形成穿過上半導體層200的汲極通孔501及源極通孔502。

回頭參照圖3A,上閘極結構220形成於上半導體層200上。其後,將利用上閘極結構220作為離子光罩來執行離子植入製程,以便在上半導體層200中形成上雜質區210、上源極區210S、以及上汲極區210D。接著,上蝕刻終止層230與第一上層間絕緣層241依序形成於包括上閘極結構220的合成結構上。

並且,將圖案化第一上層間絕緣層241及下層間絕緣層140以形成源極接觸孔150。這些源極接觸孔150穿過源極通孔502且使下源極區110S曝露出來。並且,源極接觸孔150形成於上半導體層200的上方使得其寬度大於源極通孔502的寬度,因而使上源極區的頂面曝露出來。此外,將形成上蝕刻終止層230以避免在源極接觸孔150的形成期間造成上半導體層200(例如,特別是上源極區210S)的蝕刻損害。亦即,源極接觸孔150的形成包括利用相對於上蝕刻終止層230具有蝕刻選擇性的蝕刻配方(etch recipe)來蝕刻第一上層間絕緣層241及下層間絕緣層140。此外,所形成的上蝕刻終止層230最好是比下蝕刻終止層130厚,以避免在下蝕刻終止層130的蝕刻期間損害上半導體層200的頂面。

參照圖3B,在一較佳實施例中,將形成充填源極接觸孔150的源極插塞300以及共同源極線CSL。因此,將利用鑲嵌製程來形成源極接觸孔及源極插塞300。另一方面,根據另一較佳實施例,可能利用雙鑲嵌製程(dual damascene process)來形成源極插塞300,如圖4A至4C所示。參照圖4A至4C,第一上層間絕緣層241可能包括依序堆疊的第一至第三絕緣層241a、241b、以及241c。將圖案化第一上層間絕緣層241以形成用以劃定源極接觸孔150的初步接觸孔(preliminary contact hole)149。此外,預定光罩圖案(mask pattern)50接著形成於合成結構上以便使初步接觸孔149曝露出來。並且,將利用光罩圖案50作為蝕刻光罩來圖案化第一上層間絕緣層241及下層間絕緣層140。並且,在雙鑲嵌製程期間使用第二絕緣層241b作為蝕刻終止層,而其用以轉移初步接觸孔149所劃定的接觸孔結構至下層140及240。因此,第二絕緣層241b可能由相對於第一及第三絕緣層241a及241c具有蝕刻選擇性的材料所構成。例如,第二絕緣層241b可能由氮化矽所構成。

參照圖3C,第二上層間絕緣層242形成於包括源極插塞300的合成結構上。尤其,第二上層間絕緣層242連同第一上層間絕緣層241構成上層間絕緣層240。隨後,將圖案化上及下層間絕緣層240及140以形成穿過汲極通孔501且使下汲極區110D曝露出來的汲極接觸孔151。在此例中,汲極接觸孔151形成於上半導體層200的上方使得其寬度大於汲極通孔501的寬度,以便使上汲極區210D的頂面曝露出來。並且,將形成上蝕刻終止層230以避免在形成汲極接觸孔151時造成上半導體層200(例如,特別是上汲極區210D)的蝕刻損害。亦即,汲極接觸孔151的形成包括利用相對於上蝕刻終止層230具有蝕刻選擇性的蝕刻配方來蝕刻上層間絕緣層240及下層間絕緣層140。此外,所形成的上蝕刻終止層230最好是比下蝕刻終止層130厚,以避免在下蝕刻終止層130的蝕刻期間損害上半導體層200的頂面。

參照圖3D,將形成位元線插塞400以充填汲極接觸孔151。隨後,與位元線插塞400接觸且跨越字元線WL的位元線BL形成於上層間絕緣層240上。在一較佳實施例中,汲極絕緣層(見圖2B的參考數字155)可能形成於汲極接觸孔151的側壁上。同樣地,在形成源極插塞300之前,源極絕緣層(見圖2B的156)可能形成於源極接觸孔150的側壁上。汲極及源極絕緣層155及156可能利用典型的間隙壁形成製程來形成。

上述方法可能用以製造任何半導體裝置。在一較佳實施例中,將形成上半導體層使得其在下半導體層的下源極及汲極區的上方具有通孔,其中此通孔穿過上半導體層。並且,將形成源極及位元線插塞使得其通過通孔。因此,能夠電性連接三維排列記憶胞的源極及汲極電極而不致損及晶片面積有效性。

以上揭露的主要內容應視為用以說明而非限定本發明,因此後附之申請專利範圍將包含所有此種符合本發明的精神及範疇的修改、加強以及其他實施例。因此,為了最大化法律所賦與的權利保護範圍,本發明的範圍將取決於下列申請專利範圍及其等效的最廣可允許解釋,而非限定或侷限於前面的詳細說明。

50...預定光罩圖案

88...種晶孔

99...種晶插塞

100...下半導體層

105...下閘極絕緣層

110...下雜質區

110D...下汲極區

110S...下源極區

120...下閘極結構

121...下浮動電極

122...下閘極層間絕緣層

123...下控制電極

124...下覆蓋圖案

129...閘極間隙壁

130...下蝕刻終止層

140...下層間絕緣層

149...初步接觸孔

150...源極接觸孔

151...汲極接觸孔

155...汲極絕緣層

156...源極絕緣層

195...鑄模圖案

198...半導體層

199...磊晶半導體層

199’...薄半導體層

200...上半導體層

205...上閘極絕緣層

210...上雜質區

210D...上汲極區

210S...上源極區

220...上閘極結構

221...上浮動電極

222...上閘極層間絕緣層

223...上控制電極

224...上覆蓋圖案

229...閘極間隙壁

230...上蝕刻終止層

240...上層間絕緣層

241...第一上層間絕緣層

241a...第一絕緣層

241b...第二絕緣層

241c...第三絕緣層

242...第二上層間絕緣層

300...源極插塞

301...下源極插塞

302...上源極插塞

400...位元線插塞

401...下位元線插塞

402...上位元線插塞

501...汲極通孔

502...源極通孔

BL...位元線

CSL...共同源極線

G1...汲極通孔501的寬度

G2...源極通孔502的寬度

GSL...接地選擇線

SSL...字串選擇線

WF...晶圓

WL...字元線

包含附圖是為了提供對本發明的進一步理解,其併入且構成本說明書的一部分。附圖繪示本發明的較佳實施例,並且連同其說明用以解釋本說明書的原理。在圖中:圖1A至1D是根據較佳實施例之NAND快閃記憶體裝置的記憶胞陣列的平面圖。

圖2A至2C是根據較佳實施例之NAND快閃記憶體裝置的記憶胞陣列的斷面圖。

圖3A至3D是根據一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。

圖4A至4C是根據另一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。

圖5A及5B是根據又另一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。

圖6A至6C是根據又另一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。

圖7A及7B是根據又另一較佳實施例之NAND快閃記憶體裝置的製造方法的斷面圖。

100...下半導體層

105...下閘極絕緣層

110...下雜質區

110D...下汲極區

110S...下源極區

120...下閘極結構

121...下浮動電極

122...下閘極層間絕緣層

123...下控制電極

124...下覆蓋圖案

129...閘極間隙壁

130...下蝕刻終止層

140...下層間絕緣層

200...上半導體層

205...上閘極絕緣層

210...上雜質區

210D...上汲極區

210S...上源極區

220...上閘極結構

221...上浮動電極

222...上閘極層間絕緣層

223...上控制電極

224...上覆蓋圖案

230...上蝕刻終止層

240...上層間絕緣層

241...第一上層間絕緣層

242...第二上層間絕緣層

300...源極插塞

400...位元線插塞

501...汲極通孔

502...源極通孔

BL...位元線

GSL...接地選擇線

SSL...字串選擇線

WL...字元線

Claims (26)

  1. 一種NAND快閃記憶體裝置,包括:下半導體層及上半導體層,所述上半導體層位於所述下半導體層的上方;第一汲極區及第一源極區,位於所述下半導體層中;第二汲極區及第二源極區,位於所述上半導體層中;第一閘極結構,位於所述下半導體層上;第二閘極結構,位於所述上半導體層上;位元線,位於所述上半導體層的上方;以及至少一個位元線插塞,連接在所述位元線與所述第一汲極區之間,其中所述至少一個位元線插塞經由位於所述上半導體層中的汲極通孔延伸,其中每一個所述閘極結構包括:與所述第一或第二汲極區相鄰的字串選擇線;與所述第一或第二源極區相鄰的接地選擇線;以及多條位於所述字串選擇線與所述接地選擇線之間的字元線,其中所述位元線以跨越所述字元線的方向延伸。
  2. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,其中所述上半導體層中的所述第二汲極區與所述汲極通孔相鄰。
  3. 如申請專利範圍第2項所述之NAND快閃記憶體裝置,其中所述至少一個位元線插塞包括:上位元線插塞,位於所述上半導體層的上方,並且連接到與所述汲極通孔相鄰的所述上半導體層的所述第二汲 極區,其中所述上位元線插塞的寬度大於所述汲極通孔的寬度;以及下位元線插塞,其由所述上位元線插塞延伸且通過所述汲極通孔,並連接到所述下半導體層的所述第一汲極區。
  4. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,其中所述至少一個位元線插塞包括:上位元線插塞,在所述位元線與所述上半導體層的所述第二汲極區之間延伸;以及下位元線插塞,在所述位元線與所述下半導體層的所述第一汲極區之間延伸,其中所述下位元線插塞通過所述汲極通孔且與所述上位元線插塞分離。
  5. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,其中所述至少一個位元線插塞由包含鎢、鈦、鉭、氮化鈦、氮化鉭、氮化鎢、以及多晶矽的群組中選出的至少一種材料所構成。
  6. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,更包括汲極絕緣層,位於所述汲極通孔的內壁上且其所述至少一個位元線插塞與所述上半導體層的側壁隔離。
  7. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,更包括上蝕刻終止層,位於所述上半導體層的上方且覆蓋所述第二閘極結構。
  8. 如申請專利範圍第7項所述之NAND快閃記憶體裝置,更包括下蝕刻終止層,位於所述下半導體層的上方且 覆蓋所述第一閘極結構,其中所述上蝕刻終止層比所述下蝕刻終止層厚。
  9. 如申請專利範圍第1項所述之NAND快閃記憶體裝置,更包括:共同源極線,位於所述位元線的下方且與所述第一及第二閘極結構的所述接地選擇線互相平行地延伸;以及至少一個源極插塞,電性連接所述共同源極線與所述下及上半導體層各自的所述第一及第二源極區。
  10. 如申請專利範圍第9項所述之NAND快閃記憶體裝置,其中所述上半導體層更包括源極通孔,位於所述下半導體層的所述第一源極區的上方,並且其中所述至少一個源極插塞通過所述源極通孔。
  11. 如申請專利範圍第10項所述之NAND快閃記憶體裝置,其中所述上半導體層的所述第二源極區與所述源極通孔相鄰。
  12. 如申請專利範圍第11項所述之NAND快閃記憶體裝置,其中所述至少一個源極插塞包括:上源極插塞,位於所述上半導體層的上方,且連接到與所述源極通孔相鄰的所述上半導體層的所述第二源極區,其中所述上源極插塞的寬度大於所述源極通孔的寬度;以及下源極插塞,由所述上源極插塞延伸且通過所述源極通孔,並連接到所述下半導體層的所述第一源極區。
  13. 如申請專利範圍第10項所述之NAND快閃記憶體 裝置,其中所述源極插塞包括:上源極插塞,在所述共同源極線與所述上半導體層的所述第二源極區之間延伸;以及下源極插塞,在所述共同源極線與所述下半導體層的所述第一源極區之間延伸,其中所述下源極插塞通過所述源極通孔且與所述上源極插塞分離。
  14. 如申請專利範圍第9項所述之NAND快閃記憶體裝置,其中所述至少一個源極插塞由包含鎢、鈦、鉭、氮化鈦、氮化鉭、氮化鎢、以及多晶矽的群組中選出的至少一種材料所構成。
  15. 如申請專利範圍第9項所述之NAND快閃記憶體裝置,更包括源極絕緣層,位於所述源極通孔的內壁上且將所述至少一個源極插塞與所述上半導體層的側壁隔離。
  16. 一種NAND快閃記憶體裝置的製造方法,包括:在下半導體層中形成下源極區及下汲極區;在所述下半導體層的上方形成上半導體層,所述上半導體層包括汲極通孔、源極通孔、上源極區、以及上汲極區;形成至少一個位元線插塞,經由所述汲極通孔延伸且連接到所述上及下汲極區;以及形成至少一個源極插塞,經由所述源極通孔延伸且連接到所述上及下源極區。
  17. 如申請專利範圍第16項所述之NAND快閃記憶體裝置的製造方法,其中所述上半導體層的形成包括:藉由利用所述下半導體層作為晶種層來執行磊晶製程以形成磊晶矽層於所述下半導體層上;平面化所述磊晶矽層以形成所述上半導體層;以及圖案化所述上半導體層以形成穿過所述上半導體層的所述源極通孔與汲極通孔,其中所述源極通孔與汲極通孔分別排列在所述下源極區及汲極區的上方。
  18. 如申請專利範圍第16項所述之NAND快閃記憶體裝置的製造方法,其中所述上半導體層的形成包括:形成下層間絕緣層於包括所述下半導體層的結構上;接合晶圓與所述下層間絕緣層;蝕刻所述晶圓以形成半導體層;圖案化所述半導體層以形成所述上半導體層;以及圖案化所述上半導體層以形成穿過所述上半導體層的所述源極通孔與所述汲極通孔,其中所述源極通孔與汲極通孔分別排列在所述下源極區及汲極區的上方。
  19. 如申請專利範圍第16項所述之NAND快閃記憶體裝置的製造方法,其中所述上半導體層的形成包括:形成下層間絕緣層於包括所述下半導體層的結構上;形成鑄模圖案於所述下層間絕緣層上;沈積半導體層於包括所述鑄模圖案的結構上;以及平面化所述半導體層直到曝露出使所述鑄模圖案為 止以形成所述上半導體層,其中所述鑄模圖案位於所述源極與汲極通孔的位置。
  20. 如申請專利範圍第19項所述之NAND快閃記憶體裝置的製造方法,更包括在沈積所述半導體層之後結晶化所述半導體層。
  21. 如申請專利範圍第16項所述之NAND快閃記憶體裝置的製造方法,更包括:形成下閘極結構於所述下半導體層上,其中所述下閘極結構包括:與所述下汲極區相鄰的字串選擇線;與所述下源極區相鄰的接地選擇線;以及多條位於所述字串選擇線與所述接地選擇線之間的字元線;形成上閘極結構於所述上半導體層上,其中所述上閘極結構包括:與所述上汲極區相鄰的字串選擇線;與所述上源極區相鄰的接地選擇線;以及多條位於所述字串選擇線與所述接地選擇線之間的字元線;以及形成位元線,跨越所述字元線且連接到所述至少一個位元線插塞。
  22. 如申請專利範圍第16項所述之NAND快閃記憶體裝置的製造方法,更包括:形成介於所述下半導體層與所述上半導體層之間的下層間絕緣層;形成位於所述上半導體層上的上層間絕緣層;圖案化所述上及下層間絕緣層以形成曝露出所述下及上源極區的源極接觸孔;以及 圖案化所述上及下層間絕緣層以形成曝露出所述下及上汲極區的位元線接觸孔。
  23. 如申請專利範圍第22項所述之NAND快閃記憶體裝置的製造方法,其中所述上層間絕緣層包括覆蓋所述上源極區及所述上汲極區的上蝕刻終止層。
  24. 如申請專利範圍第23項所述之NAND快閃記憶體裝置的製造方法,其中所述下層間絕緣層包括覆蓋所述下源極區及所述下汲極區的下蝕刻終止層,所述上蝕刻終止層所形成的厚度比所述下蝕刻終止層厚。
  25. 如申請專利範圍第22項所述之NAND快閃記憶體裝置的製造方法,更包括:在形成所述至少一個源極插塞之前,形成源極絕緣層於所述源極通孔的側壁上,其中所述源極絕緣層將所述至少一個源極插塞與所述源極通孔的側壁隔離;以及在形成所述至少一個位元線插塞之前,形成汲極絕緣層於所述汲極通孔的側壁上,其中所述汲極絕緣層將所述至少一個位元線插塞與所述汲極通孔的側壁隔離。
  26. 如申請專利範圍第22項所述之NAND快閃記憶體裝置的製造方法,其中利用雙鑲嵌製程來形成所述源極接觸孔及所述源極插塞。
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