TWI411083B - 半導體封裝元件及其製造方法 - Google Patents

半導體封裝元件及其製造方法 Download PDF

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TWI411083B
TWI411083B TW099121566A TW99121566A TWI411083B TW I411083 B TWI411083 B TW I411083B TW 099121566 A TW099121566 A TW 099121566A TW 99121566 A TW99121566 A TW 99121566A TW I411083 B TWI411083 B TW I411083B
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conductive layer
semiconductor package
layer
insulating layer
package component
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TW099121566A
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TW201042744A (en
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Hwee-Seng Jimmy Chew
Chee Kian Ong
Razak Bin Chichik Abd
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Advanpack Solutions Pte Ltd
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Description

半導體封裝元件及其製造方法
本發明是有關於一種半導體封裝元件及其製造方法，尤關於一種在製造過程中，可單獨分離運輸的導線架。
隨著科技發展，各種電子產品需求量大增，而對於電子產品的小型化，也是消費者所期望，而應用於電子產品中的半導體元件，通常是關鍵的元件，因此半導體元件的需求，也走向小型化之設計，因此縮小半導體元件的線路間距(Pitch)與線寬，一直是產業努力的目標。而半導體元件的小型化，並不限於半導體晶片內部本身的線路間距問題，承負著晶片訊號向外延伸的晶片封裝，也扮演相當重要的角色。若是，半導體封裝元件的線路間距，不能有效縮小，則晶片經此封裝後，實際應用的半導體元件體積小型化的程度即相當有限。
舉例而言，傳統封裝的金屬導線厚度，約為120~250微米(micrometer)，要經過微影、曝光與蝕刻，才會形成封裝導線(Package trace)。然而，因會蝕刻線距限制，以及下切(undercutting)效果，會影響封裝導線的可靠度。因此，傳統的導線架(lead frame)封裝導線，並不太適合半導體元件小型化的需求。
因此，如何解決上述元件小型化問題，以及簡化封裝製程，實為目前半導體封裝元件研發之一重要方向。
依據本發明一實施例之一觀點，在於提供一種半導體封裝元件，包括一第一絕緣層，設有複數個孔洞於該第一絕緣層之第一表面上，以及複數個封裝導線，嵌設於該絕緣層中，與該等孔洞的另一端連接。
依據本發明另一實施例之一觀點，在於提供一種半導體封裝元件，包括一第一絕緣層，且該絕緣材料具有彈性模量大於1.0GPa的特性；以及複數個定位單元，以該第一絕緣層為材料，設於該第一絕緣層上；並且包括複數個封裝導線，設於該等定位單元之下方。
依據本發明再一實施例之一觀點，在於提供一種半導體封裝元件製造方法，包括以下步驟：提供一載體，並形成複數個導線在該載體上，再形成一第一絕緣層於該複數個導線上，而後形成複數個定位單元於該第一絕緣層之第一表面上，且該等定位單元與該等導線直接接觸。
依據本發明再一實施例之一觀點，提出一種半導體封裝元件製造方法，包括以下步驟：提供一載體；形成一由第一導電層構成之數個電性絕緣的封裝導線佈局單元；而封裝導線佈局單元，則係由數個電性絕緣的封裝導線所組成；形成一圖案化之第二導電層於第一導電層上；形成一由塑模材料構成之第一絕緣層，嵌封第一導電層與該第二導電層；選擇性移除部分之載體。
為讓上述本發明之特點以及可能的優點更為清晰，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
 第一實施例
請參第1圖及以下，其為本發明第一實施例半導體封裝元件的製造方法。首先提供一載體10，在本實施例中，為一鋼片(Steel)。然後，參第2圖，在載體10上方，形成光阻層11，再成型為圖樣化光阻層11’如第3圖所示。
請參第4圖，在光阻層11’空白部份，形成導電層20，其厚度一般為0.01~0.4 mm，較佳為0.025~0.035mm。而在本實施例中，形成導電層20的方法，係為電鍍法。除去光阻層11’，如第5圖所示，留下導電層20(第一導電層)，係作為封裝導線使用，並非半導體晶片內的導線，而在本實施例中，導電層20形成之複數個封裝導線，較佳者係為電性分離的，以作為封裝導線佈局單元(package trace layout unit)，但實際上，也可以是電性連接的。而成型時，係同時形成複數個封裝導線佈局單元(unit)，而各個封裝導線佈局單元，為實質相同的圖樣，主要個別對應一個待封裝之晶片。
請參第6圖，提供一模具23，該模具23上設有多個突點，對應於該導線層20的位置。而後注入絕緣材料，形成第一絕緣層21，其厚度一般為0.1~0.4 mm，較佳為0.18~0.22 mm。並使複數個封裝導線(package trace)，嵌設於該第一絕緣層21中，如第7圖所示，或是設於該第一絕緣層21中，並使其延伸至該第一絕緣層之一表面。在本實施例中，絕緣材料係為塑模材料(molding material)，且此絕緣材料具有彈性模量大於1.0GPa的特性，且較佳者，其CTE值，小於10 ppm/℃，在本實施例中，係為epoxy resin。實際上，此第一絕緣層21，不見得限定於一層。對於習於此項技藝人士而言，亦可用幾種材料，分次形成，組成一複合的絕緣層，或是使用同一材料，分次成形，構成一絕緣層。但這些變化，仍屬於在本發明之保護範圍內。但在本實施例中，係以一種單一材料，塑成第一絕緣層21，以使封裝導線(package trace)，嵌設於該第一絕緣層21中。亦即，第一絕緣層21的高度，要高於封裝導線的高度。
由於模具23上對應於該導線層20位置的突點，使得第一絕緣層21的表面上，上形成複數的孔洞22。而後，移去模具23以及載體10，請參第8圖，形成一可獨立運送的半導體封裝元件。由本圖可見，在本實施例中，孔洞22的另一端，與該導線層20的封裝導線直接接觸，該等孔洞，係作為後續連接導體單元之定位單元，並以該導線層20為材料設置而成。
請參第9圖，如第8圖製妥之一獨立半導體封裝元件，以一第二導體單元，連接至晶片31。在本實施例中，係以焊料33(solder)、柱狀凸塊32(Pillar bump)連接至晶片31。此外，如第10圖所示，亦可在孔洞22中，全部填入或部份填入導體材料，作為第二導電層41，例如鎳、金、銅或焊料，在本實施例中，係為焊料41，以供後續進一步加工。
請參第11圖，導體單元42(在本實施例中，係為焊球(solder ball)，也可以是其他形式的導線)，可經由孔洞22的定位，固定於該獨立半導體封裝元件上，使得晶片31訊號，經由柱狀凸塊32(Pillar bump)、焊料33(solder)、導線層20、導體單元42向外傳輸。而定位單元(在本實施例中為孔洞22，但此孔洞不一定要穿透，也可說是凹洞)，可避免焊球之焊料，因為加熱而四處竄流，而被限定於該孔洞22之中。
而焊料41的設置，可使導體單元42與導線層20的電性連結更為緊密，避免導體單元42在使用焊球時，無法完全填滿孔洞22，產生氣泡。
另一方面，獨立半導體封裝元件與晶片31的封裝，可以有彈性。請參第12圖，晶片31，可以填入絕緣材料，例如封裝材料(encapsulating material)，作為第二絕緣層51，封住柱狀凸塊32(Pillar bump)以下而露出晶片31；或是，如第13圖所示，第二絕緣層52封住柱狀凸塊32與晶片31，但露出晶面上表面；或者，如第14圖所示，只剛好封住柱狀凸塊32而與晶片31切齊。
此外，此一半導體封裝元件，亦可用於多晶片封裝。請參第15圖，在第一絕緣層的孔洞以外，另外設有可供晶片61固定連接至導線的空間72，而以孔洞22’另外與焊球連結。
請參第16圖，其為本發明一第一實施例導線架的示意圖。其亦即第8圖所示元件的下視圖。其中可見，第一導電層所形成之封裝導線佈局單元(package trace layout unit)80，嵌設於第一絕緣層21之中，其中還包括複數個定位孔(fiducial mark)90，作為導線架用於晶片封裝時的定位對齊之用。而本實施例之個別的封裝導線佈局單元80的形狀，請參第17圖。其中一個封裝導線佈局單元80中，包括複數個複數個電性絕緣的封裝導線，構成一封裝導線佈局單元的圖樣，以對應一個待封裝之晶片。其可能是較小的晶片，以導電點84與晶片作電連結；，或是較大的晶片，以導電點74與晶片作電連結。是以，本實施例，可作為不同大小晶片的導線架之用。再由第16圖與第17圖可見，這些複數個封裝導線佈局單元(unit)80，為實質相同的圖樣，且這些複數個封裝導線佈局單元(unit)80之間，以絕緣且重覆的形式，係排列成矩陣狀，嵌設於第一絕緣層21之中。
而各個封裝導線佈局單元(unit)80的圖樣，較佳者為Fan-in或Fan-out圖樣。且第一導電層20與第二導電層41，可設有不同的線寬(pitch)，以達到Fine Pitch功能。
第二實施例
請參第18圖及以下，其為本發明第二實施例半導體封裝元件的製造方法。首先提供一載體19，在本實施例中，為一銅片(Copper)。其他製法，同第一實施例第1圖至第4圖所示，而得出第18圖的階段性結果，在載體19上形成圖樣化的第一導電層20’。
請參第19圖，在第一導電層20’上方，上一層光阻層25，並且圖案化該光阻層25，留出孔洞27’。請參第20圖，在孔洞27’中，形成第二導電層27，在本實施例中，係以電鍍的方式成型，其為實質平坦狀，並未凸出該第一絕緣層28表面。
移除光阻層25，得到圖樣化之第一導電層20’以及第二導電層27，如第21圖所示。請參第22圖，以模具填入塑模材料(molding material)形成第一絕緣層28，以將圖樣化之第一導電層20’以及第二導電層27嵌入於第一絕緣層28之中。此第一絕緣層28所使用的塑模材料，在本實施例為epoxy resin，並且具有彈性模量大於1.0GPa的特性，且其CTE值小於10 ppm/℃的特性。
以蝕刻方式，移除載體19，得到封裝前之半導體封裝元件，如第23圖所示。此封裝前之半導體封裝元件應用，請參第24圖，其可以焊料33’、導電凸塊32’(Pillar bump)連接至晶片31’。
此外，其中該第二導電層27，可經預處理(pre-treatment)，可解決QFN封裝，會因為移除tape，而產生的resin residue問題。
請參第25圖，第一導電層20’封裝導線佈局上，亦可設有導電凸點39，可為銀、金、其他金屬或其他導電材料，並設使對應該導電凸點的封裝導線佈局垂直上方，係為第一絕緣層28的塑模材料。如此，封裝前之半導體封裝元件，應用於傳統Wiring Bond時，導線可連接至此導電凸點39，可使導線架儘可能接近封裝晶片，並在連接導線時，不會搖晃，讓製作wire連結到晶片的效能，大為提高。
第三實施例
請參照第26～36圖，其繪示依照本發明第三實施例之半導體封裝元件之製造方法的流程圖。首先，提供一載體19’。在本實施例中，載體19’為一銅片(Copper)。其他製法，同第一實施例第1圖至第4圖所示，而得出第26圖的階段性結果，在載體19’上形成圖樣化的第一導電層20’。
請參第27圖，在第一導電層20’上方，上一層光阻層25，並且圖案化該光阻層25，留出孔洞27’。請參第28圖，在孔洞27’中，形成第二導電層27，在本實施例中，第二導電層27係以電鍍的方式成型，其為實質平坦狀，並未凸出該第一絕緣層28表面。
移除光阻層25，得到圖樣化之第一導電層20’以及第二導電層27，如第29圖所示。請參第30圖，以模具填入塑模材料(molding material)形成第一絕緣層28，以將圖樣化之第一導電層20’以及第二導電層27嵌入於第一絕緣層28之中。此第一絕緣層28所使用的塑模材料，在本實施例為epoxy resin，並且具有彈性模量大於1.0GPa的特性，且其CTE值小於10 ppm/℃的特性。
以蝕刻方式，移除載體19’，得到封裝前之半導體封裝元件，如第31～35圖所示。
請參照第31圖，一光阻層81係形成於載體19’上。然後，光阻層81透過一光罩82進行曝光。光罩82具有至少一第一開口82a及至少一第二開口82b，如第32圖所示。接著，獲得已圖案化之光阻層81，此以圖案化光阻層81具有至少一第一開口81a及至少一第二開口81b，如第33圖所示。其中第一開口81a及第一開口82a係對應於第一絕緣層28之內側區域，第二開口81b及第二開口82b係對應於第一絕緣層28之外側區域。
然後，請參照第34圖，以已圖案化之光阻層81為遮罩蝕刻載體19’。其中，載體19’及部分之第一導電層20’同時被蝕刻，使得第一導電層20’之表面20’a及第一絕緣層28之表面28a位於不同表面。接著，移除已圖案化之光阻層81，以形成一支撐環19’c及至少一定位孔19’b於載體19’上，如第35圖所示。
請參照第36圖。在部分之載體19’被選擇性移除後，支撐環19’c係形成於載體19’之周邊區域，且定位孔19’b係形成於支撐環19’c內。半導體封裝元件係可透過支撐環19’c及定位孔19’b進行運送，而不會接觸第一絕緣層28或第二導電層27。因此，可避免對於半導體封裝元件的機械性損害。
由以上的實施例可知，導電層20或20’(封裝導線)係以製程直接成形，不需要對導電層進行微影、曝光與蝕刻，因此導電層不會受到蝕刻線距的限制，以及下切(undercutting)的影響封裝導線的可靠度。因而封裝導線，可以比較適合半導體元件小型化的需求。
而且，封裝導線佈局單元(package trace layout unit)設有Fan-in或Fan-out圖樣的設置，而可達到Fine pitch功效。
再則，由於孔洞22(定位單元)的設置，可以使焊球的連結至封裝元件的定位較為精確，避免焊料因加熱竄流。
此外，由於使用模具23，以及孔洞22(定位單元)的設置，係直接以第一絕緣層21的材料設成，使得填充一次塑模材料，即得形成第一絕緣層21以及形成定位單元，可以大幅簡化半導體封裝元件之製程。
又且，由第11圖可見，由於封裝導線20的設置，使得焊球(solder ball)間的間距，可以大於晶片凸塊32(Pillar bump)間的間距，而可便於利用對線寬要求較低的製程加工或製造。
此外，由於第一絕緣層21，使用塑模材料molding material作為各個封裝導線圖樣(package trace pattern)的載具。是以，各個封裝導線圖樣(package trace pattern)之間，並無金屬導線連結，這與傳統導線架(lead frame)在封裝導線圖樣間，必須有連結導線相連不同，而導線架中導線間的絕緣層，只是單純用於絕緣，並不能作為載具。因此，依據本發明之實施例，因無連結導線架圖樣的連結導線，各個封裝單體圖樣，因此更容易切割。
再則，晶片連結至封裝導線後，相較於過去晶片，因為封裝導線間仍有金屬導線連結，因此，必須切割後才能個別測試。而依上述實施例，由於各個封裝導線圖樣係為電性區隔，並無金屬導線連結，所以晶片連結至封裝導線後，可作批次測試。可大幅減少測試成本與時間。綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。如前所述，第一絕緣層21，不見得限定於一層。對於習於此項技藝人士而言，亦可用幾種材料，分次形成，組成一複合的絕緣層，或是使用同一材料，分次成形，構成一絕緣層。但這些變化，仍屬於在本發明之保護範圍內。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．載體
11．．．光阻
11’．．．圖樣化光阻層
19、19’．．．載體
19’b．．．定位孔
19’c．．．支撐環
20．．．導電層
20’．．．第一導電層
20’a．．．第一導電層之表面
21．．．第一絕緣層
22,22’．．．孔洞
23．．．模具
25．．．光阻層
27．．．第二導電層
27’．．．孔洞
28．．．第一絕緣層
28a．．．第一絕緣層之表面
31、31’．．．晶片
32．．．柱狀突塊
32’．．．導電凸塊
33、33’‧‧‧焊料
39‧‧‧導電凸點
41‧‧‧第二導電層
42‧‧‧導體單元
51,52,53‧‧‧第二絕緣層
61‧‧‧晶片
72‧‧‧晶片固定連接至導線的空間
74‧‧‧導電點
80‧‧‧封裝導線佈局單元
81‧‧‧光阻層
81a‧‧‧第一開口
81b‧‧‧第二開口
82‧‧‧光罩
82a‧‧‧第一開口
82b‧‧‧第二開口
84‧‧‧導電點
90‧‧‧定位孔
第1圖至第8圖，為本發明第一實施例，製作一獨立半導體封裝元件之製作流程說明圖。
第9圖至第14圖，為本發明第一實施例，製作一獨立半導體封裝元件，連結至晶片的進一步說明圖，並包括三種不同的晶片封裝說明例。
第15圖，為本發明第一實施例，應用於多晶片封裝的說明例。
第16圖至第17圖，為本發明封裝元件實施例，未封裝前的進一步細部說明圖。
第18圖至第25圖，為為本發明第二實施例，製作一獨立半導體封裝元件的說明圖。
第26～36圖繪示依照本發明第三實施例之半導體封裝元件之製造方法的流程圖。
20．．．該導線層
21．．．第一絕緣層
22．．．孔洞

Claims (24)

  1. 一種半導體封裝元件，包括：第一導電層，具有一上表面和一下表面；第二導電層，具有一上表面和一下表面；第一絕緣層，具有一上表面和一下表面，其中該第一絕緣層由塑模材料構成，該第一導電層和該第二導電層完全嵌設於該第一絕緣層內，該第二導電層的下表面設置於部分該第一導電層的上表面上，該第二導電層的上表面暴露於該第一絕緣層的上表面；以及支撐環，設置於該第一絕緣層的下表面的周邊區域，該第一導電層的下表面暴露於該第一絕緣層的下表面的內側區域。
  2. 如申請專利範圍第1項所述之半導體封裝元件，更包括至少一金屬凸點，設置於該第一導電層的下表面上。
  3. 如申請專利範圍第1項所述之半導體封裝元件，其中該第一導電層由複數個封裝導線所組成，構成複數個封裝導線佈局單元，各該封裝導線佈局單元係設有扇入或扇出圖樣。
  4. 如申請專利範圍第3項所述之半導體封裝元件，其中該複數的封裝導線佈局單元，係為實質相同的圖樣。
  5. 如申請專利範圍第3項所述之半導體封裝元件，其中該複數的封裝導線佈局單元，係排列成矩陣狀。
  6. 如申請專利範圍第1項所述之半導體封裝元件， 其中該塑模材料係為環氧樹脂。
  7. 如申請專利範圍第1項所述之半導體封裝元件，其中該第一導電層的下表面和該第一絕緣層的下表面位於不同一平面。
  8. 如申請專利範圍第1項所述之半導體封裝元件，其中該支撐環更包括至少一定位孔對應於第一絕緣層的外側區域。
  9. 如申請專利範圍第1項所述之半導體封裝元件，更包括至少一半導體晶片，經由至少一導電結構連接至第一導電層上。
  10. 如申請專利範圍第9項所述之半導體封裝元件，更包括第二絕緣層，包封住該半導體晶片、該導電結構及第一絕緣層的下表面。
  11. 一種半導體封裝元件的製造方法，包括以下步驟：提供一載體；形成具有一上表面和一下表面的第一導電層；形成具有一上表面和一下表面的第二導電層，該第二導電層的下表面設置於部分該第一導電層的上表面上；形成具有一上表面和一下表面的第一絕緣層，其中該第一絕緣層由塑模材料構成，該第一導電層和該第二導電層完全嵌設於該第一絕緣層內，該第二導電層的上表面暴露於第一絕緣層的上表面；以及選擇性移除部分該載體，形成一支撐環於該第一絕緣 層的下表面的周邊區域，該第一導電層的下表面暴露於該第一絕緣層的下表面的內側區域。
  12. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，更包括形成至少一金屬凸點於部分該第一導電層的下表面上。
  13. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，其中該第一導電層由複數個封裝導線所組成，構成多個封裝導線佈局單元，各該封裝導線佈局單元係設有扇入或扇出圖案。
  14. 如申請專利範圍第13項所述之半導體封裝元件的製造方法，其中該多個封裝導線佈局單元係為實質相同的圖案。
  15. 如申請專利範圍第13項所述之半導體封裝元件的製造方法，其中該複數的封裝導線佈局單元係排列成矩陣狀。
  16. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，其中該塑模材料係為環氧樹脂。
  17. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，其中所述形成該第一導電層的步驟包括：在該載體上形成一第一光致抗蝕劑層；圖案化該第一光致抗蝕劑層；以及使用圖案化的該第一光致抗蝕劑層作為掩模，電鍍該第一導電層。
  18. 如申請專利範圍第17項所述之半導體封裝元件 的製造方法，其中所述形成該第二導電層的步驟包括：在該載體和該第一導電層上形成一第二光致抗蝕劑層；圖案化該第二光致抗蝕劑層；以及使用圖案化的該第二光致抗蝕劑層作為掩模，電鍍該第二導電層。
  19. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，其中所述選擇性移除部分該載體的步驟包括：在該載體上形成一第三光致抗蝕劑層；圖案化該第三光致抗蝕劑層；使用圖案化的該第三光致抗蝕劑層作為掩模，蝕刻該載體；以及移除圖案化的該第三光致抗蝕劑層。
  20. 如申請專利範圍第19項所述之半導體封裝元件的製造方法，其中蝕刻該載體之該步驟更包括：同時蝕刻部分之該第一導電層，使該第一導電層之下表面與該第一絕緣層之表面位於不同一平面。
  21. 如申請專利範圍第19項所述之半導體封裝元件的製造方法，其中所述圖案化該第三光致抗蝕劑層的步驟更包括：同時形成至少一第一開口及一第二開口，該第一開口對應於該第一絕緣層的內側區域，該第二開口對應於該第一絕緣層的外側區域。
  22. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，其中所述形成該支撐環的步驟更包括：形成至少一定位孔於該支撐環，該至少一定位孔對應於該第一絕緣層的外側區域。
  23. 如申請專利範圍第11項所述之半導體封裝元件的製造方法，更包括設置至少一半導體晶片，經由至少一導電結構連接至第一導電層上。
  24. 如申請專利範圍第23項所述之半導體封裝元件的製造方法，更包括形成第二絕緣層，包封住該半導體晶片、該導電結構及第一絕緣層的下表面。
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US20080145967A1 (en) 2008-06-19
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US20090102043A1 (en) 2009-04-23
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US9396982B2 (en) 2016-07-19
TWI364101B (en) 2012-05-11
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US20100264526A1 (en) 2010-10-21
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