TWI396275B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI396275B
TWI396275B TW097111232A TW97111232A TWI396275B TW I396275 B TWI396275 B TW I396275B TW 097111232 A TW097111232 A TW 097111232A TW 97111232 A TW97111232 A TW 97111232A TW I396275 B TWI396275 B TW I396275B
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TW
Taiwan
Prior art keywords
semiconductor substrate
semiconductor
capacitor
semiconductor device
insulating film
Prior art date
Application number
TW097111232A
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English (en)
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TW200843086A (en
Inventor
Katsu Horikoshi
Hisayoshi Uchiyama
Takashi Noma
Yoshinori Seki
Hiroshi Yamada
Shinzo Ishibe
Hiroyuki Shinogi
Original Assignee
Sanyo Electric Co
Sanyo Semiconductor Co Ltd
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Application filed by Sanyo Electric Co, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co
Publication of TW200843086A publication Critical patent/TW200843086A/zh
Application granted granted Critical
Publication of TWI396275B publication Critical patent/TWI396275B/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置
本發明係有關一種具備有電容元件的半導體裝置。
從降低因電磁雜訊所造成的電壓位準變動之影響，以防止半導體晶片的誤動作之觀點，以往係於該半導體晶片的端子(電源端子或接地端子)設置有稱為旁路電容(bypass capacitor)的電容元件。
例如，在以下的專利文獻1中，已揭示有一種將半導體晶片以及稱為晶片電容之外裝的電容元件安裝在同一個基板上，而將整體封裝成一個晶片狀之半導體裝置。
此外，在以下的專利文獻2中，已揭示有一種利用半導體基板上的多層配線層以及多層配線層之間的層間絕緣膜來形成具有旁路電容功能的電容元件之半導體裝置。
與本發明有關連的技術係記載於例如以下的專利文獻。
專利文獻1：日本特開平05－021698號公報 專利文獻2：日本特開2000－349238號公報
然而，如同上述專利文獻1，在使用外裝的電容元件之構成中，雖能獲得具有大靜電電容的電容元件，但必須在基板上具有用以安裝該電容元件的空間。因此，有難以謀求裝置整體的小型化之問題。
此外，由於近年來半導體晶片動作的高速化，有因為電晶體的高速切換(switching)動作而增加高頻(數百MHz以上的頻率)的電磁雜訊，使動作特性劣化的傾向。因此，期望一種能有效地去除電磁雜訊之技術。
作為謀求降低電磁雜訊影響的方法之一，可列舉使半導體晶片與電容元件儘量接近，以謀求連接半導體晶片與電容元件之配線(電源配線或接地配線)的低阻抗化及低電感化之方法。然而，由於該等配線在佈局設計上有時亦會被拉長，因此，當半導體晶片與電容元件為個體的零件時，兩者的接近程度還是有限。
如同上述說明，在具備有外掛的電容元件之構成中，有難以同時實現半導體裝置的小型化與進一步降低電磁雜訊的影響之問題。
另一方面，如同上述專利文獻2，在同一個半導體裝置內形成有電容元件的習知構成中，與使用外裝的電容元件之情形相比雖可謀求配線的低阻抗化與低電感化，但為了獲得能有效去除高頻的電磁雜訊程度之充分的靜電電容，仍需要大面積。
因此，由於在同一個半導體基板上形成電容元件以外的其他功能元件(例如由電晶體等所構成之驅動器電路、邏輯電路、或者連接該等電路之配線等)，故有無法謀求半導體裝置的小型化之問題。
因此，本發明的主要目的係提供一種謀求在同一個半導體裝置內具備有電容元件以將裝置整體小型化，並且具 備有靜電容量比以往還大的電容元件之半導體裝置，本發明的另一目的係提供一種能降低電磁雜訊影響的半導體裝置。
本發明乃有鑑於上述課題而研創者，主要特徵如下所述。亦即，本發明的半導體裝置係具備有：半導體基板；半導體積體電路，係形成於前述半導體基板的表面；銲墊電極(pad electrode)，係與前述半導體積體電路連接；電容電極，係與前述半導體基板的背面接觸而形成；絕緣膜，係形成於前述半導體基板的側面上與前述電容電極上；以及配線層，係與前述電容電極重疊而形成於前述絕緣膜上，且與前述銲墊電極連接；其中，由前述電容電極、前述絕緣膜、以及前述配線層來形成電容。
在本發明中，由於在半導體基板一方的面上形成半導體積體電路，並於另一方的面上形成電容，因此能實現具備有靜電電容比以往還大的電容，且為小型化的半導體裝置。
接著，參照附圖說明本發明的第一實施形態。第1圖至第9圖係分別顯示製造步驟順序的剖面圖或平面圖。以下所說明的製造步驟係使用晶圓狀的半導體基板來進行，雖以預定的切割線(dicing line)為交界將複數個半導體裝置形成矩陣狀，但為了便利，係說明形成一個半導體裝置 的步驟。
首先，如第1圖所示，準備由矽(Si)等所構成的半導體基板2，該半導體基板2的表面係形成有半導體積體電路1(例如將CCD(Charge Coupled Device；電荷耦合元件)感測器、CMOS(Complementary Metal－Oxide Semiconductor；互補式金氧半導體)感測器、照明感測器等之受光元件或發光元件、以及電晶體等半導體元件予以積體化所構成的驅動器電路或邏輯電路、以及連接該等之配線等)。半導體基板2的厚度係例如為300 μm至700 μm左右。接著，於半導體基板2的表面形成例如2 μm厚度的第一絕緣膜3(例如以熱氧化法或CVD(Chemical Vapor Deposition；化學氣相沉積)法所形成的氧化矽膜)。
接著，藉由濺鍍法、鍍覆法、或其他成膜方法形成鋁(Al)、鋁合金、或銅(Cu)等金屬層，之後，將未圖示的光阻層作為遮罩來蝕刻金屬層，於第一絕緣膜3上形成例如厚度1 μm的銲墊電極4。銲墊電極4係經由未圖示的配線而電性連接至半導體積體電路1或其周邊元件之外部連接用電極。接著，電源電壓、接地電壓、或各種信號係從後述的導電端子13a、13b、13c經由銲墊電極4供給至半導體積體電路1或半導體基板2等。此外，在第1圖中，雖然銲墊電極4配置於半導體積體電路1的兩側，但並未限定於該位置，亦可配置於半導體積體電路1上。
接著，於半導體基板2的表面形成覆蓋銲墊電極4的局部上或全部之鈍化膜5(例如藉由CVD法所形成的氮化 矽膜)。在第1圖中，以覆蓋銲墊電極4局部上的方式來形成鈍化膜5。
接著，於包含有銲墊電極4的半導體基板2的表面上經由環氧樹脂(Epoxy resin)、聚醯亞胺(Polyimide)(例如感光性聚醯亞胺)、光阻、或丙烯醛基(Acryl)等之接著層6來貼附支持體7。此外，在半導體積體電路1包含有受光元件或發光元件的情形中，由於接著層6會變成從半導體積體電路1所射出的光線或者射入至半導體積體電路1的光線的通過路徑，故較佳為由透明且透光性良好的材料所構成。
支持體7係可為例如薄膜狀的保護帶，亦可為玻璃、石英、陶瓷、或金屬等之剛性基板，亦可由樹脂所構成。支持體7係具有支持半導體基板2且保護半導體基板2的元件表面之功能。此外，在半導體積體電路1包含有受光元件或發光元件的情形中，支持體7係由透明或半透明的材料所構成，且具有透光性者。
接著，使用背面研削裝置(研磨機)對半導體基板2的背面進行背面研磨(Back grinding)，將半導體基板2的厚度削薄至預定的厚度(例如100 μm左右)。該研削步驟係可為蝕刻處理，亦可併用研磨機與蝕刻處理。此外，根據最終製品的用途或規格，以及所準備的半導體基板2最初的厚度，亦有無需進行研削步驟的情形。
接著，如第2圖所示，從半導體基板2的背面側選擇性地僅蝕刻半導體基板2中與銲墊電極4對應的預定區 域，使第一絕緣膜3局部露出。以下，將此露出部分稱為開口部8。
參照第3圖A、B來說明半導體基板2的選擇性蝕刻。第3圖A、B係從半導體基板2側所視的概略平面圖，第2圖係對應沿著第3圖A、B的A－A剖線的剖面圖。
如第3圖A所示，能將半導體基板2蝕刻成比支持體7的寬度還窄，且為大致長方形的形狀。此外，如第3圖B所示，僅蝕刻形成有銲墊電極4的區域，藉此能以形成凹凸狀的方式來構成半導體基板2的外周。後者的方式，半導體基板2與支持體7的重疊面積大，半導體基板2會存留至接近支持體7的外周。因此，從提升支持體7對於半導體基板2的支持強度之觀點來看，後者的構成為佳。此外，依據後者的構成，由於能防止半導體基板2與支持體7的熱膨脹率的差異而導致支持體7的翹曲，故能防止半導體裝置產生裂縫(crack)或剝離。此外，亦可將半導體基板2設計成與第3圖A、B所示的平面形狀不同的形狀。之後，說明如第3圖A所示蝕刻半導體基板2時的製造步驟。
此外，在本實施形態中雖以半導體基板2的橫寬度愈朝表面側愈寬的方式將半導體基板2的側壁斜向蝕刻，但亦能以半導體基板2的寬度為固定，且半導體基板2的側壁與支持體7的主面垂直之方式來進行蝕刻。
接著，如第4圖及第5圖所示，藉由CVD法、濺鍍法、或其他成膜方法，於半導體基板2的背面上形成例如 厚度約1 μm至2 μm之例如由鋁、金、或銀等金屬材料所構成的電容電極9。此外，亦可在前述半導體基板2進行背面研磨後形成電容電極9，接著，選擇性地蝕刻電容電極9與半導體基板2兩者以形成開口部8。如同後述，電容電極9係構成電容16的一方電極，且在實際使用時會被固定成與半導體基板2相同的電位(通常為接地電位)。此外，為了儘可能地獲得大靜電電容的電容元件，電容電極9的面積較廣為佳。此外，第5圖係從第4圖的半導體基板2側所視的概略平面圖，第4圖係沿著第5圖的B－B剖線之剖面圖。
接著，於包含有開口部8與電容電極9的半導體基板2的側面及背面上形成第二絕緣膜10。該第二絕緣膜10係藉由例如電漿CVD法所形成的氧化矽膜或氮化矽膜。
接著，如第6圖所示，將未圖示的光阻層作為遮罩，選擇性地蝕刻第一絕緣膜3與第二絕緣膜10。藉由該蝕刻，選擇性地去除從銲墊電極4的局部上至切割線的區域所形成之第一絕緣膜3與第二絕緣膜10，並在開口部8的底部中至少露出銲墊電極4的局部。
接著，藉由濺鍍法、鍍覆法、或其他成膜方法形成成為配線層11之鋁或銅等之金屬層。之後，將未圖示的光阻層作為遮罩來蝕刻該金屬層，並如第7圖及第9圖所示，於銲墊電極4的局部上以及第二絕緣膜10上形成例如厚度1 μm的配線層11。配線層11係覆蓋銲墊電極4及第二絕緣膜10且沿著半導體基板2的側面及背面而形成，當從半 導體基板2的主面垂直方向觀看時，如第9圖所示，配線層11係與電容電極9重疊。
此外，電容電極9與配線層11較佳為使用相同的材料(例如鋁)及相同的方法(例如濺鍍法)來形成。這是由於具有製造步驟單純化，且能降低製造成本的優點之故。
接著，形成覆蓋配線層11之未圖示的電極連接層(例如鎳層與金(Au)層的層疊)。形成電極連接層的原因是由鋁等所構成的配線層以及由銲錫等所構成的導電端子13a、13b、13c難以接合之故，以及防止導電端子13a、13b、13c的材料流入配線層11側之故。可在形成保護層12後形成該電極連接層。接著，如第8圖所示，在半導體基板2的側面及背面上形成由如阻焊劑之光阻材料所構成的保護層12。
接著，將保護層12的預定區域(導電端子形成預定區域)予以開口，在該開口內露出的電極連接層上網版印刷導電材料(例如銲錫)，並藉由熱處理使該導電材料回銲(reflow)，藉此如第8圖及第9圖所示，形成球狀的導電端子13a、13b、13c。導電端子13a為電源電壓供給用的端子，導電端子13b為接地電壓供給用的端子，導電端子13c為各種輸出入信號的端子。此外，導電端子13a、13b、13c的形成方法並未限定於上述方法，亦可藉由電解電鍍法或使用分配器(dispenser)將銲錫等塗佈於預定區域之所謂的分配法(塗佈法)等來形成。如此，銲墊電極4係經由配線層11而與導電端子13a、13b、13c電性連接。
接著，沿著複數個半導體裝置的交界之切割線DL來切斷保護層12或支持體7等，而分割成個別的半導體裝置15。用來分割成個別的半導體裝置的方法有切割法、蝕刻法、以及雷射切割法等。此外，支持體7係可維持在與半導體基板2貼附的狀態下，亦可在分割成個別的半導體裝置15之前或之後剝離。
藉由以上的步驟，完成晶片尺寸封裝型的半導體裝置15。半導體裝置15係經由導電端子13a、13b、13c而安裝至印刷基板等。此外，第9圖係從半導體基板2側觀看半導體裝置15時的概略平面圖，第8圖係相當於沿著第9圖的C－C剖線的剖面圖。
在第一實施形態的半導體裝置15中，由於在半導體基板2的背面上依序層疊電容電極9、第二絕緣膜10、以及配線層11，因此由疊層電容電極9、第二絕緣膜10、以及配線層11形成電容16。因此，例如將導電端子13a與電源電壓VDD的供給端子連接、將導電端子13b與接地電壓GND的供給端子連接時，能藉由電容16的充放電作用去除從導電端子13a、13b、13c侵入至內部的電磁雜訊，以及在電晶體的切換動作等時從半導體積體電路1的內部所產生的電磁雜訊，而防止半導體積體電路1的誤動作。
由於電容16的靜電電容係與電容電極9與配線層11的重疊面積以及第二絕緣膜10(電介質)的介電常數成正比，與第二絕緣膜10的厚度成反比，因此可藉由改變各參數來獲得期望的靜電電容。
此外，由於電容16形成在半導體基板2的背面上，因此即使設置該電容16，亦完全無需變更半導體基板2表面上的佈局，而不會使半導體裝置大型化。此外，由於可將半導體裝置15背面的幾乎整面作為電容16來使用，故容易增大靜電電容。因此，依據本實施形態的構成，能同時實現半導體裝置的小型化與電容元件的大電容化。
由於電容16與半導體積體電路1形成在同一個半導體晶片內，且與使用外掛的電容元件之情形相比電容16與半導體積體電路1之間的配線較短，能謀求低阻抗化與低電感化，因此具有有效去除電磁雜訊的效果。具體而言，例如電容16係具有100pF至500pF左右的靜電電容，藉此能實現去除與安裝具有0.01 μF靜電電容之外裝的電容元件相同程度的電磁雜訊之效果。如此，與一般外裝的電容元件相比，雖然電容16的靜電電容較小，但由於電容16配置在同一個半導體晶片內且非常接近半導體積體電路1，故能提升電磁雜訊的去除效果。因此，依據具備有電容16的構成，為電晶體的高速切換動作所必須之裝置等，亦可應用於容易產生高頻(數百MHz以上的頻率)的電磁雜訊之裝置。
此外，在第8圖及第9圖中，雖然構成為將預定電壓(通常為接地電壓)從導電端子13b經由配線層11與銲墊電極4供給至半導體基板2及電容電極9，但亦可如第10圖所示，構成為在半導體基板2的背面上形成與電容電極9直接連接的導電端子17，從導電端子17直接供給預定電壓 至電容電極9及半導體基板2。依據此構成，由於導電端子17與電容電極9接觸，因此具有能降低從導電端子17侵入的電磁雜訊的影響之優點。導電端子17係可在保護層12形成達至電容電極9的開口部，且以與形成上述導電端子13a、13b、13c的相同步驟(網版印刷法或鍍覆法等)來形成。
接著，參照附圖說明本發明的第二實施形態。與第一實施形態相同的構成係附上相同的符號並省略其說明。
第一實施形態中的電容電極9係僅形成於半導體基板2的背面上。相對於此，如第11圖所示，在第二實施形態中，半導體基板2的側面及背面的整體係被電容電極20覆蓋，而以電容電極20、第二絕緣膜10、以及配線層11來形成電容21。依據該構成，不僅是在半導體基板2的背面上，形成在側面側的面積部分能增大電容21的靜電電容。並且，與第一實施形態的構成相比，能進一步提升電磁雜訊的去除效果。
接著，參照附圖說明本發明的第三實施形態。與上述實施形態相同的構成係附上相同的符號並省略其說明。
如第12圖所示，在第三實施形態的半導體裝置中，形成從半導體基板2的背面至銲墊電極4之通孔(via hole)30，在通孔30內及半導體基板2的背面上形成阻障金屬層(barrier metal layer)31，在阻障金屬層31上形成由鋁或銅等之金屬所構成的配線層11。阻障金屬層31係例如由鈦(Ti)層、氮化鈦(TiN)層、鉭(Ta)層、氮化鉭(TaN)層、 或鎢化鈦(TiW)層等之金屬材料所構成，且在通孔30的底部(接近半導體基板2表面的附近)與銲墊電極4連接。
接著，在半導體基板2的背面與第二絕緣膜10之間形成與半導體基板2的背面接觸之電容電極9，而形成由電容電極9、第二絕緣膜10、阻障金屬層31、以及配線層11所構成的電容32。如此，本發明亦可應用於所謂貫穿電極型的半導體裝置，且可形成電容32。
貫穿電極型的半導體裝置係例如經由下列的步驟來製造：準備半導體基板2，該半導體基板2係隔著半導體積體電路1與第一絕緣膜3而形成有銲墊電極4，於對應銲墊電極4的位置形成貫穿半導體基板2之通孔30之步驟；在半導體基板2的背面上形成電容電極9之步驟；形成用以覆蓋通孔30的內壁以及半導體基板2的背面之第二絕緣膜10之步驟；去除通孔30底部的第二絕緣膜10之步驟；在通孔30內形成阻障金屬層31之步驟；在通孔30內以及半導體基板2的背面上藉由例如電解電鍍法等形成由鋁或銅等金屬所構成的配線層11之步驟；以及形成保護層12及導電端子13a、13b之步驟。上述步驟係用以概略說明本實施形態的貫穿電極型的半導體裝置的製造步驟的一例，並未限定於上述製造步驟，例如亦可在形成通孔30之前先形成電容電極9。
接著，參照第13圖及第14圖來說明本發明的第四實施形態。第14圖係從半導體基板2側觀看第四實施形態的半導體裝置時的概略平面圖，第13圖係相當於沿著第14 圖的D－D剖線的剖面圖。與上述實施形態相同的構成係附上相同的符號，並省略其說明。
第四實施形態的半導體裝置，配線層40係以在半導體基板2的背面上且為在第二絕緣膜10上會與電容電極9重疊的方式來形成。此外，以覆蓋配線層40與第二絕緣膜10的方式形成由氧化矽膜或氮化矽膜等所構成的第三絕緣膜41，並在第三絕緣膜41上，沿著半導體基板2的側面與背面形成與銲墊電極4連接的配線層42、11。於第三絕緣膜41的局部形成達至配線層40之開口部43，且經由該開口部43來連接配線層40與配線層42。
在第四實施形態的半導體裝置中，由於在半導體基板2的背面上依序層疊電容電極9、第二絕緣膜10、以及配線層40，因此由電容電極9、第二絕緣膜10、以及配線層40來形成電容44。因此，例如將導電端子13a與電源電壓VDD的供給端子連接、將導電端子13b與接地電壓GND的供給端子連接時，能藉由電容44的充放電作用去除從導電端子13a、13b、13c侵入至內部的電磁雜訊，以及在電晶體的切換動作等時從半導體積體電路1的內部所產生的電磁雜訊，而防止半導體積體電路1的誤動作。如此，對於半導體基板2的背面上的電容構成可考慮各種變形例。
此外，本發明並未限定於上述實施形態，在未脫離本發明的技術思想之範圍內可進行各種變更。例如，在上述實施形態中，雖針對具有球狀的導電端子之BGA(Ball Grid Array；球形陣列)型的半導體裝置加以說明，但本發明亦 可應用於LGA(Land Grid Array；柵格陣列)型或其他的CSP(Chip Size Package；晶片尺寸封裝)型的半導體裝置。本發明係可作為具有電容元件的半導體裝置而廣泛地應用。
1‧‧‧半導體積體電路
2‧‧‧半導體基板
3‧‧‧第一絕緣膜
4‧‧‧銲墊電極
5‧‧‧鈍化膜
6‧‧‧接著層
7‧‧‧支持體
8、43‧‧‧開口部
9、20‧‧‧電容電極
10‧‧‧第二絕緣膜
11、40、42‧‧‧配線層
12‧‧‧保護膜
13a、13b、13c、17‧‧‧導電端子
15‧‧‧半導體裝置
16、21、32、44‧‧‧電容
30‧‧‧通孔
31‧‧‧阻障金屬層
41‧‧‧第三絕緣膜
DL‧‧‧切割線
第1圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第2圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第3圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之平面圖。
第4圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第5圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之平面圖。
第6圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第7圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第8圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之剖面圖。
第9圖係用以說明本發明的第一實施形態的半導體裝置的製造方法之平面圖。
第10圖係用以說明本發明的第一實施形態的半導體 裝置的變形例之平面圖。
第11圖係用以說明本發明的第二實施形態的半導體裝置之剖面圖。
第12圖係用以說明本發明的第三實施形態的半導體裝置之剖面圖。
第13圖係用以說明本發明的第四實施形態的半導體裝置之剖面圖。
第14圖係用以說明本發明的第四實施形態的半導體裝置之平面圖。
1‧‧‧半導體積體電路
2‧‧‧半導體基板
3‧‧‧第一絕緣膜
4‧‧‧銲墊電極
5‧‧‧鈍化膜
6‧‧‧接著層
7‧‧‧支持體
9‧‧‧電容電極
10‧‧‧第二絕緣膜
11‧‧‧配線層
12‧‧‧保護膜
13a、13b‧‧‧導電端子
15‧‧‧半導體裝置
16‧‧‧電容
DL‧‧‧切割線

Claims (4)

  1. 一種半導體裝置，係具備有：半導體基板；半導體積體電路，係形成於前述半導體基板的表面；銲墊電極，係與前述半導體積體電路連接；電容電極，係與前述半導體基板的背面接觸，並從前述半導體基板的背面上延伸至前述半導體基板的側面上而形成；絕緣膜，係形成於前述半導體基板的側面上之前述電容電極上；以及配線層，係與前述電容電極重疊而形成於前述半導體基板的側面上之前述絕緣膜上，且與前述銲墊電極連接；其中，由前述電容電極、前述絕緣膜、以及前述配線層來形成電容。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述半導體基板係具有貫穿前述半導體基板之通孔；前述半導體基板的側面係包含前述通孔的內壁面。
  3. 如申請專利範圍第1項之半導體裝置，其中，於前述半導體基板的背面上具有：第一導電端子，係經由前述配線層而與前述銲墊電極電性連接；以及 第二導電端子，係與前述電容電極接觸。
  4. 如申請專利範圍第1至3項中任一項之半導體裝置，其中，於前述半導體基板上貼附支持體。
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