US20080258258A1

US20080258258A1 - Semiconductor device

Info

Publication number: US20080258258A1
Application number: US12/103,857
Authority: US
Inventors: Katsu Horikoshi; Hisayoshi Uchiyama; Takashi Noma; Yoshinori Seki; Hiroshi Yamada; Shinzo Ishibe; Hiroyuki Shinogi
Original assignee: Sanyo Electric Co Ltd; Sanyo Semiconductor Co Ltd
Current assignee: Deutsche Bank AG New York Branch
Priority date: 2007-04-20
Filing date: 2008-04-16
Publication date: 2008-10-23
Anticipated expiration: 2028-04-16
Also published as: TW200843086A; US8410577B2; CN101290934A; JP5301108B2; TWI396275B; JP2008270573A; CN101290934B

Abstract

The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.

Description

CROSS-REFERENCE OF THE INVENTION

This application claims priority from Japanese Patent Application No. 2007-112336, the content of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention
The invention relates to a semiconductor device having a capacitor element.
2. Description of the Related Art
In order to reduce variation of a voltage level by influence of electromagnetic noise to prevent malfunction of a semiconductor die, a capacitor element called a bypass capacitor has been mounted on a terminal (a source terminal or a ground terminal) of a semiconductor die conventionally.
For example, Japanese Patent Application Publication No. Hei 05-021698 discloses a semiconductor device in which a semiconductor die and an external capacitor element called a die capacitor are mounted on the same substrate and packaged in a die form as a whole.
Japanese Patent Application Publication No. 2000-349238 discloses a semiconductor device formed with a capacitor element functioning as a bypass capacitor by using a multilayered wiring layer on a semiconductor substrate and an interlayer insulation film between these.
However, although the structure using the external capacitor element as described in Japanese Patent Application publication No. Hei 05-021698 obtains large capacitance in the capacitor element, it needs a space for mounting the capacitor element on the substrate. Therefore, it is difficult to reduce the size of the device as a whole.
Furthermore, since recent semiconductor dies operate fast, high frequency (frequency of several hundreds MHz or more) electromagnetic noise is likely to increase by a high speed switching operation of a transistor to degrade operation characteristics. Therefore, a technique of effectively removing such electromagnetic noise is desired.
One method of reducing influence of electromagnetic noise is that a semiconductor die and a capacitor element are formed adjacent as much as possible to reduce the impedance and inductance of a wiring (a source wiring or a ground wiring) connecting these. However, the wiring may be extended long for a layout design in some cases, and when the semiconductor die and the capacitor element are individual components there is a limitation on the adjacent formation of these.
As described above, the structure having the external capacitor element has a problem of difficulty in realizing both the size reduction of the semiconductor device and the reduction of an influence of electromagnetic noise.
On the other hand, the conventional structure having the capacitor element formed in the same semiconductor device as described in Japanese Patent Application publication No. 2000-349238 may reduce the impedance and inductance of the wiring more than the case using the external capacitor element, but it requires a large area for obtaining enough capacitance to effectively remove high frequency electromagnetic noise.
Therefore, this has a problem of difficulty in size reduction of the semiconductor device since other functional elements (e.g. a driver circuit or a logic circuit formed by a transistor or the like, wirings connected to these, or the like) other than the capacitor element are formed on the same semiconductor substrate.
Therefore, the invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. Such a semiconductor device reduces an influence of electromagnetic noise.

SUMMARY OF THE INVENTION

The invention is for solving the above problem and its feature is as follows. The invention provides a semiconductor device including: a semiconductor substrate; a semiconductor integrated circuit formed on a front surface of the semiconductor substrate; a pad electrode connected to the semiconductor integrated circuit; a capacitor electrode formed contacting a back surface of the semiconductor substrate; an insulation film formed on a side surface of the semiconductor substrate and the capacitor electrode; and a wiring layer formed on the insulation film so as to overlap the capacitor electrode and connected to the pad electrode; wherein the capacitor electrode, the insulation film and the wiring layer form a capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device of a first embodiment of the invention.

FIG. 2 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIGS. 3A and 3B are a plan view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 4 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 5 is a plan view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 6 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 7 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 8 is a cross-sectional view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 9 is a plan view for explaining the method of manufacturing the semiconductor device of the first embodiment of the invention.

FIG. 10 is a plan view for explaining a modification of the semiconductor device of the first embodiment of the invention.

FIG. 11 is a cross-sectional view for explaining a semiconductor device of a second embodiment of the invention.

FIG. 12 is a cross-sectional view for explaining a semiconductor device of a third embodiment of the invention.

FIG. 13 is a cross-sectional view for explaining a semiconductor device of a fourth embodiment of the invention.

FIG. 14 is a plan view for explaining the semiconductor device of the fourth embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

A first embodiment of the invention will be described referring to figures. FIGS. 1 to 9 are cross-sectional views and plan views showing a process of manufacturing a semiconductor device in order. The manufacturing process described below is performed using a wafer form semiconductor substrate and a number of semiconductor devices are formed in a matrix configuration along predetermined dicing lines as borders, although the description is given about a process of forming one of these semiconductor devices for convenience.
First, as shown in FIG. 1, a semiconductor substrate 2 made of silicon (Si) or the like is prepared, of which the front surface is formed with a semiconductor integrated circuit 1 (e.g. a driver circuit or a logic circuit formed by integrating semiconductor elements such as a light receiving element such as a CCD sensor, a CMOS sensor or an illumination sensor, a light emissive element or a transistor, wirings connected to these, or the like). The semiconductor substrate 2 is about 300 to 700 μm in thickness, for example. Then, a first insulation film 3 (e.g. a silicon oxide film formed by a thermal oxidation method, a CVD method, or the like) is formed on the front surface of the semiconductor substrate 2 to have a thickness of, for example, 2 μm.
Then, a metal layer made of aluminum (Al), an aluminum alloy, copper (Cu) or the like is formed by a sputtering method, a plating method or other deposition method, and then the metal layer is etched using a resist layer (not shown) as a mask to form pad electrodes 4 having a thickness of 1 μm on the first insulation film 3. The pad electrodes 4 are electrodes for external connection electrically connected to the semiconductor integrated circuit 1 or its peripheral elements through wirings (not shown). A supply voltage, a ground voltage (or a reference voltage to the extent that it is not necessary 0 volts) or various signals are supplied from conductive terminals 13 a, 13 b and 13 c, which will be described below, to the semiconductor integrated circuit 1, the semiconductor substrate 2 and so on through the pad electrodes 4. Although the pad electrodes 4 are disposed on the both sides of the semiconductor integrated circuit 1 in FIG. 1, the position is not limited to this and these may be also disposed on the semiconductor integrated circuit 1.
Then, a passivation film 5 is formed on the front surface of the semiconductor substrate 2 (e.g. a silicon nitride film formed by a CVD method), covering the pad electrodes 4 partially or completely. In FIG. 1, the passivation film 5 is formed so as to cover the pad electrodes 4 partially.
Then, a supporting body 7 is attached to the front surface of the semiconductor substrate 2 including the pad electrodes 4 with an adhesive layer 6 made of epoxy resin, polyimide (e.g. photosensitive polyimide), resist, acrylic or the like being interposed therebetween. When the semiconductor integrated circuit 1 includes a light receiving element or a light emissive element, the adhesive layer 6 is preferably made of a suitable transparent material having light transmitting property since it is a passage of light emitted from the semiconductor integrated circuit 1 or entering the semiconductor integrated circuit 1.
The supporting body 7 may be a film form protection tape or a rigid substrate made of glass, quartz, ceramic, metal or the like, or may be made of resin, for example. The supporting body 7 has a function of supporting the semiconductor substrate 2 and protecting the surface of the element thereon. When the semiconductor integrated circuit 1 includes a light receiving element or a light emissive element, the supporting body 7 is made of a transparent or semitransparent material having light transmitting property.
Then, back-grinding is performed to the back surface of the semiconductor substrate 2 with a back surface grinder to thin the semiconductor substrate 2 to a predetermined thickness (e.g. about 100 μm). The grinding process may be replaced by an etching process, or a combination of a grinder and an etching process. There is also a case where the grinding process is not necessary depending on application or specification of an end-product and the initial thickness of the provided semiconductor substrate 2.
Then, as shown in FIG. 2, the semiconductor substrate 2 is selectively etched only in regions corresponding to the pad electrodes 4 from the back surface of the semiconductor substrate 2 to partially expose the first insulation film 3. Hereafter, this exposed portion is referred to as an opening 8.
This selective etching of the semiconductor substrate 2 will be described referring to FIGS. 3A and 3B. FIGS. 3A and 3B are schematic plan views on the semiconductor substrate 2 side, and FIG. 2 corresponds to a cross-sectional view of FIGS. 3A and 3B along line A-A.
As shown in FIG. 3A, the semiconductor substrate 2 may be etched into an almost rectangular shape smaller than the supporting body 7. It is noted that the openings 8 shown in FIG. 2 form a lattice-like structure in a plan view, and one lattice is shown in FIG. 3A. Alternatively, as shown in FIG. 3B, the semiconductor substrate 2 may be etched only in a region formed with the pad electrodes 4 so as to have an uneven periphery. The latter provides the larger overlapping area between the semiconductor substrate 2 and the supporting body 7 and the semiconductor substrate 2 remains near the periphery of the supporting body 7. Therefore, the latter structure is preferable for enhancing the support strength of the supporting body 7 for the semiconductor substrate 2. Furthermore, since the latter structure prevents the supporting body 7 from warping due to the difference in coefficient of thermal expansion between the semiconductor substrate 2 and the supporting body 7, cracking or separation in the semiconductor device is prevented. It is noted that the semiconductor substrate 2 may be designed into other plane shape than the shapes shown in FIGS. 3A and 3B. Hereafter, a description will be given about the manufacturing process in the case where the semiconductor substrate 2 is etched as shown in FIG. 3A.
Furthermore, although the sidewall of the semiconductor substrate 2 is etched obliquely so that the width of the semiconductor substrate 2 is wider on the front surface side in this embodiment, the semiconductor substrate 2 may be etched to have the constant width and form the sidewall perpendicular to the main surface of the supporting body 7.
Then, by a CVD method, a sputtering method or other deposition method, a capacitor electrode 9 made of, for example, a metal material such as aluminum, gold or silver is formed on the back surface of the semiconductor substrate 2 as shown in FIGS. 4 and 5 to have a thickness of, for example, about 1 to 2 μm. Alternatively, the capacitor electrode 9 may be formed after the back-grinding of the semiconductor substrate 2 and then the opening 8 may be formed by selectively etching both of the capacitor electrode 9 and the semiconductor substrate 2. The capacitor electrode 9 forms one electrode of a capacitor 16 as described below, and is fixed to the same potential (usually a ground potential) as that of the semiconductor substrate 2 in actual use. The larger area of the capacitor electrode 9 is more preferable for obtaining the capacitor element having as large capacitance as possible. FIG. 5 is a schematic plan view of FIG. 4 on the semiconductor substrate 2 side, and FIG. 4 is a cross-sectional view of FIG. 5 along line B-B.
Then, a second insulation film 10 is formed on the side and back surfaces of the semiconductor substrate 2 including in the opening 8 and on the capacitor electrode 9. This second insulation film 10 is a silicon oxide film or a silicon nitride film formed by a plasma CVD method, for example.
Then, the first insulation film 3 and the second insulation film 10 are selectively etched using a photoresist layer (not shown) as a mask as shown in FIG. 6. By this etching, the first insulation film 3 and the second insulation film 10 formed in a region from a portion of the pad electrodes 4 to dicing lines are selectively removed to expose at least a portion of the pad electrodes 4 on the bottom of the opening 8.
Then, a metal layer made of aluminum (Al), copper (Cu) or the like, which is to be wiring layers 11, is formed by a sputtering method, a plating method or other deposition method. Then, the metal layer is etched using a photoresist layer (not shown) as a mask to form the wiring layers 11 having a thickness of, for example, 1 μm on a portion of the pad electrodes 4 and on the second insulation film 10 as shown in FIGS. 7 and 9. The wiring layers 11 are formed along the side and back surfaces of the semiconductor substrate 2, covering the pad electrodes 4 and the second insulation film 10, and overlap the capacitor electrode 9 as shown in FIG. 9 when viewed from right above the semiconductor substrate 2.
The capacitor electrode 9 and the wiring layers 11 are preferably made of the same materials (e.g. aluminum) and formed by the same methods (e.g. a sputtering method). This advantageously simplifies the manufacturing process and reduces the manufacturing cost.
Then, an electrode connection layer (not shown) (e.g. a lamination layer of a nickel layer and a gold layer) is formed covering the wiring layers 11. The electrode connection layer is formed because the wiring layers 11 made of aluminum or the like and the conductive terminals 13 a, 13 b and 13 c made of solder or the like are rather difficult to be attached together and for the purpose of preventing the material of the conductive terminals 13 a, 13 b and 13 c from entering the wiring layers 11 side. Alternatively, the electrode connection layer may be formed after the formation of a protection layer 12. Then, as shown in FIG. 8, the protection layer 12 made of a resist material such as a solder resist is formed on the side and back surfaces of the semiconductor substrate 2.
Then, openings are formed in predetermined regions (the regions where the conductive terminals are to be formed) of the protection layer 12, a conductive material (e.g. solder) is formed on the electrode connection layer exposed in each of the openings by screen printing, and the conductive material is reflowed by a heat treatment, thereby forming the ball-shaped conductive terminals 13 a, 13 b and 13 c as shown in FIGS. 8 and 9. The conductive terminal 13 a is a terminal for supplying a supply voltage, the conductive terminal 13 b is a terminal for supplying a ground voltage, and the conductive terminals 13 c are terminals relating to various input/output signals. The method of forming the conductive terminals 13 a, 13 b and 13 c is not limited to this, and an electrolytic plating method, a so-called dispensing (coating) method in which solder or the like is applied in predetermined regions with a dispenser, or the like may be used for the formation. In this manner, the pad electrodes 4 are electrically connected to the conductive terminals 13 a, 13 b and 13 c through the wiring layers 11.
Then, the protection layer 12, the supporting body 7 and so on are cut along dicing lines DL which are borders of a number of semiconductor devices to separate these into individual semiconductor devices 15. The method of separating the semiconductor devices includes a dicing method, an etching method, a laser cutting method and so on. The supporting body 7 may remain attached to the semiconductor substrate 2, or may be removed before or after the semiconductor devices 15 are separated.
The chip size package type semiconductor device 15 is thus completed by this process. The semiconductor device 15 is mounted on a printed board or the like through the conductive terminals 13 a, 13 b and 13 c. FIG. 9 is a schematic plan view of the semiconductor device 15 on the semiconductor substrate 2 side, and FIG. 8 corresponds to a cross-sectional view of FIG. 9 along line C-C.
In the semiconductor device 15 of the first embodiment, the capacitor electrode 9, the second insulation film 10 and the wiring layers 11 are layered on the back surface of the semiconductor substrate 2 in this order, and these form the capacitors 16. Therefore, for example, when the conductive terminal 13 a is connected to a terminal for supplying a supply voltage VDD and the conductive terminal 13 b is connected to a terminal for supplying a ground voltage GND, electromagnetic noise entering inside from the conductive terminals 13 a, 13 b and 13 c and electromagnetic noise occurring in the semiconductor integrated circuit 1 by a switching operation of a transistor or the like are removed by the charging and discharging effects of the capacitors 16, thereby preventing the malfunction of the semiconductor integrated circuit 1.
Since the capacitance of this capacitor 16 is proportional to the area where the capacitor electrode 9 and the wiring layer 11 overlap and the dielectric constant of the second insulation film 10 (a dielectric), and inversely proportional to the thickness of the second insulation film 10, desired capacitance is obtainable by changing each of the parameters.
Furthermore, since the capacitors 16 are formed on the back surface of the semiconductor substrate 2, it is not necessary to change the layout on the front surface of the semiconductor substrate 2 by the formation of the capacitors 16, and the size of the semiconductor device is not increased. Furthermore, since almost the whole back surface of the semiconductor device 15 is usable as the capacitors 16, the capacitance is easily increased. Therefore, the structure of this embodiment realizes both the size reduction of the semiconductor device and the increase of the capacitance of the capacitor element.
Furthermore, since the capacitor 16 and the semiconductor integrated circuit 1 are formed in the same semiconductor die, the wiring between the capacitor 16 and the semiconductor integrated circuit 1 is shorter than in the case of using an external capacitor element, and thus the impedance and inductance thereof are reduced, the device has an excellent effect of removing electromagnetic noise. In one experiment, the equivalent effect of removing electromagnetic noise to the effect of a device provided with an external capacitor element having, for example, 0.01 μF capacitance was realized by providing the capacitor 16 having the capacitance of about 100 to 500 pF. In this manner, although the capacitance of the capacitor 16 is smaller than that of the general external capacitor element, since the capacitor 16 is disposed in the same semiconductor die and very near the semiconductor integrated circuit 1, the effect of removing electromagnetic noise is enhanced. Therefore, the structure having the capacitor 16 may be applied to a device which needs a high-speed switching operation of a transistor and easily generates high frequency electromagnetic noise (the frequency of several hundred MHz or more).
While a predetermined voltage (usually a ground voltage) is supplied from the conductive terminal 13 b to the semiconductor substrate 2 and the capacitor electrode 9 through the wiring layer 11 and the pad electrode 4 in the structure shown in FIGS. 8 and 9, the structure shown in FIG. 10 may be possible, in which a conductive terminal 17 directly connected to the capacitor electrode 9 is formed on the back surface of the semiconductor substrate 2 and a predetermined voltage is directly supplied from the conductive terminal 17 to the capacitor electrode 9 and the semiconductor substrate 2. In this structure, the conductive terminal 17 and the capacitor electrode 9 contact, so that an influence of electromagnetic noise entering from the conductive terminal 17 is advantageously reduced. The conductive terminal 17 is formed by forming an opening in the protection layer 12 to the capacitor electrode 9 and by the similar process to the process of forming the described conductive terminals 13 a, 13 b and 13 c (by a screen-printing method, a plating method or the like).
Next, a second embodiment of the invention will be described referring to figures. The same numerals are given to the same components as those of the first embodiment and a description thereof is omitted.
The capacitor electrode 9 in the first embodiment is formed only on the back surface of the semiconductor substrate 2. In the second embodiment, as shown in FIG. 11, the whole side and back surfaces of the semiconductor substrate 2 are covered by a capacitor electrode 20, and the capacitor electrode 20, the second insulation film 10 and the wiring layers 11 form capacitors 21. The capacitance of the capacitor 21 in this structure is increased by the amount of the area of the electrode 20 formed not only on the back surface of the semiconductor substrate 2 but also on the side surface thereof. The effect of removing electromagnetic noise is enhanced more than that of the structure of the first embodiment.
Next, a third embodiment of the invention will be described referring to figures. The same numerals are given to the same components as those of the above described embodiments and a description thereof is omitted.
In a semiconductor device of the third embodiment, as shown in FIG. 12, via holes 30 are formed from the back surface of the semiconductor substrate 2 to the pad electrodes 4, barrier metal layers 31 are formed in the via holes 30 and on the back surface of the semiconductor substrate 2, and the wiring layers 11 made of metal such as aluminum, copper or the like are formed on the barrier metal layers 31. The barrier metal layers 31 are made of a metal material such as, for example, a titanium (Ti) layer, a titanium nitride (TiN) layer, a tantalum (Ta) layer, a tantalum nitride (TaN), a titanium tungsten (TiW) layer or the like, and connected to the pad electrodes 4 on the bottoms of the via holes 30 (near the front surface of the semiconductor substrate 2).
The capacitor electrode 9 is formed between the back surface of the semiconductor substrate 2 and the second insulation film 10, contacting the back surface of the semiconductor substrate 2, and the capacitor electrode 9, the second insulation film 10, the barrier metal layers 31 and the wiring layers 11 form capacitors 32. In this manner, the capacitors 32 may be formed by applying the invention to the so-called penetrating electrode type semiconductor device.
This penetrating electrode type semiconductor device is formed by, for example, preparing the semiconductor substrate 2 formed with the semiconductor integrated circuit 1 and the pad electrodes 4 with the first insulation film 3 being interposed therebetween, forming the via holes 30 penetrating the semiconductor substrate 2 in positions corresponding to the pad electrodes 4, forming the capacitor electrode 9 on the back surface of the semiconductor substrate 2, forming the second insulation film 10 covering the inner sidewalls of the via holes 30 and the back surface of the semiconductor substrate 2, removing the second insulation film 10 on the bottoms of the via holes 30, forming the barrier metal layers 31 in the via holes 30, forming the wiring layers 11 made of metal such as aluminum, copper or the like in the via holes 30 and on the back surface of the semiconductor substrate 2 by, for example, an electrolytic plating method, and forming the protection layer 12 and the conductive terminals 13 a, 13 b. It is noted that this method is for describing the outline of the process of manufacturing the penetrating electrode type semiconductor device of this embodiment as an example. The method is not limited to this, and the capacitor electrode 9 may be formed before the formation of the via holes 30.
Next, a fourth embodiment of the invention will be described referring to FIGS. 13 and 14. FIG. 14 is a schematic plan view of a semiconductor device of the fourth embodiment on the semiconductor substrate 2 side, and FIG. 13 corresponds to a cross-sectional view of FIG. 14 along line D-D. The same numerals are given to the same components as those of the above described embodiments and a description thereof is omitted.
In the semiconductor device of the fourth embodiment, a wiring layer 40 is formed on the second insulation film 10 on the back surface of the semiconductor substrate 2 so as to overlap the capacitor electrode 9. A third insulation film 41 made of a silicon oxide film, a silicon nitride film or the like is formed so as to cover the wiring layer 40 and the second insulation film 10, and the wiring layers 42, 11 connected to the pad electrodes 4 are formed on the third insulation film 41 along the side and back surfaces of the semiconductor substrate 2. An opening 43 is formed in a portion of the third insulation film 41, reaching the wiring layer 40, and the wiring layer 40 and the wiring layer 42 are connected through this opening 43.
In the semiconductor device of the fourth embodiment, the capacitor electrode 9, the second insulation film 10 and the wiring layer 40 are layered on the back surface of the semiconductor substrate 2 in this order, and thus these form a capacitor 44. Therefore, for example, when the conductive terminal 13 a is connected to a terminal for supplying a supply voltage VDD and the conductive terminal 13 b is connected to a terminal for supplying a ground voltage GND, electromagnetic noise infiltrating inside from the conductive terminals 13 a, 13 b and 13 c and electromagnetic noise occurring in the semiconductor integrated circuit 1 by a switching operation of a transistor or the like are removed by the charging and discharging effects of the capacitor 44, thereby preventing the malfunction of the semiconductor integrated circuit 1. In this manner, there are various structures of the capacitor on the back surface of the semiconductor substrate 2.
The invention is not limited to the above described embodiments, and modifications are possible within the scope of the invention. For example, although the BGA (Ball Grid Array) type semiconductor device having the ball-shaped conductive terminals is used in the description of the above embodiments, the invention may be applied to a LGA (Land Grid Array) type or other CSP (Chip Size Package) type semiconductor device. The invention is widely applicable as a semiconductor device having a capacitor element.
In the structures explained above, the semiconductor integrated circuit is formed on one surface of the semiconductor substrate and the capacitor is formed on the other surface thereof, thereby realizing a smaller semiconductor device having a capacitor with larger capacitance than conventional.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor integrated circuit formed on a front surface of the semiconductor substrate;

a pad electrode disposed on the front surface so as to be connected to the semiconductor integrated circuit;

a capacitor electrode disposed on a back surface of the semiconductor substrate;

an insulation film disposed on the capacitor electrode; and

a wiring layer disposed on the insulation film and connected to the pad electrode,

wherein the capacitor electrode, the insulation film and the wiring layer are configured to form a capacitor.

2. The semiconductor device of claim 1, wherein the capacitor electrode, the insulation film and the wiring layer extend from the back surface of the semiconductor substrate to a side surface of the semiconductor substrate so that the extended portions of the capacitor electrode, the insulation film and the wiring layer form an additional capacitance to the capacitor.

3. The semiconductor device of claim 1, wherein the semiconductor substrate has a via hole penetrating the semiconductor substrate, and the insulation film and the wiring layer extend from the back surface of the semiconductor substrate into the via hole.

4. The semiconductor device of claim 1, further comprising a first conductive terminal disposed on the back surface of the semiconductor substrate and connected to the pad electrode through the wiring layer and a second conductive terminal disposed on the back surface of the semiconductor substrate and in contact with the capacitor electrode.

5. The semiconductor device of claim 1, further comprising a supporting body attached to the semiconductor substrate.

6. The semiconductor device of claim 1, wherein the capacitor electrode and the semiconductor substrate are configured to receive a reference voltage.