TWI329926B - Semiconductor devices and methods of manufacture thereof - Google Patents
Semiconductor devices and methods of manufacture thereof Download PDFInfo
- Publication number
- TWI329926B TWI329926B TW095135441A TW95135441A TWI329926B TW I329926 B TWI329926 B TW I329926B TW 095135441 A TW095135441 A TW 095135441A TW 95135441 A TW95135441 A TW 95135441A TW I329926 B TWI329926 B TW I329926B
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- gate
- region
- metal oxide
- nitride
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 199
- 238000000034 method Methods 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000463 material Substances 0.000 claims description 147
- 229910044991 metal oxide Inorganic materials 0.000 claims description 123
- 150000004706 metal oxides Chemical class 0.000 claims description 123
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 47
- 239000002019 doping agent Substances 0.000 claims description 35
- 239000000126 substance Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 24
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229910052719 titanium Inorganic materials 0.000 claims description 23
- 239000010936 titanium Substances 0.000 claims description 23
- 239000007943 implant Substances 0.000 claims description 21
- 238000005121 nitriding Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 230000009471 action Effects 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- -1 tungsten nitride Chemical class 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000004575 stone Substances 0.000 claims description 6
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910005889 NiSix Inorganic materials 0.000 claims description 4
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052797 bismuth Inorganic materials 0.000 claims description 4
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- 239000010955 niobium Substances 0.000 claims description 4
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- 229910019044 CoSix Inorganic materials 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- 229910008486 TiSix Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- 241000894007 species Species 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 claims description 2
- 229910021324 titanium aluminide Inorganic materials 0.000 claims description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 4
- SKKMWRVAJNPLFY-UHFFFAOYSA-N azanylidynevanadium Chemical compound [V]#N SKKMWRVAJNPLFY-UHFFFAOYSA-N 0.000 claims 2
- 229910052763 palladium Inorganic materials 0.000 claims 2
- OFEAOSSMQHGXMM-UHFFFAOYSA-N 12007-10-2 Chemical compound [W].[W]=[B] OFEAOSSMQHGXMM-UHFFFAOYSA-N 0.000 claims 1
- 229910000951 Aluminide Inorganic materials 0.000 claims 1
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 claims 1
- 206010036790 Productive cough Diseases 0.000 claims 1
- 238000003723 Smelting Methods 0.000 claims 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 claims 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- YRJLCOLNAYSNGB-UHFFFAOYSA-N [Nb].[Bi] Chemical compound [Nb].[Bi] YRJLCOLNAYSNGB-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 claims 1
- AUVPWTYQZMLSKY-UHFFFAOYSA-N boron;vanadium Chemical compound [V]#B AUVPWTYQZMLSKY-UHFFFAOYSA-N 0.000 claims 1
- 238000002309 gasification Methods 0.000 claims 1
- 229910052746 lanthanum Inorganic materials 0.000 claims 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 1
- RHDUVDHGVHBHCL-UHFFFAOYSA-N niobium tantalum Chemical compound [Nb].[Ta] RHDUVDHGVHBHCL-UHFFFAOYSA-N 0.000 claims 1
- 150000002825 nitriles Chemical class 0.000 claims 1
- UYDPQDSKEDUNKV-UHFFFAOYSA-N phosphanylidynetungsten Chemical compound [W]#P UYDPQDSKEDUNKV-UHFFFAOYSA-N 0.000 claims 1
- JKJKPRIBNYTIFH-UHFFFAOYSA-N phosphanylidynevanadium Chemical compound [V]#P JKJKPRIBNYTIFH-UHFFFAOYSA-N 0.000 claims 1
- 229910052703 rhodium Inorganic materials 0.000 claims 1
- 239000010948 rhodium Substances 0.000 claims 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims 1
- 210000003802 sputum Anatomy 0.000 claims 1
- 208000024794 sputum Diseases 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 59
- 230000005669 field effect Effects 0.000 description 31
- 230000000295 complement effect Effects 0.000 description 30
- 230000008569 process Effects 0.000 description 15
- 238000012546 transfer Methods 0.000 description 13
- 230000008901 benefit Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000011282 treatment Methods 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- LJIGZUPJIWDZJM-UHFFFAOYSA-N [N].[Ti].[Ti] Chemical compound [N].[Ti].[Ti] LJIGZUPJIWDZJM-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 241000282320 Panthera leo Species 0.000 description 2
- 229910020776 SixNy Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000010454 slate Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- QYEXBYZXHDUPRC-UHFFFAOYSA-N B#[Ti]#B Chemical compound B#[Ti]#B QYEXBYZXHDUPRC-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 241000027294 Fusi Species 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 208000003788 Neoplasm Micrometastasis Diseases 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052772 Samarium Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- WBQCYHBKOHGNQI-UHFFFAOYSA-N [N].[As] Chemical compound [N].[As] WBQCYHBKOHGNQI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910001566 austenite Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000003995 emulsifying agent Substances 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000001912 gas jet deposition Methods 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 235000002020 sage Nutrition 0.000 description 1
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000017105 transposition Effects 0.000 description 1
- PBYZMCDFOULPGH-UHFFFAOYSA-N tungstate Chemical compound [O-][W]([O-])(=O)=O PBYZMCDFOULPGH-UHFFFAOYSA-N 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Description
1329926 九、發明說明: 【發明所屬之技術領域】 且特別有關具有複數閘 本發明大致有關半導體裝置 極及其製造方法。 【先前技術】 半導體裝置係被用於各種電子應用,如個人電腦 機,數位相機及其他電子設備。半導體裝置通常藉由 沉積絕緣或介電層,傳導層及半導物質層於一半導體基板 上’及使用石板印麵製該各層來職其電子組件及元件。 一電晶體係為廣泛用於半導體裝置中之一元件。例 如’單積體電路(ic)上具有數百萬電晶體。被用於半導體裝 置裝置中之共同電晶體類型,係為金屬氧化物半導體場效 電晶體(MOSFET)。傳統金屬氧化物半導體場效電晶體具有 可控制通道區域之-難,且通常被稱為相極電晶體。 早期金屬氧化物轉體場效電晶體係麵—摻雜類型來創 造包含正或負通道電晶體之單電晶體。被稱為互補金屬氧 化物半導體(CMOS)裝置之其他更新設計’係使用互補配置 之正及負通道裝置,如正通道金屬氧化物半導體(pM〇s)電 晶體及負通道金屬氧化物半導體_〇5)電晶體。 傳統成批單閘極平面金屬氧化物半導體場效電晶體裝 置係無法達成45奈米或更大之未來技術節點要求效能。經 了成批裝置概念係以複合三維掺雜輪廓為基礎,其包含通 道植入’源極及汲極植入,輕度摻雜汲極(LDD)擴充植入, 6 及口袋/暈輪植入處理,由於無法潛在控制通道區域及深底 基板而造成摻雜變動增加及較強寄生短通道效應,所以其 尺寸不可向下度量。因此,在此被併入參考之2002年國際 半導體技術藍圖(ITRS)版本中揭示之國際半導體技術藍 圖,係提出兩最新設計概念:完全耗盡平面絕緣層上覆矽 (SOI)金屬氧化物半導體場效電晶體裝置,及一垂直多閘極 鰭式場效電晶體(FinFET)或三閘極裝置。 因此,具多閘極之電晶體係為一新興電晶體技術。雙 閘極電晶體具有彼此面對面且可控制相同通道區域之兩並 列閘極。鰭式場效電晶體係為垂直雙閘極裝置,其中通道 係包合一垂直鰭,其包含通常形成於絕緣層上覆矽基板上 之半導體物f。,鰭式場效電晶體兩閘極係被形成於垂直鰭 之對向側壁上。二閘極電晶體係具有可控制相同通道區域 之三閘極,例如該通道包含該垂直鰭,該閘極之二係被形 成於垂直鰭之侧面上,而第三閘極係被形成於該鰭頂部 上,。鰭式場效電晶體結構類似於三閘極電晶體,該第三閘 極為該_部上佈置之輯物質或硬鮮所阻隔。縛式場 效電晶體及三_電晶體’及某些形成它們之製造挑戰, 係於在此被併入參考N〇wak,RJ等人於2〇〇4年丨月/2月份 IEEE ^^^^S.|^i4(Circuits&Devices Magazine)^ 20-31 頁中標題為”在邊緣上猶^ :以制極及料場效電晶體 技術克服矽定標障礙,,文件中說明。 ^式場效電晶體及三閘極電晶體可被絲形成互補金 屬氧化物半^體裝置。—個或好鰭式場效電晶體可被當 作正通道金屬氧化物半導體及/或負通道金屬氧化物半導體 電晶體:通常並列兩或更多鰭係被用來形成單正通道金屬 氧化物半導體或負通道金屬氧化物半導體電晶體。如在此 被併入參考Chang,L等人於2003年II月份91冊第n部 IEEE事名第1860-1873頁’標題為’,極端定標石夕奈互補金 屬氧化物半導體裝置,,文件巾說明’鰭式場效電晶體可較平 面電晶體結構更積極作定標,且顯示低·感應汲極漏茂 (GIDL)。然而,如鰭式場效電晶體之多閘極電晶體係較平 面互補金屬氧化物半導體裝置更難製造及複雜,且其需明 顯不同物質並引進不同處理挑戰。 再者,設計互補金屬氧化物半導體裝置達成該互補金 屬氧化物半導體裝置之正通道金屬氧化物半導體及負通道 金屬氧化物半導體電晶體之對稱門梧電壓乂係很重要。然 =’虽特別是具有多閘極之先進電晶體設計裝置愈做愈小 2 ’很難找出可達成對稱門檻電壓Vt之㈣,裝置結 製造處理。 造户=此,技術領域巾需要多閘極電晶體之改良結構及製 【發明内容】 :_體_之最新結構及方法之本發 ’大致可解決或智取這些及其關題並達成 半導體電晶體之閘極物質第—參數及第二^ 1= 1329926 來諧調該閘極物質作用函數。某些實施例中,金屬係 改變=極物質厚度當作具有可軸或可調整作用函數^開 極物質,及針對正通道金魏化物半賴及貞通道金 化物半導體多閘極電晶體,調整該金屬厚度來達成預期作 用函數。其他實施例中,係將閘極物質植人摻雜物來達成 預期作用函數。 依據本發明較佳實施例,一種半導
電晶體’該第-電晶體包含至少兩第—間:置:;上 第-閘極具有—第—參數。該半導體裝置包含接近該第— 電晶體之-第二電晶體,該第二電晶體包含至少兩第二間 極。該至少兩第二閘極具有—第二參數。該第二參數盘該 第一參數不同。 x
〃依據本發明另一較佳實施例,一種半導體裝置包含一 第-電晶體’該第-電晶體包含至少兩第—閘極,而該至 少兩第-閘極具有-第m二電晶體係配置=近 該第-電晶體,該第二電晶體包含至少兩第二閘極,該至 少兩第二閘極具有-第二厚度,該第二厚度與該第一厚度 不同。該第-厚度係建立該至少兩第1極之—第一作$ 函數’而該第二厚度係建立該至少兩第二閘極之—第二作 用函數,其中該第二作用函數與該第一作用函數不同。一 依據本發明再另一較佳實施例,一種半導體裝置包含 -第-電晶體,該第-電晶體包含至少兩第—開極,= 至少兩第-閘極具有一第一摻雜等級〜第二電晶體係配 置接近該第一電晶體,該第二電晶體包含至少兩第二閘 9 t °亥至少兩第二閘極具有一第二摻雜,等 少兩第等級不同。該第一推雜等級可建立該至 立該至少Γί P個錄,喊第二_等級可建 與該第—翻轉不同。 作用函數 法,較佳實關,-種半導μ置製造方 -他 第—電日日日體’該第-電日日日體包含至少兩第 甲° ,而該至少兩第一閘極具有一第一參數。一帝 曰_曰體升V成接近該第—電晶體,該第二電晶體包含 =:;::第二_具有-第二參數。該第二參數 本發明較佳實施例優點係包含提供製造電晶體裝置及 其結構最新方法。可製造多閘極互補金屬氧化物半導體裝 置,其中多閘極互補金屬氧化物半導體裝置之正通道金屬 氣化物半導體電晶體及負通道金屬氧化物半導體電晶體具 有實質對稱Vt。金仙物f厚度及/或閘極物質摻雜等級係 建立該電阳體間極之作用函數,及建立電晶體之門楹電塵 vt。某些實施例中,相同物質係較佳用於正通道金屬氧化 物半導體及負通道金屬氧化物半導體電晶體之閘極,而降 低沉積及蝕刻兩不同閘極物質所需努力,且亦避免製造處 理作用時之污染。其他實施例巾,單f雜物質物質沉積, 而正通道金屬氧化物半導體裝置或負通道金屬氧化物半導 體電晶體係植入摻雜物來調整該作用函數。 上述已更廣泛說明本發明實施例之特性及技術優點, 1329926 可較佳理解以下本發明詳細說明。此後.將說明本發明附加 特性及優點,其形成本發明申請專利說明主題。熟練技術 人士應了解揭示概念及特定實施例可立即當作修正或設計 其他結構,如電容器或閘極二極體,或可執行本發明相同 目的之其他處理之基礎。熟練技術人士亦應了解該同等建 構並不背離附帶申請專利範圍中說明之本發明精神及範 脅。
【實施例詳細說明】 本較佳實施例製作及使用係被詳細討論如下。然而, 應理解本發明可提供具體化為歧特定文脈之許多可應用 發明性概念。討論之特定實施例僅植造及使用本發明之 例證’而不限制本發明範曹。
—電子學中’,,作用函數,,係為通常以電子伏特測量,將 Fermi等級移至離表面外—無限距離之一點 ==:::質之物謙^ 物暂傳t,過去料體物㈣被#作電晶體裝置之閘極 =導體物質作用函數可藉由摻雜半導體物二 :數,而摻雜购,約515電子伏特:: 電晶體之服賴。 切體仙函鋪直接影響 為了達成先進電晶體設計所需之裳置效能,係趨向使 11 用金屬間極物質及高k介電物 八 閉極係較傳統多晶梦間極為佳,可避^描^物質。金肩 厚度_。然而,用作應並降 體褒置,特別是用於具有開極介 、,屬乳化物半導 =氧化物半_,屬閘= 多電―it ::函4數广_,所,此定義其為=;=r 例如,4.1電子伏特及5 2電子 罨子伏特。 及傳導帶間之電子伏特能隙。在價帶 定義為接近約祕電子伏特之作用函數;;中間^名雜 =化物半導體裝置之近,間隙作用函‘ :::==化物半導體裝置,_ = ,術領_需具有多閘極互騎化物半導 函數之金屬開極。為使互補金屬氧化物半導 效電㈣技術提供優於雜敍齡觀化 體技術之敢大效能利益,需解決之—議 導
Vt控制之可諧調作用函數閘極技術。 、、威電壓 f發明實施例之-特徵係分職出具有如多閘極 道金屬魏物半導體裝置及㈣極正通道金屬氧化物丰 體裝置約4.45電子伏特及4·85電子伏特作用函數之兩近中 12 1329926 間隙金屬·物質。這些作用函數可達成互補金屬氧化物 半導體裝置所需之_ Vtn及@ 〜 〇.3,本發明實施編—特徵翁這兩金屬閘極物質整合 為多閘極裝置處理流程。
本發明實施例可藉由揭示可用於作為負通道金屬氧化 物半導體電晶體及正通道金屬魏物轉體電晶體之多閑 極互補金屬氧化物半導體電晶财之祕物質來達到技術 優勢。-實施例中,閘極物質較佳包含氮石夕化欽。另一實 施例中’閘極物質較佳包含氮化叙或氮化欽。閘極物質亦 可包含其他物質。某些實施财,貞通道金魏化物半導 體電晶體及正通道金屬氧化物半導體電晶體之作用函數可 藉由譜調或調整該閘極物質厚度做調整。因為鄰近閑極介 電質之_物㈣為-金屬’所以可避免使用閘極介電質 之高k介電物賊產生之Fenni釘扎效應。例如某些實施 例中,請道金屬氧化物半導體電晶體及正通道金屬氧化 物料體電晶體之多閘極,亦可包含配置於其上表 一半導體物質層。 本發明將參考特定文脈,亦即互補金屬氧化物半導 韓式場效電晶齡置+之触實關。然而,本發明實施 例亦可被施加至其他半導體裝置剌,其+如三閘極裂置 具有兩個或更多閘極之電晶體可使用。注意,圖式中,、僅 顯示-互齡屬氧化物铸體裝置;然而,在此說明之 製造處理綱可具有許乡形雜半導體工件上之電晶體。 在此說明之金屬層係可藉由改變處理情況而非曰常精確 13 地沉積及_。,,_,,名詞係涉及電晶·體之馳,而這些 名Θ在此交換做使用。 第1至5圖顯示依據本發明較佳實施例於各製造階段 處之半_展置100橫斷面圖式,其中一互 半導體裝置包含具有不同閘極物質厚度 屬氧化物半導體電晶體及負通道金屬氧化物半導 體現在參考第-圖,顯示包含一工件之半 觸知、斷面圖式。工件1〇2較佳包含一絕緣層上覆絲^。 例如,該絕緣層上覆石夕基板包含半導體物質104之第-層, 其包含一基板,配置於該半導體物質104第一層上之一埋 、、巴緣層106或埋入氧化層,及配置於該埋入絕緣層⑽ 之半導體物質108之第二層。工件1〇2亦可包含形成於工 件1〇2其他區域中無圖式之其他主動組件或電路。例如, =件102可包含單晶石夕上之氧化石夕。工件1〇2可包含如電 晶體’二極體等之其他傳導層或其他半導體元件。例如坤 化鎵’化銦’石夕/鍺或碳切之化合半導體可用來取代石夕。 件102可摻雜如p型摻雜物及N型摻雜物以分別形成p 井及N井(無圖式)。例如,雖然半導體物質⑽之第二層 可替代地包含其他物質及尺寸,但半導 __ 層通常包含具有約⑽奈米厚度之石綱。f 第一 硬幕罩110/112/114係被形成於工件1〇2上。硬幕罩 110/112/114係包含第一氧化物層11〇,其包含形成於工件 102上約5奈米或更少之二氧化矽。包含約2〇奈米之 之氣化物112係形成於第-氧化物層110上。包含約2〇奈 米或更少二氧化㊉之第二氧化物層114·係形成氮化物n2 上。例如,可替代是,硬幕罩110/112/114可包含其他物質 及尺寸。 、 _如圖式,半導體裝置100包含正通道金屬氧化物半導 體裝_成之至少-第—區域117,及負通道金屬氧化物半 導體農置七成之至少—第二區域118。例如,該圖式中僅顯 不一第一區域117及一第二區域118 ;然而,半導體裝置 100上可形成許多第一區域117及第二區域118。第一區域 :17及第二區域118可藉由隔離區(第1圖不顯*,例如見 第14圖,392)分隔。 硬幕罩110/112/114係使用石版印刷來模製,例如藉由 沉積光致抗侧層於硬幕罩11()/112/114上,使用石版^ 幕罩將光致抗蝕劑層曝光能量,發展光致抗蝕劑層,及將 光致抗蝕劑層當作模製硬幕罩11〇/112/114之幕罩。如第2 圖所示,硬幕罩110/112/114及可選擇地光致抗钱劑層係被 當作模製工件102之半導體物質之第二層。例如,埋 入絕緣層106可包含半導體物冑108帛二層钱刻處理之一 蝕刻終止層。例如,埋入絕緣層106頂部部分可於半導體 物質108第二層蝕刻處理期間移除.例如,埋入絕緣層1〇6 可具有約150奈米厚度,且可蝕刻包含約15奈米或更少之 一量山’雖然d!可替代地包含其他尺寸。 半導體物質108第二層可形成以遠離工件1〇2水平方 向之垂直方向延伸之半導體物質1G8垂直鰭。鰭式結構1〇8 可當作在此進-步說明之正通道金屬氧化物半導體及負通 15 道金屬氧化物半導縣置之通道。_.神 =d但,了式T通常具有可二 ::::rri〇8^d2 可更大,如具有_上 其他參數亦具有決定尺寸d2之效應,但^=二2
例如,鰭式結構1〇8具有等於半導體物们〇8第二層 曰度之-而度。半導體震置卿之第—區域117及第二區 域118中僅顯示兩韓式結構應;然而,雖然可使用其他替 代地數量鰭式結構1G8 ’但各貞通道金魏化物半導體及正 通道金屬氧化物半導縣置可具有許多財結構,如約i 至200縛式結構。
如第2圖所示,閘極介電f 116形成於縛式半導體物 質108側壁上。如圖式’閘極介電f 116可使用如僅氧化 半V體物質108之熱氧化處理來形成。例如,閘極介電質 Π6 了替代地使用;儿積處理來形成,產生亦形成於埋入絕緣 層106及硬幕罩110/112/114(無圖式)上之閉極介電質116 之一薄層。雖然閘極介電質116可替代地包含其他物質, 但閘極介電質較佳地包含铪為基礎介電質,如Hf〇2,
HfSiOx ’ Al2〇3,Zr02 ’ ZrSiOx,Ta205,La203,其氮,SixNy, SiON,HfA10x,HfA10x N—,ZrA10x,ZrAI〇x Ny,SiA10x,
SiA10x Nj.x.y > HfSiA10x * HfSiA10x Ny » ZrSiAl〇x > ZrSiA10x Ny ’其組合或其與二氧化梦之組合。 16 某些實施例中,閘極介電質116較佳包含具有較二氧 化矽介電常數為大之介電常數之一高k介電物質。例如, 閘極介電質116較佳包含具有約4.0或更大之介電常數之一 高k介電物質。雖然閘極介電質116可替代地包含其他尺 寸,但一實施例中,閘極介電質116較佳包含約5〇埃或更 少之一厚度。 ^接著,如第3圖所示,具有一厚度d3之閘極物質12〇 係形成於第一區域117及第二區域118中之鰭式結構上。 雖然閘極介電質116可替代地包含其他尺寸,但閘極物質 120例如較佳包含約5〇〇埃或更少之一厚度山。 一實施例中’閘極物質120較佳包含氮矽化鈦(TiSiN), 其係為具有視厚度而定之一可變作用函數之一物質。例 如,閘極物f 120較佳包含氮化组或氮化鈦。雖然閘極物 質120可替代地包含其他物冑,但其他實施例中,閑極物 貝120較佳包含如氮石夕化鈦,氮化欽,氮化艇,钮,釘, 氮化給,鶴,銘,釕,氮化釕,氮石夕化叙,NiSix,CoSix ’ 孤乂 ’銀,γ,始,鈦,鈦化始,纪,鍊,錢,欽,給,錯, 乳銘化鈦’錮,氮化翻,氮石夕化錯,氮化錯,氮化給,氮 石夕化铪’氮化鶴’鎳,镨,氮化飢,鶴化鈦之硼化物,磷 化物或銻化物’部份其魏物質,完全其魏物質,及/或 其組合物。_物質12G較佳包含例如作職數可藉由改 變物質厚度而改變之一物質。 雖然閘極物質12G可替鶴錢其_纽積技術被 沉積,但間極物質12〇可藉由如化學汽相沉積㈣^,原子 17 層/儿積(ALD),有機金屬化學汽相沉積(M〇CVD),物理汽 相沉積(PVD),或喷射汽相沉積(1¥1))被沉積。 π 閘極物質120包含半導體物質1〇8之一鰭之第一侧壁 上之第一閘極,及該鰭式半導體物質1〇8第一側壁對侧上 之第二閘極。因此,具有一雙閘極結構之一鰭式場效電晶 體係形成於半導體物質108各鰭上。再次,例如若干鰭 可並列放置形成工件102之第一區域117中之一正通S道金 屬氧化物半導體裝置,或形成第二區域118中之一負通道 金屬氧化物半導體裝置。 、、 雖然亦可使用其他方法及處理參數來形成閘極物質 120 ’但若閘極物質120包含氮石夕化鈦,則閘極物質較 佳係於約攝氏340度溫度及約60托壓力時使用〇 u克/分 鐘之TDEAT前導物及氣體,每分鐘約1〇〇標準立方公分 (s.c.c.m.)之SiH4 ’每分鐘約5,_標準立方公分之氨之化學 汽相沉積而形成。 如第4圖所示,幕罩122係覆蓋著工件1〇2之第一區 域117。幕罩122可沉積於工件102全部表面,且使用石板 印刷從第二區域118被移除以曝光第二區域118中之問極 物質120。例如幕罩122可包含一層光致抗蝕劑及/或一硬 幕罩。一實施例中,雖然亦可使用其他物質,但幕軍122 可包含如SixNy之氮化物質。 如第4圖所示’當閘極物質120至少一上部件從工件 102之第二區域118被移除時,幕罩122係被當作—幕罩。 雖然可使用其他蝕刻處理,但閘極物質120上部件移除處 18 1329926 理係可包含如時間蝕刻處理及/或溼式姓.刻處理之—蝕刻處 理。例如’該姓刻處理包含如反應離子蝕刻(ΜΕ),溼式蝕 刻,或如反向原子層沉積處理之原子層蝕刻。例如,幕罩 122可保護第-區域117中之閘極物質12〇於侧處理期間 不被移除。 例如,第二區域118中之閘極物質12〇於钱刻處理移 除閘極物質120上部件之後較佳包含約1〇〇埃或更少之一 厚度山。例如,正通道金屬氧化物半導體裝置之第一區域 1Π中之閘極物質120厚度山係較佳大於負通道金屬氧化 物半導體裝置之第二區域118中之閘極物f 12G厚度屯。 例如本發明實施例中,係依據第一區域117及第二區域118 中之間極物質120預期侧函絲佳選制極物f 12〇之 厚度屯及d4。 雖然亦可使用其他化學物,但若硬幕罩122包含氮化 石夕,則可使用如熱顧移除該硬幕罩122。如第4圖所示, 半導體物質124之-選擇層可形成於閘極物f 12()上。例 如’雖然半導體物質m之層可替代地包含其他尺寸及物 ^但半導體物質m之層可包含具有約2〇〇〇埃或更少之 -厚度之多晶梦。例如’半導體物質124包含形成於工件 102之第一區域117及第二區域118中之部分電晶體閉極。 -實施例中’細式,較佳所有閘極物f i2G係於姓 :=中攸第_區域118上被移除。此實施射,閑極物 :另=層接著被沉積於第二區域m及硬幕罩⑵上。或 疋更幕軍ID可於閘極物質附加層被沉積之前被移除來再 19 1329926 • 沉積閘極物質於工件之第二區域ιΐ8上.。例如,閘極物質 . =加層可較佳包含被列為閘極_ 12〇較佳物質之相同物 貝0 接^繼續半導體裳置1〇〇之製造處理。例如,閑極物 f。卩件可被移除以形成如互補金屬氧化物半導體績式 場效電晶體之閘極,閘極物質120及可選半導體物質124 係被同時模製給第一區域117及第二區域118,以分別形成 • 第一區域117及第二區域118中之正通道金屬氧化物半導 體及負通道金屬氧化物半導體多閘極電晶體之間極。附加 絕緣物質層可形成於·上。如第13及14騎權此做 進-步說明),將接觸籍式場效電晶體之源極,及極及閘極。 曰具優點地’可形叙補金屬氧錄半導體鰭式場效電 日日體裝置’其中第一區域m中之多開極正通道金屬氧化 物半導體裝置係包含較第二輯118中之多閘極負通道金 • 屬氧化物半導體裝置為厚之閘極⑽。例如,多閘極正通道 金屬氧化物半導體裝置之閘極1如較佳具有大於多閘極負 通道金屬氧化物半導體裝置之閘極⑽厚度約50埃多 之一厚度。 、 第6及7圖顯示依據本發明一實施例製造包含多閘極 電晶體且具有不同閘極物質厚度之互補金屬氧化物半導體 裴置之另一方法橫斷面圖。相似數字如同用於第丨至5圖 般地用於第6及7圖,而類似物質及厚度係如同上述實: 例所說明者較佳做使用。 只 如第6圖所示’此實施例中,具有厚度屯之第一間極 20 物質220a係形成於鰭式結構2〇8上(如釔置於鰭式結構2⑽ 上之閘極介電值216及硬幕罩21〇/212/214上)。例如包 含光致抗_或硬幕單層之幕罩⑽係形成於半導體褒置 200之第二區域218上。第二閘極物質220b厚度(16係形成 於第:區域217中之第—閘極物質22〇a上及第二區域218 中之幕罩230上。如第7圖所示,使用金屬剝離⑽__技 術,當幕罩230被移除時,第二閘極物質22%係從第二區 域218上被移除。 因此’如第1至第5圖所示實施例,第-區域217中 之閘極220a/22〇b係包含大於第二區域218中之閉極物質 220a厚度(15之-厚度d5 + d6。如第7圖所示,半導體物質 224之一層可被形成於第一區域217中之閘極物質 220a/220b上及第二區域218中之閘極物質22〇a上。 第8圖為顯示依據本發明實施例具有若干類型閑極介 質物質不同厚度之氮魏鈦閘極_函數圖式。包含問極 介電質二氧姆具有不同厚度之氮㈣鈦閘極物㈣㈣ 係顯示於232 ;包含閘極介電質Hf〇x之氮梦化關極物質 116/216係顯不於234 ;而包含閘極介電質HfSi〇x之氮石夕化 鈦閘極物質1膽6係顯示於236。顯示於y軸上之作用函 數係依據顯示於X軸上以埃表示之氮魏鈦酿物質厚度 而改變。 第9圖顯示具有各當作兩不同沒極對源極電壓(彻) 閘極物質之未摻雜通道及多晶石夕之正通道金屬氧化物半導 體及負通道金屬氧化物半導體鰭切效電晶體之轉移特 1329926 性’說明本發明實施例於該轉移特性上’之影響。汲極電流 ID係被顯示於y軸上當做χ軸上閛極對源極電壓vgs之函 數。238處之曲線顯示具有當作閘極物質之未摻雜通道及多 晶矽之正通道金屬氧化物半導體鰭式場效電晶體之轉移特 性(如傳統平面正通道金屬氧化物半導體短通道裝置將呈現 =238之類似曲線)’而24〇處之曲線顯示具有當作開極物 質之未摻雜通道及多晶矽之負通道金屬氧化物半導體鰭式 場效電晶體之轉雜性(如傳統平面貞通道金屬氧化物二 麵通道裝置將呈現如施之類似曲線)。先前技術互補金 屬氧化物半導體裝置之兩組曲線238及240係於約⑽祕 至1.00E-06之汲極電流ID (見區域242)處之〇問極對源極 電壓VGS處交又。具優點地,依據本發明實施例,因為作 用函數係使用閘極物質厚度做調整’所以轉移函數曲線可 f諧調於244戶斤示赚-12至1.00E-K)之沒極電流ID處 父叉。例如’因為此大大降低如互補金屬氧化物半導體 S曰曰體被形成其巾’亦包含其他Μ觀元件之全 路功率消耗,所以嶋·Π之電晶Μ閉電流(off·瞻ent) =某些互補金屬氧化物半導體裝置之i施_5關閉電流 為佳。若功率消織降低,縣電晶體·於如手機,個 人數位助理(PDA)_上约腦之行動應財,則行 具優點地不需充電而可於待機模0操作更長。』 依據在此進-步說明之本發明實施例,閘極 參數係可觀變翻_物歧 半導$ 及負通道金屬氧化物半導體電晶體之作用^數+導體 22 1329926 在此被併入參考之Lin,R等人於_E電子裝 2002年1月第23冊第1部49·51頁文獻標題,,互補金屬 化物半導财置㈣綱之可輕侧函數技術,,中, 示以氮植入鉬,發現些微轉移包含錮之閘極作用函數:秋 而,因為氮植入會降低通常由低能量及劑量形成之源極^ 汲極區域,所以使用高能量(29keV)及高劑量阳$⑽q之 氮植入為基礎之相當厚_片(㈣A)作用函數轉移,係不 足用於具薄鰭之鰭式場效電晶體或三閘極裝置。 接著參考第10目,本發明實施例可藉由將推雜物 352/354植人互補金屬氧化物半導體鳍式場效電晶體裳置 至少-電晶體之金屬閘極32G ’以譜調金制極難36〇作 用函數達成技術優勢。第1G_示本發明另—實施例橫斷 面圖式,其中第二區域318中之負通道金屬氧化物半導體 電晶體籍式場效電晶體作用函數可藉由將摻雜物松⑽ 植入閘極物質320做調整。使用之相似數字係如同先前圖 式中所使用者。 雖然其他作用函數可替代性轉移,但例如係可選擇閑 極物質320/360及掺雜物352/354來達成至少2〇〇mV之作 用函數轉移。同時’其他實施射,閘極植入所使用之推 雜物係包含用來形成多閘極裝置之源極及沒極區域(第⑴ 圖無圖式;見第14圖中之源極區域3_及汲極區域 職)。例如’ _摻雜人處糖储有如时形成源極 ^及極區域308b & 308c之植入處理般之低能量及低劑 量,所以閘極植入並不會過度補償源極及汲極區域3〇8b及 23 1329926 308c植入處理。
再次參考第10圖,一實施例中,閘極物質320較佳包 含氮矽化鈦,且如第二區域318中之負通道金屬氧化物半 導體電晶體之至少一電晶體係被植入包含矽之摻雜物 352/354。其他實施例中,閘極物質32〇較佳包含氮矽化鈦, 氮化鈦,氮化组,组,釕,翻,氮化給,鎢,銘,釘,氮 化釕,氮矽化鈕,NiSix,CoSix,TiSix,銥,γ,鉑,鈦, 鈦化鉑,妃,銖,铑,鈦,給,錯,氮鋁化鈦,鉬,氮化 钥,氮石夕化鍅,氮化錯,氮化給,氮石夕化铪,氮化鶴,錄, 镨,氮化釩,鎢化鈦之硼化物,磷化物或銻化物,部份矽 化物質,完全矽化物質(FUSI),及/或其組合物。植入至少 一閘極物質320之摻雜物352/354較佳包含矽,硼,砷,磷, 碳,鍺或銻或其組合。
某些實施例中,因為氮植入通常過大且可能不利影響 源極及汲極區域(見第4圖中之區域3〇8b及3〇8旬,所以摻 雜物352/354較佳包含如非氮之物質。較佳是,植入摻雜物 3S2/3M植人處理之獻織及功料級倾如形成源極 及沒極區域3_及施之植人處理弱或不強,而不過度 麵源極308b及沒極308c區域植入處理。例如某些實施 例中’相同摻雜物係可植入被用來形成源極獅及沒極 308c區域之閘極物質mo。 再參考第1G圖’閘極物質32G被配置於第-區域317 及第二區域318上之後,幕罩现係於第-區域317上形 成。例如’幕罩350可於第一區域317及第二區域318上 24 1329926 ,成,且接著從第二區域318被移除,如,幕罩35〇可 包含-層光致抗钱劑或包含絕緣體之硬幕罩。 352 第二區域318中之閘極物質係被植入摻雜物 。幕罩350可於植人處理期間保護第—區域317中之間 極物質。閘極物質·係於第二區域318中改變,且可包 含遍及閘極物質320之摻雜物352分級密度。例如,閉極
物質可包含較接近埋入絕緣層施下表面或韓應 側面處為高之閘極物質上表面處之捧雜物352密度。 某些實施例中,第一區域317及第二區域318中1閘 極物質320係可被植入第一等級換雜物。接著,例如第一 區域317被遮罩’而第二區域318中之間極物質係被 植入附加摻雜量,以設定與第一區域317中之第一等級換 雜物不同之第二區域318中之第二等級摻雜物。
•=實施例中’如354所示,植入處理係較佳以一角度 被引導朝向件302。例如’雖然其他角度可替代被使用, 但該角度較佳包含與工件3G2上表面(其可為Q度)呈約% 至60度之-角度,如,雖然鰭3〇8可能包含相當高方向 比,但轉動植入絲354方向角度係有助於沿著韓通側 壁將摻雜物354植入閘極物質320。 某些實施例中,工件302係被旋轉若干次,而被一角 度引導之植入處理354係被重複將閘極物質36〇各側植入 於鰭308上。例如,工件302被第一次植入,則工件观 被選轉90度。工件302被第二次植入,則工件3〇2再被選 轉9〇度。某鍊關巾,场齡難人及_以植入間 25 極物質遍所有側壁,如包含四植入處理及三 例如其他實施例中,閘極物質36〇至 麵被植入較鰭姻另—側壁為高密度之摻雜^ 質入牛驟·^ U 旋轉’且具有-單推雜物 ft驟。:替代疋’例如工件搬僅可於執行第二摻雜 植入處理之耵被旋轉一次。例 ” ㈣如㈣物可被植入於鰭狀 、,,。構弟-側壁’而非雜結構第二侧壁上。 接著說明植入摻雜物調整作用函數之實驗結果。沉積 包含具有約25至3G%初始發密度之25g埃厚度之氮石夕化欽 之閘極物質。表1顯示具約中間隙等級(4 65ev)之對稱作用 函數及6不同翻裝置之互補金屬氧化物半導_式場效 電晶體處理:
裝置類型 正通道金屬氧化物半導 體高效能 0.3E15cm-2 4.85eV
質矽附加劑量作用函數
HfSiO 26 —~~~效能 _ ----—. ~———_ 表1 例如 、音人s L3二氧切7介電質之閘極介電質之正通 I屬氧化物半導财貞正通道金屬氧化物半導體裝置, Γ看到因植人紐改變所產生對侧函數最大影響之最 成功結果。
第11圖係為依據本發明—實施例具有各閘極物質於石夕 各摻雜等級之各類電晶體震置之氮石夕化鈦作用函數圖式。 —圖所示物@元件數量圖式 第u圖中之元件數量 閘極物質 370 372 374 376 氮矽化鈦 —--------- 氮化鈦 ---- 氮妙化鈦 氮化鈦 閘極介電物質 氧化發 .氧化矽
ΗίΌ'
第12圖顯示植入三閘極電晶體裝置之本發明一實施例 橫斷面圖式。此實施射,硬幕罩並列於絕緣層上覆石夕 基板402之半導體物質408第二層上表面上,或硬幕罩可 替代地於半導體物質408第二層被模製形成韓狀結構顿 之後被移除。此實施例中,各電晶體係包含鰭狀結構4〇8 上之三個第一閘極。第一閘極係被配置於鰭狀結構4〇8第 一側壁上,其中第二侧壁面對著相同鰭狀結構4〇8之第一 27 1329926 側壁。第三閘極係被配置於各鯖狀結構倾之上表面上。 例如’鰭狀結構408可當作第一區域417及第二區域· 中之電晶體通道。例如參考第U5g|,及第6及7圖, 閘極420可具有藉由閘極厚度諧調之作用函數,或閘極4如 可替代地具有藉由不同摻雜等級將摻雜物植入第一區域 417 ’第二區域418或第一區域417及第二區域418兩者中 諧調之作用函數。 如第13圖所示,接著繼續處理半導體裝置,其顯示依 據本發明實施例形成上金屬化及絕緣層於鰭式場效電晶體 裝置上之後包含多閘鰭式場效電晶體裝置之一半導體裝置 3〇〇。第14圖顯示垂直於第13圖所示圖式之第13圖所示 鰭式場效電晶體裝置鰭結構圖式。 如第14圖所示,鰭狀結構3〇8部件可被植入摻雜物以 形成源極區域308b及汲極區域308c。例如,第14圖所示 亦可看到被配置於源極區域308b及汲極區域3〇8c間之通 道308a圖式。例如某些實施例中,形成源極及汲極區域3〇肋 及308c之植入步驟係可替代地於在此說明之製造處理步驟 之釦發生。弟14圖亦顯示包含如氧化物,氮化物或其組合 之絕緣物質之隔墊394,係可形成於閘極324/320及硬幕罩 310/312/314側壁上。絕緣及傳導層係可形成於如絕緣層384 及390之互補金屬氧化物半導體鰭式場效電晶體或三閘極 電晶體。 接頭386a(第13圖)可提供電子接觸多閘極裝置之閘 極,如與形成於半導體物質324上之矽化物質3幻接觸。 28 1329926 同樣地,接頭386b(第14圖)可提供經由形成於源極3〇8b 上之石夕化物382電子接觸源極3〇8b,而接頭386c可提供經 由形成於汲極308c上之矽化物382電子接觸汲極3〇8c。 rig yju ……a〜'个/曰夕风汉保教於絕緣物質及可電
子接觸接頭386a,386b及386c如導線388a,388b及388c 之接頭上表面上。接合塾(無圖式㈣彡成於接社,而複數 半導體裝置300接著分隔為各晶粒。例如,該接合塾可連 接至積體電路封裝(亦無圖式)或其他晶粒之導線,以提供電 子接觸半導體裝置300之多閘極電晶體。 八
一實施例中,多閘極電晶體較佳包含第一區域317中 之正通道金屬氧化物半導體電晶體及第二區域318中之負 通道金屬氧錄半導體電晶體。依據本㈣實施例,較佳 是正通道金屬氧化物半導體電晶體中之閘極物f 32〇係較 負通道金屬氧化物半導體電晶體中者為厚,或間極物質32〇 較佳於㈣道金屬氧化解導體電晶體包含較正通道金屬 半導體電晶體中為高之推雜密度。一實施例中,閉 ,物質320厚度或閘極物質32〇掺雜等級,係使正通道金 屬乳匕物半導體電晶體之閘極物質具有約《8研之作用函 ί間Γ吏Μ道金屬氧化物半導體電晶體 = 道金屬氧化物半導體電晶體間極之作用函= 〇 至4.解,而正通道金屬氧化物半導體電曰體門 極之作用函數較佳包含約4.2至4 : ¥體電曰曰體閘 雖然門檻電壓可替代地包含其他電鲜級,如纟^例^ 29 1329926 至約15V之對稱Vt值’但電晶體12〇及122較佳分別具有 約+0.3及一0.3V之實質對稱門檻電壓。 ’、 本發明實施例可_若干不衫_電晶體裝置應用 之技術優勢。例如,本發明實施例可實施於負通道金屬氧 化物半導體高效能(HP)裝置,貞通道金屬氧化物半導體低 操作功率(LOP)褒置,負通道金屬氧化物铸體低待機功率 (LSTP)裝置’正通道金屬氧化物半導體高效能農置,正通 道金屬氧化物半_低操作功率裝置,正通道金屬氧化物 半導體低待機功率裝置。這些在此被併入參考之高效能裝 置’低操作功钱4 ’低待機功轉置參數,係於半導體 國際技術發展進程(ITRS)2002年版中定義。較佳是,依據 本發明某些實_ ’ -_所钱置(如貞通道金屬氧化物 半導體或正通道金屬氧化物半導體)係具有相同推雜等級, 但可依據如高效能裝置,低操作功率裝置,低待機功率 置之裝置類型具有不關極層厚度。例如,可選擇但不二 疋需要附加植入處理。 ' 第15至17圖說明以如低待機功率,低操作功率或言 效能之裝置_為基礎纽魏人肺達到預 : 性。例如’第I5圖顯示依據本發明一實施例包含最適用於 低待機功率裝置之量之雜植人負通道金屬氧化物轉體 閘極具有100埃厚度之一氮魏鈦閘極物質之一低待 率互補金屬氧化物半導體三閘極裝置之測量轉移特性。該 圖式係觸具有未摻雜通道及多晶奴正通道金屬氧化物/ 半導體電晶體及負通道金屬氧化物半導體電晶體做計算, 30 1329926 當作正通道金屬氧化物半導體電晶體及負通道金屬氧化物 半導體電晶體之各兩汲極對源極電壓(¥1)幻之閘極物質。 538a處之曲線顯示正通道金屬氧化物半導體電晶體之1 2V 沒極電麗(Vd)處之閘極對源極電壓等級(VGS)範圍之汲極 電流(ID),而538b處之曲線顯示正通道金屬氧化物半導體 電晶體之0.05V沒極電壓處之沒極電流vs閘極對源極電壓 等級。540a處之曲線顯示負通道金屬氧化物半導體電晶體 之1.2V ’及極電壓處之汲極電流v s閘極對源極電壓等級, 而54〇b處之曲線顯不負通道金屬氧化物半導體電晶體之 0.05V ;及極電壓處之汲極電流vs閘極對源極電壓等級。例 如,曲線538a及54〇a,538b及54〇b係於區域544中约 1.00E 11之;及極電流ij)處之〇閘極對源極電壓等級處交叉。 ,第16圖顯示依據本發明一實施例高效能互補金屬氧化 物半導體三祕裝置之測量轉移雜,包含具有正通道金 屬氧化物半導體約施埃厚度及負通道金屬氧化物半導體 約75埃厚度之氮石夕化鈦閘極物質。負通道金屬氧化物半導 體裳置閘極物質係被植人最適用於高功率裝置之密度下之 石夕。638a處之崎顯示正通道金屬氧化物半導體電晶體之 uv汲極電壓處之沒極電流vs間極對源極賴等級,而 挪處之曲線顯示正通道金屬氧化物半導體電晶體之 0.05V沒極賴處之汲極電流vs 對源極電壓等級。输 ^之曲線顯示負通道金屬氧化物铸體電晶體之W沒極 電壓處之秘電流v.s __極電_級,而祕處之 曲線顯示負通道金屬氧化物半導體電晶體之〇〇5v汲極電 31 1329926 壓處之沒極電流v.s閘極對源極電壓等級。例如,曲線638a 及640a,638b及640b係於區域644巾約i 〇㈣至工施_9 之汲極電流ID處之〇閘極對源極電壓等級處交又。
第17圖顯示依據本發明一實施例低操作功率互補金屬 氧化物半導體三閘極裝置之測量轉移特性,包含具有正通 道金屬氧化物半導體約·埃厚度及負通道金屬氧化物= 導體約75埃厚度之氮純鈦閘極物質。負通道金屬氧化物 半導體裝置閘極物質係被植入最適驗低操作功率裝置之 密度下之㊉。738a處之#_示正通道金屬氧化物料體 電晶體之1.2V祕電壓處之祕電流vs閘極對源極電壓 等級’而738b處之曲線顯示正通道金屬氧化物轉體電晶 體之0.G5V _電壓處之祕電流vs閘極對源極電壓等 級。740a處之曲線顯示負通道金屬氧化物半導體電晶體之 1.2V汲極電壓處之汲極電流vs閘極對源極電壓等級,而 740b處之曲線顯示負通道金屬氡化物半導體電晶體之 0.05V汲極電壓處之汲極電流vs閘極對源極電壓等級。例 如,曲線738a及740a,738b及740b係於區域744中約 1.00E-10之汲極電流Π)處之〇閘極對源極電壓等級處交又。 因此,如第15-17圖顯示及在此說明,依據本發明實施 例,多閘極互補金屬氧化物半導體閘極物質之摻雜植入等 級及厚度係可針對正通道金屬氧化物半導體及負通道金屬 氧化物半導體電晶體做調整,以達成互補金屬氧化物半導 體之轉移特性及預期效能。 包3互補金屬氧化物半導體多閘極裝置之最新半導體 32 1329926 •裝置’具有包含—金屬之正通道金4氧化物半導體及負通 運金屬氧化物半導體裝置,係依據本發明實施例形成。本 發明較佳實施例優點係包含提供製造半導體裝置廳, 200 ’ 300及400之方法及其結構。分獅成於第一區域 117 ’ 217 ’ 317 及 417 及第二區域 118,218,318 及 418 中 •之夕閘極正通道金屬氧化物半導體及負通道金屬氧化物半 籲 冑體電晶體係較佳具有-實質對稱Vt。例如,Vtp約為— 0.3V ’而Vtp可為實質相同正值,如約+〇3v。例如,金屬 ,極層厚度及/或雜植人等級係可建立多閘極正通道金屬 氧化物半導體及負通道金屬氧化物半導體裝置閘極物質之 作用函數。依據本發明實施例,正通道金屬氧化物半導體 或負通道金屬氧化物半導體電晶體或兩者之閘極物質厚 度,閘極物質摻雜植入等級係可用來調整正通道金屬氧化 物半導體及負通道金屬氧化物半導體電晶體之作用函數。 • 雖然已詳細說明本發明實施例及其優點,但應了解只 要不背離附帶申請專利所定義之發明精神及範轉,在此均 可做各種改變及替代。例如,熟練技術人士很容易瞭解在 此說明許多特性,功能,處理及物質均可改變而仍保持於 本發明範圍内。再者,本應用範圍不預期受限於說明書中 說明之處理,機器,製造,事務組合,裝置,方法及二驟 之特定實施例。雖然熟練技術人士之一很容易從本發明揭 示瞭解’可執行與在此說明對應實施例實質相同功能或結 杲原本存在或稍後發展之處理,機器,製造,事務組合, 裝置,方法及步驟特定實施例亦可依據本發明做使用。於 33 1329926 是,附帶申請專利範圍係預期包含於如處理,機器,製造, 事務組合,裝置,方法或步驟之其範圍内。
34 1329926 【圖式間單說明】 為了更完整理解本發其優點,現在參考以下說明及 附圖,其中: _示依據本發明較佳實施例於各製造階段處
梦署勺人、置&斷面圖式’其中—互補金屬氧化物半導體 有不同閘極物質厚度之多閘極正通道金屬氧化 物料體電晶體及負通道金屬氧化物半導體電晶體; 第6及7圖顯示依據本發明一實施例另一製造包含多問 具林_域質厚度之—互補金屬氧化物半 V體裝置之方法橫斷面圖式; 第8圖為顯示依據本發明實施例閘極介質物質若干類型 及厚度之作用函數圖式; 第9圖顯示具有#作_物質之未摻雜通道及多晶石夕之 正通道^屬氧化辨導職晶體及負通道金屬氧化物半導
體《式暴放電a曰體轉移特性,描述本發明實施例對鰭式場 效電晶體互補金屬氧化物半導體裝置轉移特性之影響; 第10圖顯示本發明另一實施例橫斷面圖式,其中負通道 金屬乳化物半導體電晶體作用函數可藉由將摻雜物植入該 閘極類型做調整; 第11圖為依據本發明—實施例具有各雜物質於石夕各摻 雜等、·及之各類電晶體裝置之氮石夕化鈦(TiS iN)作用函數圖 式; 第12圖顯喊人二_電晶體裝置之本發明—實施例橫 斷面圖式; 35 第f圖顯示依據本發明實施例形成上金屬化及絕緣層於 Μ式場效電晶體裝置上之後之―,喊場效電晶體裝置; 第14圖顯示垂直於第13圖所示圖式之第13圖所示鰭式 場效電晶體裝置鰭結構圖式; 第15圖顯示依據本發明一實施例包含矽被植入負通道金 屬氧化物半導體閘極之-氮石夕化欽閘極物質之-低待用功 率(L S ΤΡ)互補金屬氧化物半導體三閘極裝置之測量轉 φ 性; 第16圖顯不依據本發明一實施例包含矽被植入負通道金 屬氧化物半導體閘極之-氮石夕化鈦閘極物質之-高效能 (HP)互補金屬氧化物半導體三閘極裝置之測量轉移特性; 及 第17圖顯示依據本發明一實施例包含矽被植入負通道金 屬氧化物半導體閘極之一氮矽化鈦閘極物質之一低操作功 率(LOP)互補金屬氧化物半導體三閘極裝置之測量轉移特 • 性。 除非另有標示,否則對應不同圖式中之數字及符號大致 意指對應部件。該圖式係清楚說明較佳實施例相關特徵且 不必定標描續'。 【主要元件符號說明】 100、200、300、400半導體裝置 102、302 工件 36 1329926
106、306、384 絕緣層 116 > 216 閘極介電質 117、217、317、417 第一區域 118、218、318、418 第二區域 120 > 320 閘極物質 122'230 ' 350 幕罩 208 > 308 鱗式結構 220a 第一閘極物質 220b 第二閘極物質 308a 通道 308b 源極區域 308c 没極區域 352 ' 354 掺雜物 382 矽化物 386a、386b、386c 接頭 388a ' 388b ' 388c 導線 394 隔墊 402 $夕基板 420 閘極 104、108、124、224、324、408 半導體物質 110、112、114、210、212、214、310、312、314 硬幕罩 37
Claims (1)
1.329926 > U (l· 、申請專利範圍·· ' 1 一種半導體裝置,包含. -第二電晶體,其接厚度;及 包含至1晶體,料二電晶纟
-閑極中的每—個僅具有^至乂兩; 極具有-第二厚度,該第一厚=該至少兩第1 中該半導體穿置勺人 度大於該第二厚度1 其中該第=:ΐ補金屬氧化物半導體裝置, 晶體,該第二電日=人正,金屬氧化物半導體雙 電晶體,其中^厚氧化物半導體 -第-作用函數其==少兩第-間極的 二_的—第用二—厂係建立該至少兩第 詨第-你田第乍 而其中該第二作用函數盘
^雷^ 獨,以提供該第—電晶體的一第一 =電壓與該第二電晶體的—第二門檀觀之 體其:該至少兩第一閘極包含鄰近該第一電晶 、閘極介電質的一第一金屬閘極材料及該至少兩 =一間極包含鄰近該第二電晶體的該_介電質的— 弟-金屬閘極材料’該第一金屬閘極材料與該第二金 f閘極材料為相_物質並包含氮魏鈦,'氮化:、, 鼠化纽’包,釕,氮化給’鎢’銘’舒氮化釕氮 ,化纽’贿,,〇^,服,银,¥,翻,欽,欽化 •’鈀’錁,錄,鈦,給,錯,氮叙化鈦,銷,氮化 38 2. 鉬’氮矽化錘’氮化锆,氮化铪,氮矽化铪,氮化鎢, 錄,鐯’氮化釩’鎢化鈦之硼化物,磷化物或銻化物, 部份其石夕化物質’完全其矽化物質,及其組合物的其 中之一。 如申請專利範圍第1項的半導體裝置,其中該第一厚 度係大於該第二厚度約50埃或更多。 3.
如申請專利範圍第1項的半導體裝置,其中該第一厚 度係包含約5GG埃或更少,而其巾該第二厚度係包含 約100埃或更少。 4. 一種半導體裝置,包含: -第-電晶體,該第一電晶體包含至少兩第一閘極, 該至少兩第-閘極具有一第一摻雜等級;及
第-電阳體’其接近該第—電晶體,該第二電晶體 包含至少兩第二閑極,該至少兩第二間極具有一第二 擦雜等級,該第二摻雜等級與該第一推雜等級不同, Ϊ中至少該第二摻雜等級之—摻雜物包含非氮之物 ^且是植人角度導致該第—摻雜等級及/或該第二摻 ”級,其中該第一換雜等級係建立該至少兩第-閘 作用函數,其中該第二摻雜等級係建立該 用I數盘;:極的一第二作用函數,而其中該第二作 的作用函數不同,以提供該第一電晶體 nr與該第二電晶體的-第二_ 之間的-對稱性,且該至少兩第一閉 材料及該至少兩第H 的金屬閘極 3極的一金相極材料包含氮石夕 39 化鈦’氮化鈦’氮化鈕’鈕,釕,氮化铪,鎢,鋁, 釕’氮化釕,氮矽化鈕,NiSix,coSix,TiSix,銥,γ, 銘,鈦’鈦化鉑’鈀,銖,铑,鈦,給,锆,氮鋁化 欽’麵’氮化銦,氮石夕化錄,氮化錄,氣化給,氣石夕 化铪,氮化鎢’鎳’镨’氮化釩,鎢化鈦之硼化物, 磷化物或銻化物,部份其矽化物質,完全其矽化物質, 及/或其組合物。 如申請專利範圍第4項的半導體裝置,其中該第一電 晶體係包含一正通道金屬氧化物半導體電晶體,其中 »亥第一電明體係包含—負通道金屬氧化物半導體電晶 體,而其中該第二摻雜等級係大於該第—掺雜等級。 如申請專利範圍第4項的半導體裝置,其中該第一電 晶體係包含-正通道金屬氧化物半導體電晶體,其中 該第二電晶體係包含-負通道金屬氧化物 體’其中該第-摻雜等級係無包含_摻雜物植入。 如申請專利翻第4項的半導體《置,其中該至少第 二摻雜等級之-摻雜物係包切1、坤 鍺、銻或其組合。 如申請專利制第4項的轉體裝置,巧 ,體包含至少-第-鰭狀結構’其中該至少兩第一閑 =該= 的-第-側壁及- ::於該至少-第,構:該第 =:側! 中該至少一第包蝴-電晶體的-通 道-其中該第二電晶體包含至少一第二鰭狀結構,其 中該至少兩第二閘極係配置於該至少一第二鰭狀結構 的一第—侧壁及一第二側壁上,而該至少一第二鰭狀 結構的該第二側壁係位於該第—側壁對側,其中該至 9. > 一第一鰭狀結構係包含該第二電晶體的一通道。 ^申請專利細第8項的轉體裝置,射該第二電 日日體的該至少一第二鰭狀結構第一側壁上該第二間極 的一摻雜輪扉係與該至少一第二鰭狀結構第二側壁上 的一摻雜輪廓不同。 10.利範圍第:項的輸裝置其中該第二電 搞的第―11狀結構的第—側壁上該第二閘 雜輪廓係與該至少一第二鰭狀結構的第二侧 u二由二Ϊ—間極的一摻雜輪廓實質相同。 3=圍第8項的半導體裝置,其中該第-換 該摻雜物ur電;c雜等級係包含 至 及 少-第二鰭狀結構中之=二源極區域及形成於該至 -源極區域、該第—㈣J—秘區域,而其中該第 第二沒㈣域係包含該摻雜:、轉二源極區域及該 一種半導體裝置製造方法,包含. 形成一第一電晶體,該 極,該至少兩第一閉極電晶體包含至少兩第一閘 〃有一第一參數;及 41 12.
形成接近該第一電晶體的一第二電晶體,該第二電晶 體包含至少兩第二閘極’該至少兩第二閘極具有一第 二參數,該第一參數係包含一第一摻雜等級,且該第 二參數係包含一第二摻雜等級’其中該至少兩第一閘 極的一金屬閘極材料及該至少兩第二閘極的一金屬閘 極材料包含氮發化鈦,氮化鈦,氮化叙,组,釕,氮 化給,鶴,紹,釕,氮化舒,氮石夕化組,NiSix,CoSix, TiSix,銥,γ,始,鈥,鈦化叙,把鍊,錢欽,給, 鍅,氮鋁化鈦,鉬,氮化鉬,氮矽化鍅,氮化錯,氮 化銓氮石夕化給,氮化鶴,鎳,錯,氮化叙,鶴化欽 之硼化物,磷化物或銻化物,部份其矽化物質,完全 其石夕化物質,及/或其組合物,其中將該捧雜物植入該 至少兩第二閘極的該金屬閘極材料包含植入石夕、侧、
Γ!:、鍺、綈或其組合,其中該第二參數與該 苐一參數不同,以提供該第—電晶體的—第 壓與該第二電晶體的-第二門檻電壓之間的一ς =,且其中形成該第-電晶體及形成該g 含:導趙物質之複數轉上形成-間極= 13 第二電晶體的該閉極物質質*將一換雜物植入該 如:請專利範圍第12項的方法,其中該第 -第-厚度’且其中該第二夂 ;數包含 14.如申請專利範圍第13項的方法,Γ成該第:厚電度曰° 形成該第二電晶體之前進一步包含.電晶體及 42 ^329926 提供-工件,該工件包含具有一基板之一絕緣層上覆 石夕基板、配置於該基板上的一埋入絕緣層、及配置於 該埋入絕緣層上的-層半導體物質,該工件包含一第 一區域及一第二區域; 分別於該第-區域及第二區域的該層半導體物質内形 成至少-第-鰭狀結構及至少一第二趙狀結構,各該 至少=第-鰭狀結構及各該至少一第二縛狀結構係包 含一第一侧壁及一對側第二侧壁;及 於該至少-第-韓狀結構及該至少一第二簿狀結構的 ίΪΓ及第二側壁上形成―閘極物質,其中形成該第 、曰體係包含於該第—區域中的該閘極物質上形成 該至少兩第一閘極,Α中兮卜 -第:::電: 極=!二電晶體係包含於該第二區域中的該間 門極亀兩第二閘極’其中該至少兩第二 =電:物質及該至少一第二鰭狀結構係包含該 15.如申請專利範圍第14項的方法其中 體=成該第二f晶體係包含树祕 沉= -第-閘極物質,及從該第二電 份該第—閘極物質。 矛' 夕一邛 16.如申請專利範第】5 電晶體 上移除至少一部份該第一 一 .㈣方法射從該第. 閘極物質係包含從該第二電 進一步包含於至少 晶體上移除所有該第-_物質, 43 1329926 該第二電晶體上沉積— 17.如申請專利範圍第16項的方;H 體及形成該第二電曰曰與位^ 八♦形成該第一電晶 二電晶體上沉積一^曰—'、匕含於該第一電晶體及該第 二電晶體、於該第 ^物質、以—幕罩遮蓋該第
及該幕罩。第一電晶體上移除該第二間極物質 18.如申請專利範圍第12項 ::電晶體的該閘極物質係包含以:== 19.
第Μ項的方法’其中各該複數鰭係包 :第-側壁及位於該第一側壁對側的一第二側壁, 兮植入料二電晶體的該閘極物質摻雜物係包含將 该摻雜物植人該魏_—第—趣上,而非該複數 鰭的該第二側壁上。 20.如申請專利範圍第18項的方法,進一步包含旋轉該半 導體裝置’並以該角度重複植入該摻雜物。 儿如申請專利範圍第12項的方法,進一步包含在將該推 雜物植入該閘極物質之前,藉由將該摻雜物植入該複 數鰭以於各該複數鰭中形成一源極區域及一汲極區 域’其中將該掺雜物植入該複數鰭係包含該摻雜物的 一第一劑量及一第一能量等級,其中將該摻雜物植入 該閘極物質係包含該摻雜物的一第二劑量及一第二能 量等級’其中該掺雜物的第二劑量小於該掺雜物的第 44 1329526 一劑量,而該第二能量等級小於該第一能量等級。
45
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/240,698 US8188551B2 (en) | 2005-09-30 | 2005-09-30 | Semiconductor devices and methods of manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200742068A TW200742068A (en) | 2007-11-01 |
TWI329926B true TWI329926B (en) | 2010-09-01 |
Family
ID=37551811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095135441A TWI329926B (en) | 2005-09-30 | 2006-09-25 | Semiconductor devices and methods of manufacture thereof |
Country Status (5)
Country | Link |
---|---|
US (3) | US8188551B2 (zh) |
EP (3) | EP1770789A3 (zh) |
JP (2) | JP4996903B2 (zh) |
KR (1) | KR100911743B1 (zh) |
TW (1) | TWI329926B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10229853B2 (en) | 2013-09-27 | 2019-03-12 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100679704B1 (ko) * | 2005-01-10 | 2007-02-06 | 한국과학기술원 | 분자소자와 바이오 센서를 위한 나노갭 또는 나노 전계효과 트랜지스터 제작방법 |
KR100724560B1 (ko) * | 2005-11-18 | 2007-06-04 | 삼성전자주식회사 | 결정질 반도체층을 갖는 반도체소자, 그의 제조방법 및그의 구동방법 |
US7968394B2 (en) * | 2005-12-16 | 2011-06-28 | Freescale Semiconductor, Inc. | Transistor with immersed contacts and methods of forming thereof |
US7414290B2 (en) * | 2006-06-23 | 2008-08-19 | Intel Corporation | Double gate transistor, method of manufacturing same, and system containing same |
US20080029827A1 (en) * | 2006-08-04 | 2008-02-07 | Ibrahim Ban | Double gate transistor, method of manufacturing same, and system containing same |
US7378713B2 (en) * | 2006-10-25 | 2008-05-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with dual-metal gate structures and fabrication methods thereof |
US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
US7812414B2 (en) * | 2007-01-23 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates |
US20080237751A1 (en) * | 2007-03-30 | 2008-10-02 | Uday Shah | CMOS Structure and method of manufacturing same |
US8124483B2 (en) * | 2007-06-07 | 2012-02-28 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US7915681B2 (en) * | 2007-06-18 | 2011-03-29 | Infineon Technologies Ag | Transistor with reduced charge carrier mobility |
JP4459257B2 (ja) * | 2007-06-27 | 2010-04-28 | 株式会社東芝 | 半導体装置 |
JP2009094227A (ja) * | 2007-10-05 | 2009-04-30 | Fujitsu Ltd | nチャネルMOSトランジスタおよびその製造方法、半導体装置 |
JP5410666B2 (ja) | 2007-10-22 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
TWI355069B (en) * | 2007-11-06 | 2011-12-21 | Nanya Technology Corp | Dram device |
US20090206405A1 (en) * | 2008-02-15 | 2009-08-20 | Doyle Brian S | Fin field effect transistor structures having two dielectric thicknesses |
US8536660B2 (en) * | 2008-03-12 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates of MOS devices |
US7781274B2 (en) * | 2008-03-27 | 2010-08-24 | Kabushiki Kaisha Toshiba | Multi-gate field effect transistor and method for manufacturing the same |
JP4518180B2 (ja) * | 2008-04-16 | 2010-08-04 | ソニー株式会社 | 半導体装置、および、その製造方法 |
US8753936B2 (en) * | 2008-08-12 | 2014-06-17 | International Business Machines Corporation | Changing effective work function using ion implantation during dual work function metal gate integration |
US8148776B2 (en) * | 2008-09-15 | 2012-04-03 | Micron Technology, Inc. | Transistor with a passive gate |
US20100102393A1 (en) * | 2008-10-29 | 2010-04-29 | Chartered Semiconductor Manufacturing, Ltd. | Metal gate transistors |
US8330170B2 (en) * | 2008-12-05 | 2012-12-11 | Micron Technology, Inc. | Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods |
US8278691B2 (en) * | 2008-12-11 | 2012-10-02 | Micron Technology, Inc. | Low power memory device with JFET device structures |
US8252649B2 (en) * | 2008-12-22 | 2012-08-28 | Infineon Technologies Ag | Methods of fabricating semiconductor devices and structures thereof |
JP2010199161A (ja) * | 2009-02-23 | 2010-09-09 | Renesas Electronics Corp | 半導体集積回路装置及びその製造方法 |
US7871873B2 (en) * | 2009-03-27 | 2011-01-18 | Global Foundries Inc. | Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material |
US8110467B2 (en) | 2009-04-21 | 2012-02-07 | International Business Machines Corporation | Multiple Vt field-effect transistor devices |
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US8101486B2 (en) | 2009-10-07 | 2012-01-24 | Globalfoundries Inc. | Methods for forming isolated fin structures on bulk semiconductor material |
US20110147804A1 (en) * | 2009-12-23 | 2011-06-23 | Rishabh Mehandru | Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation |
US9922878B2 (en) * | 2010-01-08 | 2018-03-20 | Semiconductor Manufacturing International (Shanghai) Corporation | Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing |
US20120049281A1 (en) * | 2010-08-27 | 2012-03-01 | Toshiba America Electronic Components, Inc. | Semiconductor device with effective work function controlled metal gate |
US9012283B2 (en) * | 2011-05-16 | 2015-04-21 | International Business Machines Corporation | Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture |
KR101850703B1 (ko) * | 2011-05-17 | 2018-04-23 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US8597994B2 (en) | 2011-05-23 | 2013-12-03 | GlobalFoundries, Inc. | Semiconductor device and method of fabrication |
US8735987B1 (en) | 2011-06-06 | 2014-05-27 | Suvolta, Inc. | CMOS gate stack structures and processes |
US8969154B2 (en) * | 2011-08-23 | 2015-03-03 | Micron Technology, Inc. | Methods for fabricating semiconductor device structures and arrays of vertical transistor devices |
WO2013048417A1 (en) | 2011-09-29 | 2013-04-04 | Intel Corporation | Electropositive metal containing layers for semiconductor applications |
US8569125B2 (en) * | 2011-11-30 | 2013-10-29 | International Business Machines Corporation | FinFET with improved gate planarity |
US8896066B2 (en) | 2011-12-20 | 2014-11-25 | Intel Corporation | Tin doped III-V material contacts |
US9153583B2 (en) * | 2011-12-20 | 2015-10-06 | Intel Corporation | III-V layers for N-type and P-type MOS source-drain contacts |
CN104054181B (zh) | 2011-12-30 | 2017-10-20 | 英特尔公司 | 全包围栅晶体管的可变栅极宽度 |
US9202698B2 (en) | 2012-02-28 | 2015-12-01 | International Business Machines Corporation | Replacement gate electrode with multi-thickness conductive metallic nitride layers |
US9159626B2 (en) * | 2012-03-13 | 2015-10-13 | United Microelectronics Corp. | FinFET and fabricating method thereof |
CN103325683A (zh) * | 2012-03-23 | 2013-09-25 | 联华电子股份有限公司 | 鳍状场效晶体管及其工艺 |
US8673731B2 (en) * | 2012-08-20 | 2014-03-18 | International Business Machines Corporation | Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices |
US8669167B1 (en) * | 2012-08-28 | 2014-03-11 | International Business Machines Corporation | Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices |
JP5717706B2 (ja) | 2012-09-27 | 2015-05-13 | 株式会社東芝 | 半導体装置及びその製造方法 |
US9177820B2 (en) * | 2012-10-24 | 2015-11-03 | Globalfoundries U.S. 2 Llc | Sub-lithographic semiconductor structures with non-constant pitch |
CN103855013A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | N型mosfet的制造方法 |
CN103855007A (zh) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | P型mosfet的制造方法 |
US8946014B2 (en) | 2012-12-28 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device structure and methods of making same |
US9190419B2 (en) * | 2013-02-07 | 2015-11-17 | International Business Machines Corporation | Diode structure and method for FINFET technologies |
KR20140106903A (ko) * | 2013-02-27 | 2014-09-04 | 에스케이하이닉스 주식회사 | 트랜지스터, 이를 구비하는 가변 저항 메모리 장치 및 그의 제조방법 |
US9780212B2 (en) * | 2013-09-18 | 2017-10-03 | Globalfoundries Inc. | Fin width measurement using quantum well structure |
US9219155B2 (en) * | 2013-12-16 | 2015-12-22 | Intel Corporation | Multi-threshold voltage devices and associated techniques and configurations |
US9553171B2 (en) * | 2014-02-14 | 2017-01-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (FinFET) device and method for forming the same |
US9362404B2 (en) * | 2014-02-21 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping for FinFET |
US10546856B2 (en) | 2014-02-25 | 2020-01-28 | Stmicroelectronics, Inc. | CMOS structure having low resistance contacts and fabrication method |
KR102190673B1 (ko) * | 2014-03-12 | 2020-12-14 | 삼성전자주식회사 | 중간갭 일함수 금속 게이트 전극을 갖는 반도체 소자 |
US9590105B2 (en) * | 2014-04-07 | 2017-03-07 | National Chiao-Tung University | Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof |
US9312191B2 (en) * | 2014-08-14 | 2016-04-12 | Globalfoundries Inc. | Block patterning process for post fin |
US10032683B2 (en) | 2015-06-16 | 2018-07-24 | International Business Machines Corporation | Time temperature monitoring system |
KR102350007B1 (ko) | 2015-08-20 | 2022-01-10 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
KR102396085B1 (ko) | 2015-10-28 | 2022-05-12 | 에스케이하이닉스 주식회사 | 매립금속게이트구조를 구비한 반도체장치 및 그 제조 방법, 그를 구비한 메모리셀, 그를 구비한 전자장치 |
US9960273B2 (en) * | 2015-11-16 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure with substrate isolation and un-doped channel |
US9966435B2 (en) * | 2015-12-09 | 2018-05-08 | Qualcomm Incorporated | Body tied intrinsic FET |
US9484347B1 (en) | 2015-12-15 | 2016-11-01 | International Business Machines Corporation | FinFET CMOS with Si NFET and SiGe PFET |
US10256161B2 (en) | 2016-02-17 | 2019-04-09 | International Business Machines Corporation | Dual work function CMOS devices |
US9553031B1 (en) * | 2016-04-01 | 2017-01-24 | Lam Research Corporation | Method for integrating germanides in high performance integrated circuits |
US11121040B2 (en) | 2016-09-30 | 2021-09-14 | Intel Corporation | Multi voltage threshold transistors through process and design-induced multiple work functions |
CN107958872B (zh) * | 2016-10-17 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US10163899B2 (en) * | 2016-11-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Temperature compensation circuits |
CN107195631B (zh) * | 2017-04-24 | 2019-11-12 | 中国科学院微电子研究所 | 一种调节cmos器件阈值的方法及cmos器件 |
CN107195585B (zh) * | 2017-04-24 | 2019-11-12 | 中国科学院微电子研究所 | 一种调节cmos器件阈值的方法及cmos器件 |
CN107180794B (zh) * | 2017-06-14 | 2019-11-12 | 中国科学院微电子研究所 | 一种调节高k金属栅cmos器件阈值的方法和cmos器件 |
CN109087887B (zh) * | 2017-06-14 | 2021-04-02 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
JP6783710B2 (ja) * | 2017-06-22 | 2020-11-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
KR102341721B1 (ko) | 2017-09-08 | 2021-12-23 | 삼성전자주식회사 | 반도체 소자 |
US10510855B2 (en) | 2017-11-14 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor layout to reduce kink effect |
DE102018114750A1 (de) | 2017-11-14 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor-layout zum reduzieren des kink-effekts |
US10468410B2 (en) | 2017-11-15 | 2019-11-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metal gate modulation to improve kink effect |
US11282933B2 (en) * | 2017-11-30 | 2022-03-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET having a work function material gradient |
CN108511392B (zh) * | 2018-01-31 | 2019-11-12 | 中国科学院微电子研究所 | Cmos器件及调节cmos器件阈值的方法 |
CN108428667B (zh) * | 2018-01-31 | 2020-08-04 | 中国科学院微电子研究所 | Cmos器件及其制备方法 |
US11476334B2 (en) | 2018-02-08 | 2022-10-18 | Intel Corporation | Silicide structure of an integrated transistor device and method of providing same |
US11239313B2 (en) * | 2018-10-30 | 2022-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated chip and method of forming thereof |
CN111554679B (zh) * | 2020-04-09 | 2023-03-31 | 中国科学院微电子研究所 | 一种SOI FinFET器件及其制作方法 |
KR20210128534A (ko) * | 2020-04-16 | 2021-10-27 | 삼성전자주식회사 | 반도체 장치 |
US11411180B2 (en) | 2020-04-28 | 2022-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Phase-change memory device and method |
US11482543B2 (en) * | 2020-05-29 | 2022-10-25 | metaMOS Solutions Inc. | Radio frequency (RF) amplifier device on silicon-on-insulator (SOI) and method for fabricating thereof |
Family Cites Families (130)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4432035A (en) * | 1982-06-11 | 1984-02-14 | International Business Machines Corp. | Method of making high dielectric constant insulators and capacitors using same |
US5066995A (en) * | 1987-03-13 | 1991-11-19 | Harris Corporation | Double level conductor structure |
US4990974A (en) * | 1989-03-02 | 1991-02-05 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor |
IT1235693B (it) * | 1989-05-02 | 1992-09-21 | Sgs Thomson Microelectronics | Transistore ad effetto di campo superficiale con regione di source e/o di drain scavate per dispositivi ulsi. |
US5223451A (en) * | 1989-10-06 | 1993-06-29 | Kabushiki Kaisha Toshiba | Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip and method of making it |
JP2921889B2 (ja) * | 1989-11-27 | 1999-07-19 | 株式会社東芝 | 半導体装置の製造方法 |
US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
JPH08153804A (ja) * | 1994-09-28 | 1996-06-11 | Sony Corp | ゲート電極の形成方法 |
US5763922A (en) * | 1997-02-28 | 1998-06-09 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
JP3077630B2 (ja) * | 1997-06-05 | 2000-08-14 | 日本電気株式会社 | 半導体装置およびその製造方法 |
US6777759B1 (en) * | 1997-06-30 | 2004-08-17 | Intel Corporation | Device structure and method for reducing silicide encroachment |
US6013553A (en) * | 1997-07-24 | 2000-01-11 | Texas Instruments Incorporated | Zirconium and/or hafnium oxynitride gate dielectric |
US5994747A (en) * | 1998-02-13 | 1999-11-30 | Texas Instruments-Acer Incorporated | MOSFETs with recessed self-aligned silicide gradual S/D junction |
US6348390B1 (en) * | 1998-02-19 | 2002-02-19 | Acer Semiconductor Manufacturing Corp. | Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source/drain junctions |
JP2000012856A (ja) * | 1998-06-26 | 2000-01-14 | Sony Corp | Mosトランジスタの製造方法 |
US6027961A (en) * | 1998-06-30 | 2000-02-22 | Motorola, Inc. | CMOS semiconductor devices and method of formation |
US6166417A (en) * | 1998-06-30 | 2000-12-26 | Intel Corporation | Complementary metal gates and a process for implementation |
US6130123A (en) * | 1998-06-30 | 2000-10-10 | Intel Corporation | Method for making a complementary metal gate electrode technology |
JP4245692B2 (ja) * | 1998-08-11 | 2009-03-25 | シャープ株式会社 | デュアルゲートcmos型半導体装置およびその製造方法 |
US6204103B1 (en) * | 1998-09-18 | 2001-03-20 | Intel Corporation | Process to make complementary silicide metal gates for CMOS technology |
US6124171A (en) * | 1998-09-24 | 2000-09-26 | Intel Corporation | Method of forming gate oxide having dual thickness by oxidation process |
US6084280A (en) * | 1998-10-15 | 2000-07-04 | Advanced Micro Devices, Inc. | Transistor having a metal silicide self-aligned to the gate |
US6410967B1 (en) * | 1998-10-15 | 2002-06-25 | Advanced Micro Devices, Inc. | Transistor having enhanced metal silicide and a self-aligned gate electrode |
US6911707B2 (en) * | 1998-12-09 | 2005-06-28 | Advanced Micro Devices, Inc. | Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance |
JP3287403B2 (ja) * | 1999-02-19 | 2002-06-04 | 日本電気株式会社 | Mis型電界効果トランジスタ及びその製造方法 |
US6344378B1 (en) | 1999-03-01 | 2002-02-05 | Micron Technology, Inc. | Field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors |
US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
US6159782A (en) * | 1999-08-05 | 2000-12-12 | Advanced Micro Devices, Inc. | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant |
JP2001060630A (ja) * | 1999-08-23 | 2001-03-06 | Nec Corp | 半導体装置の製造方法 |
US6753556B2 (en) * | 1999-10-06 | 2004-06-22 | International Business Machines Corporation | Silicate gate dielectric |
US6861304B2 (en) * | 1999-11-01 | 2005-03-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of manufacturing thereof |
US6373111B1 (en) * | 1999-11-30 | 2002-04-16 | Intel Corporation | Work function tuning for MOSFET gate electrodes |
US6444555B2 (en) * | 1999-12-07 | 2002-09-03 | Advanced Micro Devices, Inc. | Method for establishing ultra-thin gate insulator using anneal in ammonia |
US6448127B1 (en) * | 2000-01-14 | 2002-09-10 | Advanced Micro Devices, Inc. | Process for formation of ultra-thin base oxide in high k/oxide stack gate dielectrics of mosfets |
US6225163B1 (en) * | 2000-02-18 | 2001-05-01 | National Semiconductor Corporation | Process for forming high quality gate silicon dioxide layers of multiple thicknesses |
US6297103B1 (en) * | 2000-02-28 | 2001-10-02 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
WO2001066832A2 (en) | 2000-03-07 | 2001-09-13 | Asm America, Inc. | Graded thin films |
JP2001284466A (ja) * | 2000-03-29 | 2001-10-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6184072B1 (en) * | 2000-05-17 | 2001-02-06 | Motorola, Inc. | Process for forming a high-K gate dielectric |
JP3658342B2 (ja) | 2000-05-30 | 2005-06-08 | キヤノン株式会社 | 電子放出素子、電子源及び画像形成装置、並びにテレビジョン放送表示装置 |
JP2002118175A (ja) | 2000-10-05 | 2002-04-19 | Toshiba Corp | 半導体装置及びその製造方法 |
US20040113211A1 (en) * | 2001-10-02 | 2004-06-17 | Steven Hung | Gate electrode with depletion suppression and tunable workfunction |
US6831339B2 (en) * | 2001-01-08 | 2004-12-14 | International Business Machines Corporation | Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same |
US6436759B1 (en) * | 2001-01-19 | 2002-08-20 | Microelectronics Corp. | Method for fabricating a MOS transistor of an embedded memory |
JP2002237589A (ja) * | 2001-02-08 | 2002-08-23 | Sony Corp | 半導体装置の製造方法 |
US6858865B2 (en) * | 2001-02-23 | 2005-02-22 | Micron Technology, Inc. | Doped aluminum oxide dielectrics |
JP4895430B2 (ja) * | 2001-03-22 | 2012-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2002299610A (ja) * | 2001-03-30 | 2002-10-11 | Toshiba Corp | 半導体装置およびその製造方法 |
KR100399356B1 (ko) * | 2001-04-11 | 2003-09-26 | 삼성전자주식회사 | 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법 |
US6693333B1 (en) * | 2001-05-01 | 2004-02-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator circuit with multiple work functions |
US6740944B1 (en) * | 2001-07-05 | 2004-05-25 | Altera Corporation | Dual-oxide transistors for the improvement of reliability and off-state leakage |
US6794252B2 (en) | 2001-09-28 | 2004-09-21 | Texas Instruments Incorporated | Method and system for forming dual work function gate electrodes in a semiconductor device |
US6475908B1 (en) | 2001-10-18 | 2002-11-05 | Chartered Semiconductor Manufacturing Ltd. | Dual metal gate process: metals and their silicides |
DE60134753D1 (de) * | 2001-11-26 | 2008-08-21 | Imec Inter Uni Micro Electr | Herstellungsverfahren für CMOS-Halbleiter-Bauelemente mit wählbaren Gatedicken |
US6770521B2 (en) | 2001-11-30 | 2004-08-03 | Texas Instruments Incorporated | Method of making multiple work function gates by implanting metals with metallic alloying additives |
JP4265882B2 (ja) | 2001-12-13 | 2009-05-20 | 忠弘 大見 | 相補型mis装置 |
US6653698B2 (en) * | 2001-12-20 | 2003-11-25 | International Business Machines Corporation | Integration of dual workfunction metal gate CMOS devices |
US6696332B2 (en) * | 2001-12-26 | 2004-02-24 | Texas Instruments Incorporated | Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing |
US6563183B1 (en) * | 2001-12-31 | 2003-05-13 | Advanced Micro Devices, Inc. | Gate array with multiple dielectric properties and method for forming same |
US6528858B1 (en) * | 2002-01-11 | 2003-03-04 | Advanced Micro Devices, Inc. | MOSFETs with differing gate dielectrics and method of formation |
US20030141560A1 (en) * | 2002-01-25 | 2003-07-31 | Shi-Chung Sun | Incorporating TCS-SiN barrier layer in dual gate CMOS devices |
US20030151077A1 (en) * | 2002-02-13 | 2003-08-14 | Leo Mathew | Method of forming a vertical double gate semiconductor device and structure thereof |
JP2003273350A (ja) * | 2002-03-15 | 2003-09-26 | Nec Corp | 半導体装置及びその製造方法 |
JP2003282875A (ja) | 2002-03-27 | 2003-10-03 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
KR100487525B1 (ko) * | 2002-04-25 | 2005-05-03 | 삼성전자주식회사 | 실리콘게르마늄 게이트를 이용한 반도체 소자 및 그 제조방법 |
US20030211682A1 (en) | 2002-05-10 | 2003-11-13 | Jenq Jason Jyh-Shyang | Method for fabricating a gate electrode |
US6656764B1 (en) * | 2002-05-15 | 2003-12-02 | Taiwan Semiconductor Manufacturing Company | Process for integration of a high dielectric constant gate insulator layer in a CMOS device |
JP2003347420A (ja) * | 2002-05-23 | 2003-12-05 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6894931B2 (en) | 2002-06-20 | 2005-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
KR100476926B1 (ko) | 2002-07-02 | 2005-03-17 | 삼성전자주식회사 | 반도체 소자의 듀얼 게이트 형성방법 |
US6723658B2 (en) * | 2002-07-15 | 2004-04-20 | Texas Instruments Incorporated | Gate structure and method |
US6919251B2 (en) * | 2002-07-31 | 2005-07-19 | Texas Instruments Incorporated | Gate dielectric and method |
US6894353B2 (en) | 2002-07-31 | 2005-05-17 | Freescale Semiconductor, Inc. | Capped dual metal gate transistors for CMOS process and method for making the same |
US20040029321A1 (en) | 2002-08-07 | 2004-02-12 | Chartered Semiconductor Manufacturing Ltd. | Method for forming gate insulating layer having multiple dielectric constants and multiple equivalent oxide thicknesses |
US6716685B2 (en) * | 2002-08-09 | 2004-04-06 | Micron Technology, Inc. | Methods for forming dual gate oxides |
JP2004111549A (ja) * | 2002-09-17 | 2004-04-08 | Seiko Epson Corp | 半導体装置の製造方法 |
US7122414B2 (en) * | 2002-12-03 | 2006-10-17 | Asm International, Inc. | Method to fabricate dual metal CMOS devices |
JP2004207481A (ja) * | 2002-12-25 | 2004-07-22 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US6841441B2 (en) | 2003-01-08 | 2005-01-11 | Chartered Semiconductor Manufacturing Ltd. | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing |
US6861712B2 (en) * | 2003-01-15 | 2005-03-01 | Sharp Laboratories Of America, Inc. | MOSFET threshold voltage tuning with metal gate stack control |
US6852645B2 (en) * | 2003-02-13 | 2005-02-08 | Texas Instruments Incorporated | High temperature interface layer growth for high-k gate dielectric |
US6873048B2 (en) * | 2003-02-27 | 2005-03-29 | Sharp Laboratories Of America, Inc. | System and method for integrating multiple metal gates for CMOS applications |
US7019351B2 (en) * | 2003-03-12 | 2006-03-28 | Micron Technology, Inc. | Transistor devices, and methods of forming transistor devices and circuit devices |
JP4524995B2 (ja) | 2003-03-25 | 2010-08-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US6737313B1 (en) * | 2003-04-16 | 2004-05-18 | Micron Technology, Inc. | Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer |
US7071086B2 (en) | 2003-04-23 | 2006-07-04 | Advanced Micro Devices, Inc. | Method of forming a metal gate structure with tuning of work function by silicon incorporation |
US7179754B2 (en) * | 2003-05-28 | 2007-02-20 | Applied Materials, Inc. | Method and apparatus for plasma nitridation of gate dielectrics using amplitude modulated radio-frequency energy |
JP2004356472A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US20040262683A1 (en) * | 2003-06-27 | 2004-12-30 | Bohr Mark T. | PMOS transistor strain optimization with raised junction regions |
US6936882B1 (en) * | 2003-07-08 | 2005-08-30 | Advanced Micro Devices, Inc. | Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages |
US7045847B2 (en) * | 2003-08-11 | 2006-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with high-k gate dielectric |
US6936508B2 (en) * | 2003-09-12 | 2005-08-30 | Texas Instruments Incorporated | Metal gate MOS transistors and methods for making the same |
JP3793190B2 (ja) * | 2003-09-19 | 2006-07-05 | 株式会社東芝 | 半導体装置の製造方法 |
US7148546B2 (en) * | 2003-09-30 | 2006-12-12 | Texas Instruments Incorporated | MOS transistor gates with doped silicide and methods for making the same |
JP4368180B2 (ja) * | 2003-10-21 | 2009-11-18 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
TWI258811B (en) | 2003-11-12 | 2006-07-21 | Samsung Electronics Co Ltd | Semiconductor devices having different gate dielectrics and methods for manufacturing the same |
US7105886B2 (en) * | 2003-11-12 | 2006-09-12 | Freescale Semiconductor, Inc. | High K dielectric film |
KR100618815B1 (ko) * | 2003-11-12 | 2006-08-31 | 삼성전자주식회사 | 이종의 게이트 절연막을 가지는 반도체 소자 및 그 제조방법 |
JP4473710B2 (ja) | 2003-12-05 | 2010-06-02 | 株式会社東芝 | 半導体装置 |
JP4085051B2 (ja) | 2003-12-26 | 2008-04-30 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7247578B2 (en) * | 2003-12-30 | 2007-07-24 | Intel Corporation | Method of varying etch selectivities of a film |
JP2005217309A (ja) * | 2004-01-30 | 2005-08-11 | Toshiba Corp | 半導体装置及びその製造方法 |
US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
JP2005268553A (ja) * | 2004-03-19 | 2005-09-29 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
KR100576361B1 (ko) * | 2004-03-23 | 2006-05-03 | 삼성전자주식회사 | 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법 |
US20050224897A1 (en) * | 2004-03-26 | 2005-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | High-K gate dielectric stack with buffer layer to improve threshold voltage characteristics |
US7001852B2 (en) * | 2004-04-30 | 2006-02-21 | Freescale Semiconductor, Inc. | Method of making a high quality thin dielectric layer |
US6897095B1 (en) * | 2004-05-12 | 2005-05-24 | Freescale Semiconductor, Inc. | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode |
US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
US7060568B2 (en) * | 2004-06-30 | 2006-06-13 | Intel Corporation | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit |
TWI367560B (en) * | 2004-07-05 | 2012-07-01 | Samsung Electronics Co Ltd | Integrated circuit devices including a dual gate stack structure and methods of forming the same |
US7279756B2 (en) * | 2004-07-21 | 2007-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof |
US7416933B2 (en) | 2004-08-06 | 2008-08-26 | Micron Technology, Inc. | Methods of enabling polysilicon gate electrodes for high-k gate dielectrics |
US7348284B2 (en) * | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7595538B2 (en) * | 2004-08-17 | 2009-09-29 | Nec Electronics Corporation | Semiconductor device |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
KR100604908B1 (ko) * | 2004-10-11 | 2006-07-28 | 삼성전자주식회사 | 이종의 게이트 절연막을 구비하는 씬-바디 채널 씨모스소자 및 그 제조방법 |
US7514310B2 (en) * | 2004-12-01 | 2009-04-07 | Samsung Electronics Co., Ltd. | Dual work function metal gate structure and related method of manufacture |
US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7091568B2 (en) * | 2004-12-22 | 2006-08-15 | Freescale Semiconductor, Inc. | Electronic device including dielectric layer, and a process for forming the electronic device |
US7205186B2 (en) * | 2004-12-29 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for suppressing oxide formation |
US7160781B2 (en) * | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
US7282426B2 (en) * | 2005-03-29 | 2007-10-16 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
US20060275975A1 (en) * | 2005-06-01 | 2006-12-07 | Matt Yeh | Nitridated gate dielectric layer |
US7361561B2 (en) * | 2005-06-24 | 2008-04-22 | Freescale Semiconductor, Inc. | Method of making a metal gate semiconductor device |
US7375394B2 (en) * | 2005-07-06 | 2008-05-20 | Applied Intellectual Properties Co., Ltd. | Fringing field induced localized charge trapping memory |
US7432201B2 (en) * | 2005-07-19 | 2008-10-07 | Applied Materials, Inc. | Hybrid PVD-CVD system |
US20070069302A1 (en) * | 2005-09-28 | 2007-03-29 | Been-Yih Jin | Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby |
-
2005
- 2005-09-30 US US11/240,698 patent/US8188551B2/en active Active
-
2006
- 2006-09-25 TW TW095135441A patent/TWI329926B/zh active
- 2006-09-27 EP EP06121325A patent/EP1770789A3/en not_active Ceased
- 2006-09-27 EP EP10195478A patent/EP2290698A3/en not_active Ceased
- 2006-09-27 EP EP10196709A patent/EP2293339A3/en not_active Withdrawn
- 2006-09-29 JP JP2006267833A patent/JP4996903B2/ja active Active
- 2006-09-29 KR KR1020060095689A patent/KR100911743B1/ko active IP Right Grant
-
2010
- 2010-10-28 JP JP2010242271A patent/JP2011066433A/ja active Pending
-
2012
- 2012-04-19 US US13/451,183 patent/US8722473B2/en active Active
-
2014
- 2014-03-20 US US14/221,108 patent/US9659962B2/en active Active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10229853B2 (en) | 2013-09-27 | 2019-03-12 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
US10692771B2 (en) | 2013-09-27 | 2020-06-23 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
US10892192B2 (en) | 2013-09-27 | 2021-01-12 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
US11335601B2 (en) | 2013-09-27 | 2022-05-17 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
US11823954B2 (en) | 2013-09-27 | 2023-11-21 | Intel Corporation | Non-planar I/O and logic semiconductor devices having different workfunction on common substrate |
Also Published As
Publication number | Publication date |
---|---|
EP1770789A2 (en) | 2007-04-04 |
US9659962B2 (en) | 2017-05-23 |
JP2011066433A (ja) | 2011-03-31 |
KR20070037395A (ko) | 2007-04-04 |
US8188551B2 (en) | 2012-05-29 |
EP2290698A3 (en) | 2012-06-20 |
US8722473B2 (en) | 2014-05-13 |
EP2290698A2 (en) | 2011-03-02 |
KR100911743B1 (ko) | 2009-08-10 |
US20140203366A1 (en) | 2014-07-24 |
US20120199909A1 (en) | 2012-08-09 |
EP2293339A2 (en) | 2011-03-09 |
EP2293339A3 (en) | 2012-06-20 |
EP1770789A3 (en) | 2010-07-07 |
TW200742068A (en) | 2007-11-01 |
JP4996903B2 (ja) | 2012-08-08 |
JP2007123867A (ja) | 2007-05-17 |
US20070075351A1 (en) | 2007-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI329926B (en) | Semiconductor devices and methods of manufacture thereof | |
TWI379384B (en) | Cmos transistors with dual high-k gate dielectric and methods of manufacture thereof | |
TWI476822B (zh) | 金屬高介電常數場效電晶體之雙金屬與雙介電質整合 | |
US7229873B2 (en) | Process for manufacturing dual work function metal gates in a microelectronics device | |
TWI378558B (en) | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices | |
US7968397B2 (en) | Semiconductor device and method of manufacturing the same | |
KR101237153B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US9281390B2 (en) | Structure and method for forming programmable high-K/metal gate memory device | |
KR101036771B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP4128574B2 (ja) | 半導体装置の製造方法 | |
JP2007005721A (ja) | 半導体装置およびその製造方法 | |
CN112786438A (zh) | 半导体器件及其栅极结构的形成方法 | |
US20100252888A1 (en) | Semiconductor device | |
JP2009267180A (ja) | 半導体装置 | |
JP2011003717A (ja) | 半導体装置及びその製造方法 | |
JP4163164B2 (ja) | 半導体装置およびその製造方法 | |
JP2006108355A (ja) | 半導体装置およびその製造方法 | |
JP2004247341A (ja) | 半導体装置 | |
JP2008244331A (ja) | 半導体装置およびその製造方法 | |
JP4145272B2 (ja) | 半導体装置の製造方法 | |
TW459351B (en) | CMOS semiconductor devices and method of formation |