TWI266393B - Substrate based unmolded package - Google Patents

Substrate based unmolded package

Info

Publication number
TWI266393B
TWI266393B TW092122242A TW92122242A TWI266393B TW I266393 B TWI266393 B TW I266393B TW 092122242 A TW092122242 A TW 092122242A TW 92122242 A TW92122242 A TW 92122242A TW I266393 B TWI266393 B TW I266393B
Authority
TW
Taiwan
Prior art keywords
lead
substrate based
package
die
semiconductor die
Prior art date
Application number
TW092122242A
Other languages
English (en)
Other versions
TW200408084A (en
Inventor
Rajeev Joshi
Original Assignee
Fairchild Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor filed Critical Fairchild Semiconductor
Publication of TW200408084A publication Critical patent/TW200408084A/zh
Application granted granted Critical
Publication of TWI266393B publication Critical patent/TWI266393B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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    • H01L2924/181Encapsulation
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
TW092122242A 2002-08-30 2003-08-13 Substrate based unmolded package TWI266393B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/233,248 US7061077B2 (en) 2002-08-30 2002-08-30 Substrate based unmolded package including lead frame structure and semiconductor die

Publications (2)

Publication Number Publication Date
TW200408084A TW200408084A (en) 2004-05-16
TWI266393B true TWI266393B (en) 2006-11-11

Family

ID=31977195

Family Applications (2)

Application Number Title Priority Date Filing Date
TW092122242A TWI266393B (en) 2002-08-30 2003-08-13 Substrate based unmolded package
TW094126031A TWI267176B (en) 2002-08-30 2003-08-13 Substrate based unmolded package

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW094126031A TWI267176B (en) 2002-08-30 2003-08-13 Substrate based unmolded package

Country Status (9)

Country Link
US (6) US7061077B2 (zh)
JP (2) JP4634146B2 (zh)
KR (1) KR101037997B1 (zh)
CN (2) CN1679162B (zh)
AU (1) AU2003257046A1 (zh)
DE (1) DE10393164T5 (zh)
MY (1) MY149851A (zh)
TW (2) TWI266393B (zh)
WO (1) WO2004021400A2 (zh)

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US7061077B2 (en) 2006-06-13
MY149851A (en) 2013-10-31
US20060006550A1 (en) 2006-01-12
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AU2003257046A8 (en) 2004-03-19
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US20080213946A1 (en) 2008-09-04
US20060003492A1 (en) 2006-01-05
US20040041242A1 (en) 2004-03-04
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US8541890B2 (en) 2013-09-24
TWI267176B (en) 2006-11-21
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US20090130802A1 (en) 2009-05-21
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JP2011018924A (ja) 2011-01-27
CN1679162A (zh) 2005-10-05
US7682877B2 (en) 2010-03-23
US7790513B2 (en) 2010-09-07
US20040207052A1 (en) 2004-10-21
JP4634146B2 (ja) 2011-02-16
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CN101685811A (zh) 2010-03-31
US7439613B2 (en) 2008-10-21

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