TWI257689B - Method for improving transistor performance through reducing the salicide interface resistance - Google Patents

Method for improving transistor performance through reducing the salicide interface resistance Download PDF

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Publication number
TWI257689B
TWI257689B TW93135874A TW93135874A TWI257689B TW I257689 B TWI257689 B TW I257689B TW 93135874 A TW93135874 A TW 93135874A TW 93135874 A TW93135874 A TW 93135874A TW I257689 B TWI257689 B TW I257689B
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Taiwan
Prior art keywords
alloy
region
source
germanium
deposition
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TW93135874A
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English (en)
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TW200524090A (en
Inventor
Anand Murthy
Boyan Boyanov
Glenn Glass
Thomas Hoffmann
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Intel Corp
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Publication of TW200524090A publication Critical patent/TW200524090A/zh
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Publication of TWI257689B publication Critical patent/TWI257689B/zh

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    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Description

1257689 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於一種高速半導體電晶體，且更特別而言 ，係關於藉由使用鍺化矽增加電晶體的效能和其改進的應 用方法。 【先前技術】 矽互補金屬氧化半導體（CMOS )技術爲一主要的微 電子技術。C Μ 0 S提供高可靠度、高度整合性、低電源耗 損、且非常有成本效益。對於低頻應用而言，C Μ 0 S仍舊 可保持爲主要技術。但是，對於較高速應用而言，如需要 高速電晶體開關速率的雷達和移動通訊裝置，在矽中的電 子和電洞移動率會限制CMOS裝置可使用的範圍。 習知的解決方式乃使用半導體化合物取代元素半導體 ，如週期表第IV族的矽和鍺。這些化合物可爲週期表第 II 族（Zn 和 Cd)，第 III 族（B，Al，Ga，和 In )，第 IV 族（C，S i，和 G e )，第 V 族（P，A s，和 S b )，和 第 VI族（S，Se，和Te)的二元、三元、四元組合。一 般111 - V半導體包括砷化鎵（G a A s )，磷化鎵（G aP )， 和磷化銦（In P )。特別的，砷化鎵因爲具有1.4 3電子伏 特（eV )帶隙已廣泛的使用當成近紅外線的來源和感應器 ，和當成用於高速電子裝置的主要半導體。雖然對於矽 CMOS裝置具有速度上的改進，但是，GaAs對於多數應 用而言仍是成本禁止的。一個1 995年預測中指出在每平 (2) (2)1257689 方毫米中，矽CMOS的成本爲$〇·〇1，而GaAs磊晶成本爲 $2.00 。 一個新的方案，其提供了 G a A s速度上的優點並改善 矽C Μ 0 S的成本效益，乃使用鍺化矽（應變或不應變，通 常準確的表示爲Sii_xGex或簡單表示爲SiGe)和/或應 變矽。鍺具有4.2 %大晶格常數（例如原子間隔），其比 矽大。鍺化矽亦具有大晶格常數，其程度決定於鍺的百分 組成。當矽成長在鍺化矽上時，在適當條件下，矽晶格拉 緊以匹配鍺化矽在矽/鍺化矽介面上。當鍺化矽成長在矽 上時，在適當條件下，鍺化矽晶格受到壓縮。對於每一方 法而言，成長層（矽或鍺化矽）皆有其臨界厚度，超過此 厚度時，成長層會因爲晶格缺陷傳播而鬆弛。 於此有兩理由說明應變矽和鍺化矽爲何可提供包含其 的電晶體的改進速度特性。相較於元素矽，鍺具有較低電 子有效質量和較低的電洞有效質量（導致較高的電子移動 率和較高的電洞移動率）。鍺化矽化合物從構成物鍺之增 加移動率獲得此優點。再者，在矽或鍺化矽中引入的應變 (張力或壓縮）會產生各向異性構造，其會改變材料的導 電帶和價帶。當和具有不同帶隙的其它半導體層（如異質 層）結合時，導電帶和價帶的不連續性可受到設計以產生 量子井或內建電場以加速載子穿過異質層。 鍺化矽沉積可相當輕易的插入CMOS處理流程。例如 ’在成本上的唯一主要增加是添加了鍺化矽磊晶步驟。在 容易整合且可以鍺化矽進行帶隙工程下（例如，塊矽、塊 -6- (3) 1257689 鍺化矽、和其應變變體），可製造整體系統在一矽基底上 或絕緣體上矽（SOI )基底上。整合系統可包括光纖連接 、波導、光學偵測器、CMOS、異接面雙極電晶體、和量 卞裝置’所有皆在相问晶片上。 簡單的使用應變矽和/或鍺化矽不會馬上獲得優良的 裝置。由於所有的標準皆位移了，安裝應變矽和鍺化矽至 現在的半導體處理流程會產生一新的問題待解決。 【發明內容及實施方式】 以下說明用以改善電晶體效能的方法的實施例。這些 實施例將參考附圖詳細說明。雖然這些實施例與附圖一起 說明，但是其並非意在將其限制至附圖所示。相反的，本 發明意在涵蓋屬於本發明之精神和範疇之各種改變和修飾 ，因此，本發明之精神和範疇應由下述申請專利範圍界定 之。 本發明之一實施例藉由使用一矽鍺合金以用於源區和 汲區和一鎳矽鍺自動對準金屬矽化物（即，自動對準金屬 矽化物）層以形成源和汲區的接觸面，而降低一電晶體的 外部電阻。鍺化矽和鎳矽鍺金屬矽化物之介面基於介於鍺 化矽和金屬矽化物間的降低金屬半導體功函數和在鍺化矽 相對於矽中增加載子移動率而具有較低的特殊接觸電阻率 。此鍺化矽可受到摻雜以進一步改變其電特性。在電晶體 外部電阻之降低相等於電晶體在開關速度和電源耗損兩者 上的效能增加。 (4) (4)1257689 在1 947年產生的第一電晶體爲鍺。但是，由於其 〇 . 6 7電子伏特（相對於矽的1 . 1 1電子伏特）的窄帶隙’ 反向偏壓鍺p-n接面會呈現大的漏電流。如此會限制鍺之 操作溫度至低於1 0 0 °c。此外’其亦難以製造半導體處理 技術中所需要的鈍化層。例如，氧化鍺爲水溶性且在80 °c分解。相對於砂而言，需要更高級數成本的電子等級鍺 之品質已實質消除了元素鍺在現代半導體技術之應用。 但是，於此使用鍺相對於矽仍是具有優點的。例如， 在室溫下，鍺具有3 60 0cm2/V-s的電子移動率，相較於矽 的 1 3 5 0 cm2/V-s。更令人振奮的是鍺的電洞移動率爲 1800cm2/V-s，相較於矽的 480cm2/V-s。由於在 300K 下， 鍺具有 2.5 X 1 013cm_3的本質載子濃度，而矽爲1.5x 10] km·3，假設導電率和移動率總和與本質載子濃度的乘 積成比例，則鍺具有顯著的高導電率。如下進一步詳細說 明，電晶體的效能係相關於外部電阻。假設電阻率爲導電 率的反比，則使用較高導電材料會增加電晶體的效能。使 矽和鍺形成合金可提供此材料可利用半導體每一構成物的 優點。如下參考本發明的實施例所述，矽和鍺的半導體合 金提供了在某些半導體應用上的改進。 圖la顯示在開始產生一金屬氧化半導體（MOS)電 晶體的各種後續處理步驟後的基底橫截面圖。熟悉此項技 藝的人士可瞭解已發生那個處理步驟，因此省略對其之說 明。在本發明的實施例中，電晶體爲p型MOS或PMOS 。基底1 〇〇爲矽。一隔離屏蔽1 0 1當成一通道阻止器以防 -8- (5) (5)1257689 止在積體電路應用中介於接近陣列的電晶體間的寄生效應 。隔離屏蔽1 可爲例如以在基底1 0 0中蝕刻一溝和將該 溝充塡一沉積氧化隔離材料而形成的一淺溝隔離（s TI ) 區。一閘極1 02形成和圖型化在一絕緣體1 04上，閘極 1 02的組成爲例如多晶矽。閘極1 02的多晶矽可進一步預 摻雜。在閘極1 02的每一側，有一般以氮化矽形成的側壁 間隔器1 03。每一側壁間隔器1 03當成一硬掩模以用於後 續的自動對準處理步驟。對於熟悉此項技藝的人士而言， 側壁間隔器1 03可例如爲一硬掩模以用於在輕摻雜汲極電 晶體設計中的高劑量植入或會從側壁間隔獲得利益的其它 設計中。 經由圖1 a所示的處理步驟，上述處理爲本行技藝人 士所知悉的標準CMOS處理流程。在圖la後用於CMOS 的後續處理乃用於藉由離子植入而摻雜源區和汲區以產生 M0S電晶體的源和汲極。但是，在此時點上，本發明的 實施例和標準CMOS流程不同。在本發明的實施例中，鍺 化矽只使用於PMOS裝置。替代源和汲區植入（亦即，在 標準CMOS處理流程的後續步驟），晶圓的曝露表面覆蓋 以如Si02或Si3N4之介電層，如圖lb之介電層104所示 。使用已知的光微影法或相關圖型化技術圖型化介電層以 曝露PM0S裝置之源和汲區，如圖lc所示，而使NM0S 裝置完全的受到覆蓋。而後，以SF6基電漿蝕刻選擇性的 移除在P Μ 0 S裝置之源和汲區中的曝露矽基底1 〇 〇材料。 此蝕刻是選擇性的，即，其以比Si02或Si3N4之介電層 -9- (6) (6)1257689 105較高的速率移除塊矽基底1〇〇，而側壁間隔器103材 料當成蝕刻掩模。而後，受鈾刻的源和汲區選擇性的塡充 以鍺化矽（在一實施例中，在原處摻雜鍺化矽）。介電層 1 0 5當成源和汲區蝕刻的掩模，而後鍺化矽沉積以例如 HF基濕蝕刻移除。形成矽化物層以提供對 PMOS和 NMO S的源、汲、和閘區的接觸。而後，此晶圓進行剩餘 的CMOS處理步驟以產生從本發明之實施例獲益的裝置。 下述將說明本發明的實施例的更特別的處理技術。 圖2爲接續圖1 c從PM 0 S裝置的源和汲區移除基底 100矽的下切蝕刻201後的基底橫截面圖。蝕刻的輪廓爲 基底1 〇〇材料已從側壁間隔器1 03下方移除。在一實施例 中，下切蝕刻2 0 1延伸在閘極1 〇 2下方。下切蝕刻2 0 1的 下切點對於由本發明的實施例所產生的效能優點有實質的 影響。 特別的，如圖2所示，下切蝕刻20 1形成在基底1 〇〇 中沿著閘極1 02的側向相對側壁。在一實施例中，使用各 向同性鈾刻處理以形成下切蝕刻2 0 1。各向同性蝕刻不只 垂直蝕入基底’且亦在每一側壁間隔器1 03下方、且在一 實施例中爲在閘極1 0 2下方、水平（側向）蝕刻。此一側 向下切鈾刻可使用例如在使用包含SF6和氨的氣體混合化 學的平行板R F電漿蝕刻系統中的各向同性乾蝕刻處理且 在適於各向同性的處理條件下產生。此條件包括高壓和低 RF功率密度。在一實施例中，處理參數包括約9 00m T的 壓力，1 · 1 cm的間隙，1 〇〇w的RF功率，1 50sccm的氦氣 -10- (7) 1257689 流，和1 OOsccm的SF6氣體流。rf功率可在例如5〇w 2 00W間變化，而處理壓力可變化，但是必須大於 5 0 0 m T。在一實施例中，下切蝕刻2 〇 1在基底〗〇 〇表面 具有介於1〇〇和1500埃的最大垂直深度，且在基底1 /絕緣體104介面上，在閘極1〇2下方，水平或側向延 介於25至200埃。於此亦可依需要使用其它處理條件 蝕刻化學（例如濕蝕刻）以產生其它下切蝕刻的幾何輪 〇 不只此一蝕刻處理產生在每一側壁間隔器1 〇 3下方 和在此實施例中在閘極1 0 2下方的側向下切，且此蝕刻 學對絕緣體1 04氧化物和對側壁間隔器！ 〇3氮化物材料 具有相當高的選擇性。以此方式，下切蝕刻不會蝕刻至 緣體和側壁間隔器1 0 3材料，且因此可保持其幾何輪廓 使用以形成下切鈾刻2 0 1的蝕刻化學進一步母微的 化。使用氧化蝕刻劑使一部份絕緣體1 0 4在下切蝕刻處 時曝露以變成比絕緣體1 04層未曝露部份厚。藉由增加 閘極1 02緣上的絕緣體1 04層的厚度，可降低在裝置的 端重Η區上的閘極緣漏電。在閘極1 〇 2緣上的較厚絕緣 1 04層有助於增加裝置的臨界電壓。 下切蝕刻2 0 1處理的進一步優點爲鈾刻率降低至每 約5至3 0埃會使矽基底的蝕刻內凹。以此幾何輪廓， MOS電晶體的關斷狀態時（低I〇ff)，可達成大的 (冶金通道長度或實際通道長度），而當通道形成時， MOS電晶體啓動狀態下，可達成較小的Lmet。在啓動 至 約 下 00 伸 和 廓 化 亦 絕 〇 氧 理 在 尖 體 秒 在 丨ET 在 狀 -11 - (8) 1257689 態下的較小Lmet直接轉換成較小通道電阻且因此較高Ion 〇 圖3爲在圖2之下切蝕刻2 0 1源和汲區中沉積鍺化矽 3 0 1後的基底橫截面圖。如所示，鍺化较可表示成 Sil_xGex。X的範圍爲[0，1]從純矽至純鍺，且可調整以改 變導電率和帶隙爲一特別裝置所需要的。在一實施例中， x約爲0.1至0.4 (例如，在矽鍺合金中約10%至40 %原子 的鍺）。相關於矽鍺3 0 1合金的帶隙能量可以下式表示：
Eg ( X) = ( 1.155 - 0.43x + 0.0206x2) eV， 對於 0 < x < 0 · 8 5 ( 1 )，
Eg ( x ) = (2.010 - 1 ·27χ ) eV， 對於 0 · 8 5 < χ < 1 ( 2 )。 因此，在一實施例中，依照式（1 )，鍺化矽3 01的 帶隙能量對於1 〇%原子的鍺和40%原子的鍺而言分別爲約 介於 1 . 1 1 e V 和 0.9 9 e V。 鍺化矽3 0 1乃藉由選擇性磊晶沉積而沉積在由下切蝕 刻2 0 1所曝露且未由介電層1 0 5覆蓋的塊矽基底表面。鍺 化矽301結晶並未成長在Si02或Si3N4之介電層上。在此 實施例中，沉積技術爲降壓化學蒸氣沉積（CVD )磊晶沉 積。在其它實施例中，沉積技術包括大氣C V D磊晶和超 真空CVD磊晶。由於所沉積的鍺化矽301爲單晶，因此 每一沉積技術爲蒸氣相磊晶的特別型式。 在此實施例中，鍺化砂沉積方法爲C V D嘉晶。嘉晶 環境發生在介於600 °C至8 00 °C間，在壓力介於10至 -12- 1257689
7 6 0 t o r r間。Η 2或H e可使用當成一載體氣體。砂源先驅 氣體可爲 SiH2Cl，Si2H4，或 Si2H6。在此實施例中， GeH4爲鍺源先驅氣體。可添加HC1或Cl2當成鈾刻劑以 增加沉積的材料選擇性。在一實施例中，沉積在下切蝕刻 201源和汲區中的所得鍺化砂301具有厚度介於5 00至 2 0 0 0埃。在一實施例中，鍺化矽3 0 1沉積延伸在基底1 0 0 表面上。以此方式，鍺化矽3 01形成在基底1 00表面上和 下。藉由形成鍺化矽301在基底100表面上，會形成一上 升尖端，增加尖端導電率。因爲增加的導電率會改善裝置 效肯b 。 鍺化矽3 0 1可進一步受到摻雜以調整其電和化學性質 。此摻雜可使用各種摻雜劑和以各種摻雜技術。例如，鍺 化矽3 0 1可在原處摻雜p型雜質至摻雜濃度位準介於1 X 1018/cm3 至 3xl021/cm3，而較佳爲 lxl02Q/cm3。在一實 施例中，在產生一 PMOS裝置下，在磊晶時，藉由使用上 述先驅物和額外的B2H6先驅氣體當成硼摻雜劑源，鍺化 矽3 01在磊晶沉積時乃在原處受摻雜以硼。在原處摻雜鍺 化矽3 0 1的優點爲下切蝕刻2 0 1的下切特性在其已沉積在 由側壁間隔器所遮住的區域後難以摻雜鍺化矽3 0 1。角度 植入爲一可能的解決方式以摻雜由側壁間隔器所遮住的鍺 化矽，以降低所獲得的PMOS裝置的短通道效能。 在一實施例中，在鍺化矽3 0 1沉積時，部份添加的硼 摻雜劑在此時並未致動。亦即，在沉積硼原子在鍺化矽 3 0 1層中但並未替換入在提供有電洞（亦即，缺乏電子） -13- (10) (10)1257689 的晶格中的矽側後。在一實施例中，熱致動摻雜劑受到延 緩直到後續處理步驟，如此可降低熱需求和促成摻雜劑擴 散以致能形成一非常陡源/汲接面，改善裝置效能。 如所述，沉積的鍺化砂3 0 1具有大的晶格吊7數’其大 小決定於在鍺化矽3 0 1合金中的鍺原子百分比。當沉積在 基底1 0 0矽上時，鍺化矽3 0 1的晶格受壓縮以容納晶體成 長。在鍺化矽3 0 1源和汲區中的壓縮進一步在位於鍺化矽 301源和汲區間和在絕緣體104區下方（即MOS裝置的 通道）的基底1〇〇區中壓縮。此壓縮在通道區產生各向異 性原子構造，改變了通道材料的導電性和價帶。此壓縮應 力進一步降低在基底1 〇〇的通道區中的電洞有效質量，進 而增加電洞移動性。所增加的電洞移動性增加了所獲得之 MO S電晶體的飽和通道電流，藉以改善裝置效能。 圖4a、4b、和4c顯示在產生矽化物層時，圖3的基 底的橫截面圖。更特別而言，此層爲自動對準矽化物層。 熟悉此項技藝的人士可知矽化物層402乃藉由以標準濺鍍 技術（如物理蒸氣沉積或PVD)沉積一耐火金屬薄層在鍺 化矽3 0 1上，而接著以後續處理步驟產生金屬、矽、和鍺 矽化物合金而形成。矽化物403之不同在於矽化物合金的 半導體元件決定於閘極1 02的材料組成。 耐火金屬包括鈷、鈦、和鎳。在一實施例中，耐火金 屬爲鎳。耐火金屬的選擇需要考量不只電相容性，且亦需 考量和佔據下切蝕刻201源和汲區和在相同基底上對應於 Ν Μ Ο S裝置的曝露源、汲、和閘區之下疊鍺化矽3 01之機 -14- (11) (11)1257689 械和化學相容性。例如，矽化物層4 02必須連續且均勻以 降低介於矽化物層4 0 2和下層鍺化矽3 0 1間的介面電阻。 鎳傾向於和矽和鍺兩者均勻的反應’形成穩定的三元N i (SiGe )相，而鈷和鈦優先和矽反應，和隔離鍺化矽301 合金的鍺成份。再者，鈦和鈷基矽鍺矽化物相較於鎳矽鍺 矽化物具有降低熱穩定性。不適當的耐火金屬選擇會在矽 化物和半導體間產生一非理想介面，其會增加介面電阻， 而無關於電相容材料。 圖4a顯示在耐火金屬401表面層沉積後的圖3的基 底。如所示，在一實施例中，耐火金屬爲PVD鎳。PVD 鎳的沉積環境發生在介於 20 °C至 20(TC的溫度和小於 5 Omtorr的壓力下。鎳的厚度介於50至200埃。鎳沉積後 續爲一快速形成退火在3 2 5 °C至45 0 °C間小於或等於60秒 ，使用例如快速熱退火設備（RTA )。在形成退火時，在 鍺化矽3 01和閘極1 02上的耐火金屬40 1反應以分別形成 矽化物402和矽化物403，如圖4b所示。當鎳沉積在基 底1 00的整體曝露表面時，未反應的鎳（亦即，未與矽或 鍺化矽反應以形成矽化物的鎳，而其下層沉積在側壁間隔 器103氮化物或隔離區101上）使用例如熱H202和熱 H2S04混合物的濕蝕亥[J化學移除。而後在鍺化矽301源和 汲區和閘極1 0 2區上的剩餘反應鎳在4 0 0 °C至5 5 0 °C間進 行最終退火以完成鎳矽鍺矽化物4 0 2和矽化物4 0 3形成， 如圖4 c所示。如所知的，矽化物層可進一步覆蓋以例如 氮化鈦蓋以防止鎳矽鍺矽化物4〇2和矽化物4 03免於在後 -15- (12) 1257689 續處理步驟中氧化。 圖5至7顯示用於耐火金屬和源-汲區材料兩者的適 當材料選擇如何降低對應的接觸電阻率。圖5顯示用於塊 金屬，p型矽，和鍺化矽的能帶圖。金屬的費密（Fermi )能量表示爲。P型矽和鍺化矽的費密能量表示爲 EFSi和EFSiGe。如圖所示，雖然無需加以刻量，但是鍺化 矽的導電帶緣EFSi(3e些微低於矽的導電帶緣Ecsi。再者， 鍺化矽的價帶緣EvsiGe些微高於矽的價帶緣EVSi，且根據 在矽鍺合金中的鍺組成百分比而成比例的高。因此，鍺矽 合金的能帶隙小於矽的能帶隙，其程度、參考式（1 )和 (2 )、乃決定於在矽鍺合金中的鍺組成百分比。 圖6顯示相關於介於耐火金屬和p型矽間的接觸的帶 彎曲。需注意的是能量屏蔽的大小。以P型半導體而言， 對準在平衡下的費密位準造成在金屬側上的正電荷和在半 導體側上的負電荷。藉由產生在離子化受體由電洞餘留未 飽和的空乏區，半導體容納此負電荷。 圖7顯示相關於介於耐火金屬和鍺化矽3 0 1合金間的 接點的能帶彎曲。需再度注意的是能量屏蔽的大小。在此 例中，相較於P型矽，在矽鍺合金之能量屏蔽差異較高。 換言之’金屬-半導體功函數對於金屬·鍺化矽301接點相 對於金屬-P-型矽接點而言是較小的。用於接點的電流導 電乃由隧道效應所主宰。特殊的接觸電阻率關係如下： ⑶
Pcn (13) (13)1257689 在式（3 )中的顯著的變數爲金屬-半導體功函數φ B ，半導體摻雜Nsurf，和在半導體中的有效載子質量 如所示’在鍺化矽膜中的電洞的有效質量爲〇.34mG相對 於矽的〇 · 3 7 m 〇，其中m ^表示電子的剩餘質量。 特殊接觸電阻率等式（3)表示用於金屬-半導體介面 的特殊接觸電阻率主要決定於金屬-半導體功函數，在半 導體中的摻雜密度，和載子的有效質量。改變其變數之一 或其結合會影響特殊接觸電阻率。如所示，使用鍺化矽 301會降低金屬半導體功函數，和降低載子有效質量。在 一實施例中，參考圖3所示，鍺化矽受到進一步摻雜。 介於鍺化矽301和矽化物402間的介面可當成金屬-半導體歐姆接觸而進一步討論。首先，在介於砂化物和半 導體間的接點上的能量屏蔽必須從一量子機械觀點觀之。 如本行人士所知，波粒子二元性指示電子被處理當成一粒 子和一波以決定其如何表現。由矽化物-半導體介面所產 生的能量屏蔽可由電位屏蔽的精細厚度和高度所觀察到。 對於高於入射電子的能量之一給定的屏蔽和一給定的屏蔽 寬度，於此有可能電子會穿透屏蔽和出現在另一側。此種 隧道現象爲在固態電子傳導學中相當重要的架構。 更特別而言，接觸電阻率爲電流可多容易的穿過一金 屬-半導體介面的測量方式。如果是歐姆接觸，在介於矽 化物4 0 2和鍺化矽3 0 1間的例中，會有從一材料至另一材 料的多數載子的不受阻傳送。此亦可表示成線性電流-電 壓特性。在金屬-半導體介面的例中，導電架橇部份由接 -17- (14) 1257689 近接觸介面的半導體空乏區的寬度主宰。如果半導體受到 輕摻雜（例如’費密能量既非接近導電帶緣能量，亦非接 近價帶緣能量）’則空乏區變成足夠寬，而電子在兩接觸 材料間傳送的唯一方式即是藉由熱游子發射過最大屏蔽而 跳躍過電位屏蔽。替代的，如果半導體受到重摻雜（例如 ’費密能量靠近用於η型的導電帶緣能量，和接近用於p 型的價帶緣能量），則空乏區變成足夠窄，而因此場發射 ’或載子隧道現象即爲導電架構的主宰。場發射和熱游子 發射皆有助於穿過介面的導電，且可、例如由材料選擇和 摻雜而調整。 圖8顯示使用具有例如鎳矽鍺矽化物層4 02的鍺化矽 301源和汲區的本發明的一實施例。外部電阻Rext801爲 介於源（或汲）接點和本質電晶體的通道間的整體序列電 阻。介於鍺化矽3 0 1和矽化物402間的介面電阻爲整體序 列電阻的重要成份。藉由使用鍺化矽相對於使用用於源和 汲區的p型矽，可降低Rext 801。再者，適當的選擇矽化 物層402耐火金屬，在本實施例中爲鎳，可確保一化學的 和機械的相容金屬-半導體介面不會負面的助於Rext801， 如參考圖4所示。 熟悉此項技藝的人士可知，本發明所揭示的實施例藉 由使用新穎的材料選擇和處理技術，可降低介於鍺化矽源 和汲區間和它們相關的矽化物接點的特殊接觸電阻率。由 於接觸電阻率會影響電晶體的整體外部電阻率，因此，接 觸電阻率的降低有助於在電晶體之整體效能的增加。 -18- (15) (15)1257689 【圖式簡單說明】 圖1 a爲在閘極和氮化物間隔器形成後的基底橫截面 圖； 圖lb爲在沉積一介電膜在整個基底表面後的基底橫 截面圖； 圖1 c爲在圖型化和鈾刻介電膜以曝露源和汲區後的 基底橫截面圖； 圖2爲在源和汲區下切蝕刻後的基底橫截面圖； 圖3爲在下切源和汲區中沉積鍺化矽後的基底橫截面 圖； 圖4a爲在沉積一耐火金屬後的基底橫截面圖； 圖4b爲在退火以形成一金屬矽化物在鍺化矽源汲區 和閘區表面上後的基底橫截面圖； 圖4c爲在移除未反應的耐火金屬後的基底橫截面圖 圖5爲p型矽相對於鍺化矽的觸排構造圖； 圖6爲p型矽接觸一金屬的觸排構造圖； 圖7爲鍺化矽接觸一金屬的觸排構造圖；和 圖8爲表示金屬氧化物半導體電晶體的外部電阻（ Rext)的基底橫截面圖。 【主要元件符號說明】 100 基底 •19- 1257689 (16) 10 1 隔離屏蔽 1 02 閘極 1 03 側壁間隔器 1 04 絕緣體 1 05 介電層 20 1 下切蝕刻 301 鍺化矽 40 1 耐火金屬 402 矽化物層 403 矽化物

Claims (1)

1257减1 :第 (1) 93135874 號專利申請案 中文申請專利範圍替換本 民國一95年1月 18曰修正 十、申請專利範圍
1 ·~種形成電晶體的方法，包含： 在一矽基底中蝕刻一源區和一汲區，其中該蝕刻具有 一下切輪廓； 沉積一矽鍺合金在該源區和汲區； 沉積鎳在矽鍺合金上；和 形成一鎳矽鍺金屬矽化物層，其中該鎳矽鍺金屬矽化 物爲自動對準。 2·如申請專利範圍第〗項之方法，其中該源區和汲區 在一絕緣層下方側向延伸。 3 ·如申請專利範圍第2項之方法，其中該源區和汲區 在一閘區下方側向延伸。 4·如申請專利範圍第3項之方法，其中該源區和汲區 在該閘區下方在2 5至2 0 0埃間側向延伸。 5 ·如申請專利範圍第1項之方法，其中該源區和汲區 在矽基底表面下方具有介於100至1 5 00埃間的垂直深度 6 ·如申請專利範圍第1項之方法，其中該触刻爲乾 SF6基礎蝕刻。 7·如申請專利範圍第1項之方法，其中該矽鍺合金具 有之鍺組成介於5%至50%間。 8·如申請專利範圍第7項之方法，其中該矽鍺合金具 有之鍺組成介於10%至40%間。 9·如申請專利範圍第8項之方法，其中該矽鍺合金具 (2) 1257689 有之鍺組成介於15%至30%間。 1 〇 ·如申請專利範圍第1項之方法，其中該砂鍺合金 之沉積爲蒸氣相磊晶沉積。 11.如申請專利範圍第1項之方法，其中該砂鍺合金 之沉積爲降壓化學蒸氣沉積。 1 2 ·如申請專利範圍第1項之方法，其中該砂鍺合金 之沉積爲大氣化學蒸氣沉積。 1 3 ·如申請專利範圍第I項之方法，其中該砂鍺合金 之沉積爲超高真空化學蒸氣沉積。 1 4 ·如申請專利範圍第1項之方法，其中沉積該矽鍺 合金之步驟進一步包含摻雜該合金。 1 5 ·如申請專利範圍第1 4項之方法，其中在沉積該砂 鍺合金時之該摻雜乃在原處進行。 1 6 ·如申請專利範圍第1 5項之方法，其中一慘雜劑爲 硼。 1 7 ·如申g靑專利範圍第1 6項之方法，其中該慘雜劑之 來源爲B2H6。 1 8 ·如申請專利範圍第1 6項之方法，其中該硼之摻雜 濃度位準介於lxl018/cm3和3xl〇2I/cm3間。 1 9 ·如申請專利範圍第1 8項之方法，其中該摻雜濃度 位準爲 lxl02G/cm3。 2 〇 .如申請專利範圍第1項之方法，其中鎳之厚度介 於5 0至2 0 0埃間。 2 1 ·如申請專利範圍第1項之方法，其中形成鎳矽鍺 -2 - (3) 1257689 金屬砍化物層之步驟進一步包含： 使基底在3 25 °C至450°C間的溫度退火小於或等於60 秒； 以熱H202和H2S04之濕蝕刻化學移除過多的鎳；和 使基底在400°C至5 5 0°C間的溫度退火。 22.—種半導體電晶體，包含： 一閘區； 一絕緣區，其位於閘區下方； 一源區，其相鄰一氧化區；和 一汲區，其相鄰該氧化區， 其中該源區和汲區包括一矽鍺合金和一鎳矽鍺金屬矽 化物層。 2 3.如申請專利範圍第22項之半導體電晶體，其中該 源區和汲區在一絕緣層下方側向延伸。 24.如申請專利範圍第23項之半導體電晶體，其中該 源區和汲區在一閘區下方側向延伸。 2 5.如申請專利範圍第24項之半導體電晶體，其中該 源區和汲區在該閘區下方在2 5至2 0 0埃間側向延伸。 26.如申請專利範圍第22項之半導體電晶體，其中該 源區和汲區在矽基底表面下方具有介於1〇〇至1500埃間 的垂直深度。 2 7.如申請專利範圍第22項之半導體電晶體，其中該 矽鍺合金具有之鍺組成介於5 °/。至5 0%間。 2 8.如申請專利範圍第27項之半導體電晶體，其中該 (4) 1257689 矽鍺合金具有之鍺組成介於10%至40%間。 29.如申請專利範圍第28項之半導體電晶體，其中該 矽鍺合金具有之鍺組成介於15%至3 0%間。 3 0.如申請專利範圍第22項之半導體電晶體，其中該 矽鍺合金受到摻雜。 3 1 ·如申請專利範圍第3 0項之半導體電晶體，其中在 沉積該矽鍺合金時，該矽鍺在原處受到摻雜。 32. 如申請專利範圍第31項之半導體電晶體，其中一 摻雜劑爲硼。 33. 如申請專利範圍第32項之半導體電晶體，其中該 摻雜劑之來源爲B2H6。 3 4.如申請專利範圍第32項之半導體電晶體，其中該 硼之摻雜濃度位準介於lxl〇18/cm3和3xl021/cm3間。 35.如申請專利範圍第34項之半導體電晶體，其中該 摻雜濃度位準爲lxl〇2()/cm3。 3 6.如申請專利範圍第22項之半導體電晶體，其中鎳 矽鍺金屬矽化物層爲自動對準。 3 7.—種形成電晶體的方法，包含： 在一矽基底中蝕刻一源區和一汲區，其中該蝕刻具有 一下切輪廓； 沉積一砂鍺合金在該源區和汲區’其中該砂鍺合金具 有之鍺組成介於15%至30%間； 以硼在原處摻雜矽鍺合金，其中硼摻雜濃度位準爲ϊ xlO20/ -4- (5) 1257689 沉積鎳在矽鍺合金上； 使基底在3 2 5 °C至4 5 0 °C間的溫度退火小於或等於6 0 秒； 以熱h2o2和H2S04之濕蝕刻化學移除過多的鎳；和 使基底在4 0 0 °C至5 5 0 °C間的溫度退火。 3 8 ·如申請專利範圍第3 7項之方法，其中該源區和汲 區在一絕緣層下方側向延伸。 3 9 .如申請專利範圍第3 8項之方法，其中該源區和汲 區在一閘區下方側向延伸。 40.如申請專利範圍第39項之方法，其中該源區和汲 區在該閘區下方在2 5至2 0 0埃間側向延伸。 4 1 ·如申請專利範圍第3 7項之方法，其中該源區和汲 區在矽基底表面下方具有介於100至1500埃間的垂直深 度。 42 ·如申請專利範圍第3 7項之方法，其中該蝕刻爲乾 SF6基礎蝕刻。 4 3 ·如申請專利範圔第3 7項之方法，其中該矽鍺合金 之沉積爲蒸氣相磊晶沉積。 44·如申請專利範圍第37項之方法，其中該矽鍺合金 之沉積爲降壓化學蒸氣沉積。 4 5 ·如申請專利範圍第3 7項之方法，其中該矽鍺合金 之沉積爲大氣化學蒸氣沉積。 4 6 .如申請專利範圍第3 7項之方法，其中該矽鍺合金 之沉積爲超高真空化學蒸氣沉積。
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