CN101677110A - 用于通过减少自对准硅化物界面电阻改善晶体管性能的方法 - Google Patents

用于通过减少自对准硅化物界面电阻改善晶体管性能的方法 Download PDF

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CN101677110A
CN101677110A CN200910205003A CN200910205003A CN101677110A CN 101677110 A CN101677110 A CN 101677110A CN 200910205003 A CN200910205003 A CN 200910205003A CN 200910205003 A CN200910205003 A CN 200910205003A CN 101677110 A CN101677110 A CN 101677110A
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equipment
transistor
alloy
sige
drain region
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CN101677110B (zh
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A·莫西
B·波亚诺夫
G·格拉斯
T·霍夫曼
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Intel Corp
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Abstract

本发明的实施例通过使用用于源极和漏极区的硅锗合金以及镍硅锗自对准硅化物(即，自对准硅化物)层以形成源极区和漏极区的接触表面来减小晶体管的外电阻。基于硅锗和硅化物之间减少的金属半导体功函数数以及与硅相比硅锗中增加的载流子迁移率，硅锗和镍硅锗硅化物的界面具有较低的比接触电阻。可对硅锗进行掺杂以进一步调节其电属性。晶体管的外电阻的减小等同于在切换速度和功耗两方面提高晶体管性能。

Description

用于通过减少自对准硅化物界面电阻改善晶体管性能的方法
本发明专利申请是国际申请号为PCT/US2004/038986，国际申请日为2004年11月19日，进入中国国家阶段的申请号为200480033557.X，名称为“用于通过减少自对准硅化物界面电阻改善晶体管性能的方法”的发明专利申请的分案申请。
技术领域
本发明的实施例涉及高速半导体晶体管，尤其涉及通过使用硅锗和其改进的应用方法来提升半导体性能。
背景技术
硅互补金属氧化物半导体(CMOS)技术是主要的微电子技术。CMOS提供了高可靠性、高集成度、低功耗和低成本。对于较低频率的应用，CMOS最可能保持为主要的技术。但是，硅中的电子和空穴迁移率限制了CMOS器件可用于诸如需要高晶体管开关速度的雷达和移动通信装置的高速应用的范围。
一个历史上的解决方案是使用半导体化合物代替诸如IV族硅和锗的元素半导体。这些化合物可以是II族(Zn和Cd)、III族(B、Al、Ga和In)、IV族(C、Si和Ge)、V族(P、As和Sb)和VI族(S、Se和Te)元素的二价、三价、四价组合。普通的III-V半导体包括砷化镓(GaAs)、磷化镓(GaP)和磷化铟(InP)。特别是，砷化镓广泛地用作1.43电子伏特(eV)带隙的近红外光源和传感器并用作高速电子器件的主要半导体。尽管速度改善优于硅CMOS器件，但GaAs对于大多数应用来说是成本过高的。一项估计表明1995年的每平方毫米美元，硅CMOS成本为$0.01而GaAs外延的成本为$2.00。
一种既提供GaAs的速度优势又具有硅CMOS的较佳成本效率的更新的方法采用硅锗(应变的或不应变的，通常更精确地由Si1-xGex标注或简单地标注为SiGe)和/或应变硅。锗的晶格常数(即，原子间距)比硅大4.2％。硅锗也具有较大的晶格常数，其程度取决于锗的百分组成。当在硅锗上生长硅时，在合适的条件下，在硅/硅锗界面处硅晶格伸长以与硅锗的晶格相匹配。当在硅上生长硅锗时，在适当的条件下硅锗晶格被压缩。对于每种方法，存在生长层(硅或硅锗)的临界厚度，当晶格缺陷扩散时生长层松弛超过该临界厚度。
应变硅和硅锗能对由其构成的晶体管提供改进的速度特征有两个原因。与元素硅相比，锗具有较低的电子有效质量和较低的空穴有效质量(导致较高的电子迁移率和较高的空穴迁移率)。硅锗化合物得益于成分锗的增加的迁移率。此外，硅或硅锗中诱发的应变(分别是拉伸和压缩)形成改变材料的导带和价带的各向异性结构。当与具有不同带隙的其它半导体层(例如，异形层)组合时，可以设计导带和价带不连续以形成量子势阱或内部电场以加速载流子穿过异形层。
可以相对容易地将硅锗沉积结合入CMOS工艺流程。例如，较大的成本增加仅仅是硅锗外延步骤的添加。假定集成较容易且可能用硅锗(例如，块硅、块硅锗和每一种的应变变型)来改变带隙，则在一个硅或绝缘衬底硅(SOI)基片上制造整个系统的可能性是现实的。集成系统可包括全部在同一芯片上的光纤连接、波导、光学检测器、CMOS、异质结双极晶体管和量子器件。
简单地使用应变硅和/或硅锗不会立即提供优良的器件。如同所有示例变化，将应变硅和硅锗结合入当前的半导体处理流程形成了要解决的新的一组问题。
附图说明
图1a示出了栅极和氮化物隔离物形成之后基片的横截面。
图1b示出了在整个基片表面上沉积电介质薄膜后基片的横截面。
图1c示出了将电介质薄膜形成图案并蚀刻以露出源极和漏极区之后基片的横截面。
图2示出了源极和漏极区底切蚀刻之后基片的横截面。
图3示出了在底切蚀刻的源极和漏极区中沉积硅锗之后基片的横截面。
图4a示出了沉积难溶金属后基片的横截面。
图4b示出了形成退火以便在硅锗源极漏极区和栅极区的表面上形成硅化物接触层之后基片的横截面。
图4c示出了去除未反应的难溶金属后基片的横截面。
图5示出了p型硅比硅锗的能带结构。
图6示出了与金属相接触的p型硅的能带结构。
图7示出了与金属相接触的硅锗的能带结构。
图8示出了表示金属氧化物半导体晶体管的外电阻(Rext)的基片的横截面。
具体实施方式
下文将描述用于改善晶体管性能的方法实施例。现在参照附图详细描述这些实施例，如附图中所示的。虽然将联系这些附图来描述实施例，但并非旨在将它们限制于这里所揭示的附图。相反，目的在于覆盖所述实施例的精神和范围内的所有变化、修改和等效物，如所附权利要求书所限定的。
通过使用硅锗合金用于源极和漏极区以及镍硅锗自对准硅化物(即，自对准硅化物)层来形成源极和漏极区的接触表面，本发明的实施例减小了晶体管的外电阻。基于硅锗和硅化物之间减小的金属半导体功函数以及硅锗比硅中增加的载流子迁移率，硅锗和镍硅锗硅化物的界面具有较低的比接触电阻率。可对硅锗掺杂以进一步调整其电属性。晶体管外电阻的降低等同于开关速度和功耗两方面晶体管性能的提升。
1947年制造的第一个晶体管是锗。但是，给出0.67电子伏特的较窄带隙(比之于硅的1.11电子伏特)，反向偏压的锗p-n结呈现较大的漏电流。这将锗的工作温度限制于低于100℃。此外，很难制造钝化层，如半导体处理技术所需要的。例如，氧化锗是水溶的并在80℃时分离。这些品质与同硅相比需要高一个数量级的成本的电子级锗实际上从现代半导体技术中消除了元素锗。
但是，使用锗比硅具有好处。例如，在室温下，与硅的1350cm2/V-s的电子迁移率相比，锗具有3600cm2/V-s的电子迁移率。更惊人的是，与硅的480cm2/V-s的空穴迁移率相比，锗的空穴迁移率是1800cm2/V-s。由于300K下锗具有2.5*1013cm-3的本征载流子浓度的硅具有1.5*1010cm-3，且传导率与迁移率之和与本征载流子浓度的乘积成比例，所以锗具有明显更高的导电率。如以下进一步描述的，晶体管的性能与外电阻有关。由于电阻率是导电率的倒数，所以使用更高导电率的材料就增加了晶体管的性能。使硅和锗成为合金提供了调节材料的能力以利用每个组成半导体的益处。如参考本发明实施例描述的，硅和锗的半导体合金在某些半导体应用中提供有前途的改进。
图1a示出了在开始形成金属氧化物半导体(MOS)晶体管的各种处理步骤后基片的横截面。本领域的熟练技术人员将认识到进行了什么处理步骤，因此省去其说明。在本发明的实施例中，晶体管是p型MOS或PMOS。基片100是硅。隔离阻挡层101用作沟道障碍(stop)以防止集成电路应用中靠近排列的晶体管之间的寄生效应。隔离阻挡层101例如可以是浅沟槽隔离(STI)区，它是通过蚀刻基片100中的沟槽并用沉积的氧化物隔离材料填充该沟槽而形成的。栅极102在绝缘体104上形成并形成图案，栅极102的组合物例如是多晶硅。栅极102的多晶硅可被进一步预掺杂。在栅极102的每一侧上，有通常由氮化硅构成的侧壁隔离物103。每个侧壁隔离物103都用作用于后续自对准处理步骤的硬掩膜。本领域的熟练技术人员将理解，例如侧壁隔离物103是用于得益于侧壁隔离的轻度掺杂的漏极晶体管设计或其它设计中高剂量植入的硬掩膜，如本领域公知的。
通过图1a所示的处理步骤，所述的处理是本领域公知的标准CMOS处理流程。图1a后用于CMOS流程的下一个处理步骤是通过离子植入掺杂源极和漏极区来形成MOS晶体管的源极和漏极区。但是，在这点上，本发明实施例的处理不同于标准CMOS处理流程。在本发明的一个实施例中，硅锗仅用于PMOS器件。代替源极和漏极区植入(即，标准CMOS处理流程中的下一个步骤)，用例如SiO2或Si3N4的电介质层覆盖晶片的暴露表面，如图1b中的电介质层105所示。使用任何已知的光刻或相关图案形成技术将电介质层形成图案，以露出预期PMOS器件的源极区和漏极区，如图1c所示，并保留预期的NMOS器件被完全覆盖。随后，SF6基的等离子体蚀刻选择性地去除PMOS器件的源极和漏极区中露出的硅基片100材料。该蚀刻是选择性的，其中它以远高于用作蚀刻掩膜的SiO2或Si3N4电介质层105和侧壁隔离物103材料的速率去除大量硅基片100材料。随后，用硅锗(在一实施例中，原位掺杂硅锗)填充被蚀刻的源极和漏极区。随后，例如用基于HF的湿法蚀刻去除用作源极和漏极区蚀刻和硅锗沉积的掩膜的电介质层105。形成硅化物层以提供与PMOS和NMOS的源极、漏极和栅极区的接触。接着，晶片可经历剩余的CMOS处理步骤以形成得益于本发明实施例的器件。接着将描述本发明实施例的更特别的处理技术。
图2示出在如以上所介绍的底切蚀刻201以从PMOS器件的源极和漏极区中去除基片100硅之后图1c的基片横截面。蚀刻的轮廓使得基片100材料从侧壁隔离物103下面去除。在一实施例中，底切蚀刻201在栅极102下延伸。底切蚀刻201的底切外表对于本发明实施例所形成的性能益处有实质性影响。
特别是，如图2所示，底切蚀刻201形成于基片100中横向沿着栅极102的两相对侧壁。在一实施例中，使用各向同性的蚀刻工艺来形成底切蚀刻201。各向同性的蚀刻不仅垂直地蚀刻入基片还水平(横向)地在每个侧壁隔离物103下且在一个实施例中在栅极102下进行蚀刻。可以通过利用各向同性的干蚀刻工艺在例如使用包含SF6和氦的气体混合化学成分以及支持各向同性的工艺条件的平行板RF等离子体蚀刻系统中生成这种横向底切蚀刻。这些条件包括高压和低RF功率密度。在一个实施例中，使用包括约900mT的压强、1.1cm的间隙、100W的RF功率、150sccm的氦流量和100sccm的SF6流量的处理参数。RF功率例如可在50W到200W的范围内变化，且处理压强可以变化但应大于约500mT。在一实施例中，底切蚀刻201具有基片100的表面下100到1500埃之间的最大垂直深度并在基片100/绝缘体104界面处栅极102边缘下水平或横向地在25到200埃之间延伸。可以理解，如需要，可选的处理条件和蚀刻化学处理(例如，湿法蚀刻)可用于生成其它底切蚀刻201几何结构轮廓。
这种蚀刻工艺不仅在每个侧壁隔离物103下且在一个实施例中在栅极102下形成横向底切，且蚀刻化学处理对于绝缘体104氧化物和侧壁隔离物103氮化物材料也是高度可选的。这样，底切蚀刻不侵害绝缘体和侧壁隔离物103材料且保留了每一个的几何结构。
进一步稍许氧化用于形成底切蚀刻201的蚀刻化学成分。利用氧化蚀刻剂使得底切蚀刻处理期间露出的一部分绝缘体104层变得比绝缘体104层的未暴露部分更厚。通过增加栅极102边缘处的绝缘体104层的厚度，可以减少器件顶重叠区处的栅极边缘泄漏。栅极102边缘处的较厚绝缘体104层有助于增加器件的击穿电压。
底切蚀刻201处理的另一优点在于蚀刻速率减小到每秒5到30埃之间，使得硅基片的蚀刻向内凹入。采用这种几何结构，当形成沟道时，在MOS晶体管的截止状态(低Ioff)期间实现了较大的LMET(冶金沟道长度或物理沟道长度)同时在MOS晶体管的导通状态期间实现了较小的LMET。导通状态期间较小的LMET直接转变为较小的沟道电阻和相应的较高的Ion。
图3示出了底切蚀刻201源极和漏极区中沉积硅锗301后图2基片的横截面。如上所述，硅锗可由Si1-xGex表示。x的域是范围从纯硅到纯锗的[0，1]，并可以调节以按具体器件的需要调整传导率和带隙。在一实施例中，x约在0.1到0.4之间(例如，硅锗合金中10原子％到40原子％的锗之间)。与硅锗301合金相关联的带隙能量可由以下等式近似：
Eg(x)＝(1.155-0.43x+0.0206x2)eV    对于0＜x＜0.85    (1)
Eg(x)＝(2.010-1.27x)eV    对于0.85＜x＜1    (2)
因此，在一实施例中，根据等式(1)，硅锗301的带隙能量约在1.11eV到0.99eV之间，分别对应于10原子％的锗和40原子％的锗。
硅锗301通过选择性的外延沉积而被沉积，其中硅锗仅沉积于由底切蚀刻201露出且电介质层105未覆盖的较大硅基片表面上。硅锗301晶体不生长于SiO2或Si3N4电介质层上。在一实施例中，沉积技术是减少压力的化学气相沉积(CVD)外延沉积。在其它实施例中，沉积技术包括大气CVD外延和超高真空CVD外延。由于沉积的硅锗301是单晶的，每种沉积技术都是特殊形式的气相外延。
如上所述，在一实施例中，硅锗沉积法是CVD外延。环境上，外延发生于600℃到800℃之间并在10到760托之间的压强下。可将H2或He用作载体气体。。硅源前体气体可以是SiH2Cl、SiH4或Si2H6。在一实施例中，GeH4是锗源前体气体。可添加HCl或Cl2作为蚀刻剂以增加沉积的材料选择性。在一实施例中，底切蚀刻201源极和漏极区中沉积的形成的硅锗301具有500到2000埃之间的厚度。在一实施例中，硅锗301沉积在基片100的表面上延伸。这样，硅锗301同时形成于基片100的表面之上和之下。通过在基片100的表面上形成硅锗301，形成了上升的末端，增加了该末端的传导率。而该提升的传导率又改善了器件的性能。
硅锗301可进一步被掺杂以调节其电气和化学属性。掺杂可利用各种掺杂物并用各种掺杂技术进行。例如，硅锗301可以用p型杂质原位掺杂到1*1018/cm3和3*1021/cm3之间的掺杂浓度水平，其中约1*1020cm3的浓度是优选的。在一实施例中，形成PMOS器件，通过在硅锗301外延沉积期间将上述前体和附加的B2H6前体气体作为硼掺杂物源，在外延期间用硼原位掺杂硅锗301。原位掺杂硅锗301的好处在于底切蚀刻201的底切性质使得很难在它已沉积于侧壁隔离物所遮蔽的区域中之后掺杂硅锗301。作为掺杂由侧壁隔离物所遮蔽的硅锗的一种可能的解决方案，有角度的植入减少了所获得的PMOS器件的短沟道性能。
在一实施例中，在硅锗301沉积期间添加的硼掺杂物的一部分此时不被激活。即，在沉积后，硼原子处于硅锗301层中但仍未替换入可提供空穴(即，缺少电子)的晶格中的硅位点。在一实施例中，掺杂物的热激活被推迟直到后续处理步骤，降低了热积存和所产生的掺杂物扩散以使能形成很陡的源极/漏极结，从而改善器件性能。
如上所述，沉积的硅锗301具有较大的晶格常数，其幅度取决于硅锗301合金中锗的原子百分比。当沉积于基片100硅上时，硅锗301的晶格被压缩以适应结晶生长。硅锗301源极和漏极区的压缩进一步形成了位于硅锗301源极和漏极区之间并在绝缘体104区域下的基片100区域中的压缩(即，MOS器件的沟道)。该压缩形成了沟道区中各向异性的原子结构，改变沟道材料的导带和价带。压缩应力进一步减少了基片100的沟道区中的空穴有效质量，从而增加了空穴迁移率。该提升的空穴迁移率增加了所获得的MOS晶体管的饱和沟道电流，从而改善器件性能。
图4a、4b和4c示出了硅化物层的形成期间图3的基片横截面。更具体地，该层是自对准硅化物层或自对准金属硅化物层。本领域的熟练技术人员将理解，通过沉积难溶金属的薄层而在硅锗301上形成硅化物层402，在一个实施例中这采用标准溅射技术(即，物理气相沉积或PVD)，随后用后续处理步骤形成金属、硅和锗硅化物合金。硅化物403不同之处在于硅化物合金的半导体元素取决于栅极102的材料成分。
难溶金属尤其包括钴、钛和镍。在一实施例中，难溶金属是镍。难溶金属的选择不仅需要考虑与下面的硅锗301材料的电气兼容性还要考虑机械和化学兼容性，该硅锗301材料占据了同一基片上相应NMOS器件的底切蚀刻201源极和漏极区和露出的源极、漏极和栅极区。例如，硅化物层402必须是连续的和均匀的，以帮助减少硅化物层402和下面的硅锗301之间的界面电阻。镍趋于与硅和锗两者均匀地反应，形成稳定的三Ni(SiGe)相，而钴和钛优先与硅反应并离析硅锗301合金的锗组分。此外，与镍硅锗硅化物相比，钛和钴基的硅锗硅化物降低了热稳定性。不合适的难溶金属选择会形成硅化物和半导体之间的不理想界面，会独立于另外电兼容的材料增加界面电阻。
图4a示出了在毯状沉积难溶金属401后图3的基片。如上所述，在一实施例中，难溶金属是PVD镍。环境上，PVD镍沉积发生于20℃到200℃之间并在小于50毫托的压强下。镍的厚度在50到200埃之间。镍沉积之后，在325℃和450℃之间在小于或等于60秒内例如使用快速热退火(RTA)设备进行快速形成退火。在形成退火期间，硅锗301和栅极102顶上的难溶金属401反应，以分别形成硅化物402和硅化物403，如图4b所示。当镍沉积于基片100的整个暴露表面上时，利用例如热H2O2和热H2SO4的混合物的湿蚀刻化学成分将未反应的镍(即，在沉积于侧壁隔离物103氮化物或隔离101区域顶上时未与硅或硅锗反应以形成具有其下面层的硅化物的镍)去除。硅锗301源极和漏极区以及栅极102区顶上的剩余的反应过的镍随后经受400℃和550℃之间的最后退火以完成镍硅锗硅化物402和硅化物403的形成，如图4c所示。可以用例如氮化钛盖进一步盖住硅化物层，以防止镍硅锗硅化物层402和硅化物层403在后续处理步骤中氧化，如本领域公知的。
图5到7示出了用于难溶金属和源极-漏极区材料的合适的材料选择如何减少相应接触电阻率的物理性质。图5示出了较大片金属、p型硅和硅锗的能带图。金属的费米能被标注为EFm。p型硅和硅锗的费米能分别是EFSi和EFSiGe。如图所示，尽管不必按比例绘制，但硅锗的导带边缘ECSiGe稍许低于硅的导带边缘ECSi。此外，硅锗的价带边缘EVSiGe高于硅的价带边缘EVSi，并基于硅锗合金中锗的百分比组成而成比例地变高。因此，硅锗合金的能带间隙小于硅的能带间隙，其程度取决于锗合金中锗的百分比组成，如参考等式(1)和(2)所介绍的。
图6示出了与难溶金属和p型硅之间的接触相关联的能带弯曲。能量势垒的大小是值得注意的。采用p型半导体，在平衡状态下对准费米能级要求金属侧上的正电荷和半导体侧上的负电荷。半导体通过生成其中保留电离的受主未由空穴补偿的耗尽区来调节负电荷。
图7示出了与难溶金属和硅锗301合金之间的接触相关联的能带弯曲。能量势垒的大小是值得注意的，在此情况下注意在与p型硅相比较时硅锗合金的能量势垒高度中的相对差。换句话说，金属半导体功函数对于金属-硅锗301接触比金属-p-型硅接触更小。接触的电流传导由隧穿支配。比接触电阻率关系如下：
ρ c ∝ e 4 π Φ B qh m * s N surf - - - ( 3 )
等式(3)中的显著的变量是金属-半导体功函数ΦB，半导体掺杂Nsurf，以及半导体中的有效载流子质量m*。如上所述，硅锗薄膜中空穴的有效质量是0.34m0比硅的0.37m0，其中m0表示电子的静止质量。
比接触电阻率等式(3)示出金属-半导体界面的比接触电阻率主要取决于金属-半导体功函数、半导体中的掺杂密度和载流子的有效质量。改变这些变量中的任一个或者它们的组合就会影响比接触电阻率。如上所述，利用硅锗301减少了金属半导体功函数并减少了载流子的有效质量。在一实施例中，硅锗被进一步掺杂，如参考图3所述的。
硅锗301和硅化物402之间的界面可作为金属-半导体欧姆接触来进一步讨论。一开始，硅化物和半导体之间的接触处的能量势垒的效果必须从量子力学的观点来看。如本领域公知的，波粒二象性指明电子作为粒子和波两者看待以确定它的行为。硅化物-半导体界面所形成的能量势垒可以被视作有限厚度和高度的势垒。对于大于大于入射电子能量的给定势垒高度和给定势垒宽度，存在一定的概率使得电子穿过势垒并出现于另一侧。这种隧穿现象是固体中电子传导的重要机制。
更具体地，接触电阻率是电流如何容易地流过金属-半导体界面的量度。如果接触是欧姆性的，根据定义，存在从一种材料到另一种材料-本例下在硅化物402和硅锗301之间的多数载流子的不受阻碍的转移。这也可以表示为线性的电流-电压特征。在金属-半导体界面的情况下，传导机制部分由邻近于接触界面的半导体耗尽区的宽度规定。如果半导体被稍许掺杂(例如，费米能量既不接近于导带边缘能量也不接近于价带边缘能量)，耗尽区变得足够宽，使得电子在两个接触材料之间转移的唯一方法是通过势垒最大值以上的热离子发射跃过势垒。或者，如果半导体被高度掺杂(费米能量接近n型的导带边缘能量并接近p型的价带边缘能量)，耗尽区变得足够窄，使得场发射或载流子隧穿作为主要的传导机制。场发射和热离子发射两者都贡献跨界面的传导并可以例如通过材料选择和掺杂来调节。
图8示出了使用例如具有镍硅锗硅化物层402的硅锗301源极和漏极区的本发明实施例。外电阻Rext801是源极(或漏极)接触和本征晶体管的沟道之间的总串联电阻。硅锗301和硅化物402之间的界面电阻是该总串联电阻的重要分量。通过使用硅锗与使用p型硅用于源极和漏极区相比减少了Rext801。此外，硅化物层402的难溶金属的合适选择(在一个实施例中是镍)已确保了化学和机械兼容的金属-半导体界面，它不会不利地影响Rext801，如参考图4所述的。
本领域的熟练技术人员将认识到所揭示实施例的优点，其中它通过使用新材料选择和处理技术减少了硅锗源极和漏极区以及它们各自的硅化物接触之间的比接触电阻率。由于接触电阻率影响晶体管的总体外电阻率，所以接触电阻率的减小有助于晶体管中整体性能的提升。

Claims (35)

1.一种晶体管，包括：
栅极区；
所述栅极区下的绝缘体区；
邻近于氧化物区的源极区；
邻近于氧化物区的漏极区；
其中所述源极区和漏极区包括硅锗合金和镍硅锗硅化物层。
2.如权利要求1所述的晶体管，其特征在于，所述源极区和漏极区在绝缘层下横向延伸。
3.如权利要求2所述的晶体管，其特征在于，所述源极区和漏极区在栅极区下横向延伸。
4.如权利要求3所述的晶体管，其特征在于，所述源极区和漏极区在栅极区下在25到200埃之间横向延伸。
5.如权利要求1所述的晶体管，其特征在于，所述源极区和漏极区在硅基片的表面下具有100到1500埃之间的垂直深度。
6.如权利要求1所述的晶体管，其特征在于，硅锗合金具有5％到50％之间的锗组成。
7.如权利要求6所述的晶体管，其特征在于，所述硅锗合金具有10％到40％之间的锗组成。
8.如权利要求7所述的晶体管，其特征在于，所述硅锗合金具有15％到30％之间的锗组成。
9.如权利要求1所述的晶体管，其特征在于，所述硅锗合金被掺杂。
10.如权利要求9所述的晶体管，其特征在于，所述硅锗在硅锗合金沉积期间在原处被掺杂。
11.如权利要求10所述的晶体管，其特征在于，掺杂物是硼。
12.如权利要求11所述的晶体管，其特征在于，掺杂物的来源是B2H6。
13.如权利要求11所述的方法，其特征在于，硼具有1*1018/cm3和3*1021/cm3之间的掺杂浓度水平。
14.如权利要求13所述的方法，其特征在于，所述掺杂浓度水平是1*1020/cm3。
15.如权利要求1所述的晶体管，其特征在于，所述镍硅锗硅化物层是自对准的。
16.一种制造晶体管的设备，包括：
用于蚀刻硅基片中的源极区和漏极区的装置，其中所述蚀刻具有底切轮廓；
用于在所述源极区中和所述漏极区中沉积硅锗合金的装置；
用于在所述硅锗合金上沉积镍的装置；
用于在所述源极区中和在所述漏极区中形成镍硅锗硅化物层的装置，其中所述镍硅锗硅化物层是自对准的，
用于在325℃和450℃之间的温度下将所述基片退火小于或等于60秒的装置；
用于用热H2O2和H2SO4的湿蚀刻化学成分去除过剩的镍的装置；以及
用于在400℃和550℃之间的温度下退火所述基片的装置。
17.如权利要求16所述的设备，其特征在于，所述源极区和漏极区在绝缘层下横向延伸。
18.如权利要求17所述的设备，其特征在于，所述源极区和漏极区在栅极区下横向延伸。
19.如权利要求18所述的设备，其特征在于，所述源极区和漏极区在栅极区下在25到200埃之间横向延伸。
20.如权利要求16所述的设备，其特征在于，所述源极区和漏极区在硅基片的表面下具有100到1500埃之间的垂直深度。
21.如权利要求16所述的设备，其特征在于，所述蚀刻是干SF6基的。
22.如权利要求16所述的设备，其特征在于，硅锗合金具有5％到50％之间的锗组成。
23.如权利要求22所述的设备，其特征在于，所述硅锗合金具有10％到40％之间的锗组成。
24.如权利要求23所述的设备，其特征在于，所述硅锗合金具有15％到30％之间的锗组成。
25.如权利要求16所述的设备，其特征在于，所述硅锗合金的沉积是气相外延。
26.如权利要求16所述的设备，其特征在于，所述硅锗合金的沉积是减小压力的化学气相沉积。
27.如权利要求16所述的设备，其特征在于，所述硅锗合金的沉积是大气化学气相沉积。
28.如权利要求16所述的设备，其特征在于，所述硅锗合金的沉积是超高真空化学气相沉积。
29.如权利要求16所述的设备，其特征在于，沉积硅锗合金进一步包括掺杂所述合金。
30.如权利要求29所述的设备，其特征在于，所述掺杂在沉积硅锗合金期间在原处进行的。
31.如权利要求30所述的设备，其特征在于，掺杂物是硼。
32.如权利要求31所述的设备，其特征在于，掺杂物的来源是B2H6。
33.如权利要求31所述的设备，其特征在于，硼具有1*1018/cm3和3*1021/cm3之间的掺杂浓度水平。
34.如权利要求33所述的设备，其特征在于，所述掺杂浓度水平是1*1020/cm3。
35.如权利要求16所述的设备，其特征在于，所述镍具有50到200埃之间的厚度。
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