TWI387010B - 用於製造電晶體之方法 - Google Patents
用於製造電晶體之方法 Download PDFInfo
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- TWI387010B TWI387010B TW096109919A TW96109919A TWI387010B TW I387010 B TWI387010 B TW I387010B TW 096109919 A TW096109919 A TW 096109919A TW 96109919 A TW96109919 A TW 96109919A TW I387010 B TWI387010 B TW I387010B
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- nickel
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- germanium
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- 238000000034 method Methods 0.000 title claims description 29
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 48
- 238000000151 deposition Methods 0.000 claims description 38
- 229910052732 germanium Inorganic materials 0.000 claims description 36
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 36
- 229910052759 nickel Inorganic materials 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 229910052715 tantalum Inorganic materials 0.000 claims description 27
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 27
- 229910001362 Ta alloys Inorganic materials 0.000 claims description 19
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 10
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 claims description 8
- 229910001257 Nb alloy Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- -1 nickel halide Chemical class 0.000 claims description 5
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 229910052758 niobium Inorganic materials 0.000 claims description 4
- 239000010955 niobium Substances 0.000 claims description 4
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- UNASZPQZIFZUSI-UHFFFAOYSA-N methylidyneniobium Chemical compound [Nb]#C UNASZPQZIFZUSI-UHFFFAOYSA-N 0.000 claims 1
- 230000008021 deposition Effects 0.000 description 19
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 18
- 125000006850 spacer group Chemical group 0.000 description 14
- 239000002019 doping agent Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000013078 crystal Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000003870 refractory metal Substances 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- QJWDYDSKKWMXSO-UHFFFAOYSA-N lanthanum Chemical compound [La].[La] QJWDYDSKKWMXSO-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052797 bismuth Inorganic materials 0.000 description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052746 lanthanum Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 241001674044 Blattodea Species 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 2
- 229910000636 Ce alloy Inorganic materials 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003697 SiBN Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002475 indoles Chemical class 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- FEBJSGQWYJIENF-UHFFFAOYSA-N nickel niobium Chemical compound [Ni].[Nb] FEBJSGQWYJIENF-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本發明係有關半導體積體電路的領域,且特別有關形成一MOS電晶體。
積體電路通常製造於矽及其他半導體基材中及其上。一積體電路係可包括形成於數百平方公分面積上方之數百萬個經互連的電晶體。
此電晶體通常係包括矽基材上之一閘極介電層、閘極介電層上之一閘極電極、及閘極電極的相對側上之矽基材中的源極及汲極區。通常藉由將摻雜物雜質植入矽基材內來製成源極及汲極區。
為了增加電子活動力及成本效益,已經使用矽鍺作為一用於源極及汲極區之材料。鍺具有比矽更大4.2%的晶格常數(譬如原子間隔)。矽鍺亦具有較大晶格常數,其程度依據鍺的百分比組成物而定。當矽成長在矽鍺上時,妥當條件下,矽晶格係拉伸以匹配矽/矽鍺介面處之矽鍺者。當矽鍺成長於矽上時,妥當條件下,矽鍺晶格變成被壓縮。對於各方法,經成長層(不論其為矽或矽鍺)具有臨界厚度,超過該臨界厚度則經成長層隨著晶格瑕疵傳播而放鬆。
因為相較於元素矽而言,鍺具有較低電子有效質量及較低電洞有效質量(導致較高電子活動力及較高電洞活動力),矽鍺對於包含其之電晶體提供經改良的速度特徵。矽鍺化合物可從成份鍺的增加活動力得到利益。並且,矽鍺係生成一將更改材料傳導及價帶之異向性結構。當與具不同帶隙的其他半導體層(譬如,異質層)合併時,可設計傳導帶及價帶不連續性以生成量子井或內建電場以加速載體橫越異質層。
以電晶體效能需求(通常,15%至30%之間)為基礎來選擇磊晶SiGe層中之鍺量。對於自動對準矽化物與源極汲極之間的接觸電阻、且對於均勻的自動對準矽化物形成而言此鍺量可能不是最佳化,而導致降低的良率及效能。
依據本發明之一實施例,係特地提出一種方法,其包含:形成一閘極電極於一基材的一表面上;於該基材中等向地蝕刻一源極區及一汲極區;沉積一矽鍺合金於該源極區中及該汲極區中;在該矽鍺合金上沉積一可犧牲層,該可犧牲層之材料具有比該矽鍺合金之鍺濃度為低的鍺濃度;沉積一金屬於該可犧牲層上;形成一第一矽化物層於該矽鍺合金上;及形成一第二矽化物層於該第一矽化物層上。
依據本發明之一實施例,係特地提出一種方法,其包含:形成一閘極電極於一基材的一表面上;該該基材中等向地蝕刻一源極區及一汲極區;沉積一矽鍺合金於該源極區中及該汲極區中;以硼原位摻雜該矽鍺合金;沉積矽於該矽鍺合金上;沉積鎳於該矽上;及形成一鎳矽矽化物層於該矽鍺合金上;及形成一鎳矽鍺矽化物層於該鎳矽矽化物層上。
依據本發明之一實施例,係特地提出一種電晶體,其包含:一矽基材,其具有一包含第一摻雜物雜質以具有一第一傳導型之通路區;一閘極介電層於該通路區上;一傳導閘極電極於該閘極介電層上;源極及汲極區,其位於該通路區的相對側上,該等源極及汲極區係由一矽鍺合金製成;一鎳矽矽化物層,其形成於該矽鍺合金上;一鎳矽鍺矽化物層,其形成於該鎳矽矽化物層上。
本發明在圖式中藉由範例而非限制作顯示。
第1圖為顯示根據一實施例之相鄰電晶體的橫剖側視圖;第2圖為顯示第1圖的基材中之凹部的形成之橫剖側視圖;第3圖為顯示第2圖的基材之凹部中的一矽鍺合金的形成之橫剖側視圖;第4圖為顯示根據一實施例之第3圖的基材之矽鍺合金上的矽沉積之橫剖側視圖;第5圖為顯示根據一實施例之第4圖的基材上之罩幕的移除之橫剖側視圖;第6圖為顯示根據一實施例之第5圖的基材上之一金屬的沉積之橫剖側視圖;第7圖為顯示根據一實施例之第6圖中金屬反應後之一電晶體的橫剖側視圖;第8圖為顯示根據另一實施例之第3圖的基材上之罩幕的移除之橫剖側視圖;第9圖為顯示根據另一實施例之第8圖的基材上之矽的沉積之橫剖側視圖;第10圖為顯示根據另一實施例之第9圖的基材上之一金屬的沉積之橫剖側視圖;第11圖為顯示根據另一實施例之第10圖中金屬的反應後之一電晶體的橫剖側視圖;第12圖為顯示根據一實施例之一用以製造第7及11圖的電晶體之方法的流程圖。
下文描述提供諸如特定系統、組件、方法等的範例之許多特定細節,以供更加瞭解本發明的數項實施例。然而,熟習該技術者瞭解,本發明的至少部分實施例可以不具有這些特定細節來實施。其他案例中,並不詳述熟知組件或方法或以簡單方塊圖格式代表以免不必要地模糊本發明。因此,提出的特定細節只供示範。特定實行方式可異於這些示範性細節而仍視為位於本發明的精神及範圍內。
本發明的一實施例係對於源極及汲極區利用一矽鍺合金、一金屬矽鍺矽化物層、及一金屬矽矽化物層以形成源極及汲極區的接觸表面來降低一電晶體的外部電阻。金屬可譬如為鎳。矽鍺及鎳矽矽化物之間的介面以矽鍺及鎳矽鍺矽化物之間之一減小的金屬半導體功函數及矽鍺vs.矽之一增加的載體活動力為基礎具有一較低的比接觸電阻率。鎳矽矽化物提供一較好的接觸部形成。矽鍺可被摻雜以進一步調控其電性性質。電晶體之外部電阻降低係等同於切換速度及功率消耗兩者之增加的電晶體效能。
第1圖顯示一矽基材106上之兩相鄰電晶體102、104的製造之一實施例。電晶體102為製作於一p-型基材或井上之一金屬氧化物半導體(MOS)電晶體。電晶體104係為製作於一n-型基材或井上之一金屬氧化物半導體(MOS)電晶體。
第1圖所示經部分製造的電晶體102、104係根據一習知製程來製造。P-型摻雜物被植入矽基材106的左部分內以形成一P-井108。N-型摻雜物被植入矽基材106的右部分內以形成一N-井110。P-井108藉由一諸如二氧化矽淺溝道隔離(STI)區112或亦稱為隔離壁等之隔離區而與N-井110分離。
閘極介電層114、116隨後分別成長在P-井108及N-井110上。閘極介電層114、116可由諸如二氧化矽或經氮化二氧化矽等熟知材料製成。一實施例中,閘極介電層114及116可具有小於約40的厚度。一閘極電極可形成於閘極介電層上。譬如,多晶矽閘極電極118、120可分別形成於閘極介電層114、116上。多晶矽閘極電極118可摻雜一諸如磷或砷等N-型摻雜物。多晶矽閘極電極120可摻雜一諸如硼等P-型摻雜物。
源極汲極延伸部128及130可分別形成於多晶矽閘極電極118及120的相對側上。垂直側壁間隔件122及124亦可分別形成於多晶矽閘極電極118及120的相對側上。根據一實施例,垂直側壁間隔件122及124可由SiO2
或SiBN14
形成。
一罩幕126可形成於電晶體104上。更確切言之,罩幕126係沉積在多晶矽閘極電極120、垂直側壁間隔件124、及N-井110之留存的經曝露表面上。根據一實施例,罩幕126可作為對於進一步處理步驟之一阻絕層。
如第2圖所示,凹部202隨後被蝕刻至P-井108的一上表面內。可使用一等向性蝕刻劑來選擇性地移除S/D延伸部118、120及溝道隔離區112、閘極介電層114、及側壁間隔件122間之經曝露的矽。持續蝕刻直到凹部202的梢部分204形成於閘極介電層114下方為止。就本身而言,源極及汲極凹部202係形成於相對側上及多晶矽閘極電極118下方。源極及汲極凹部202的各者係具有多晶矽閘極電極118下方之一各別梢部分204。一通路區206被界定於梢部分204之間。電晶體104的罩幕126暫時地防止對於電晶體104之進一步製程。
第3圖顯示源極及汲極區形成後之第2圖的結構。可藉由在凹部202內磊晶成長矽鍺以形成一矽鍺層302來形成源極及汲極區。應注意矽鍺選擇性地成長於矽基材106的材料上,而非淺溝道隔離區112、閘極介電層114、側壁間隔件122、及罩幕126之材料上。矽鍺結晶並未成長於SiO2
或Si3
N4
介電層上。一般熟習該技術者將瞭解存在有許多熟知用以沉積矽鍺之技術。譬如,沉積技術可包括降壓化學氣相沉積(CVD)、磊晶沉積。其他沉積技術包括大氣CVD磊晶及超高真空CVD磊晶。由於經沉積的矽鍺層302藉由單晶形成,各沉積技術係為一特定形式的氣相磊晶。一實施例中,矽鍺合金可包括約5%至約50%間之一鍺組成物。
根據一實施例,矽鍺沉積方法係包括CVD磊晶。磊晶可發生於10至760托耳(Torr)之600℃至800℃間。可使用H2
、N2
或He作為一載體氣體。矽源前驅物氣體可為SiH2
Cl2
、SiH4
、或Si2
H6
。一實施例中,GeH4
係為鍺源前驅物氣體。HCl或Cl2
可添加作為蝕刻劑以增加沉積之材料選擇性。一實施例中,所產生的矽鍺層302可被沉積在凹部202中以形成源極及汲極區。矽鍺302的層可具有約500至約2000埃間之厚度。第3圖顯示一其中使經沉積的矽鍺層302延伸於基材106的一頂表面上方之實施例。矽鍺層302形成於基材106的一頂表面上方及下方。藉由將矽鍺層302形成於基材106的頂表面上方,形成一凸起的源極-汲極區,使傳導度增加。經增加的傳導度轉而改良裝置效能。另一實施例中,矽鍺層302可具有約200至約1000埃間之厚度。
矽鍺層302可被摻雜以調整其電性及化學性質。可利用多種不同摻雜物及多種不同摻雜技術發生摻雜。譬如,矽鍺可以諸如硼等p-型雜質作現場摻雜到1×1018
/cm3
至3×1021
/cm3
間之摻雜物濃度位準,其中較佳係為近似1×1020
/cm3
的濃度。一用以製造一PMOS裝置之實施例中,矽鍺在矽鍺磊晶沉積期間利用上述前驅物及一額外B2
H6
前驅物氣體作為硼摻雜物來源之磊晶期間係於現場摻雜硼。現場摻雜矽鍺之利益係在於:由於凹部202的形狀故很難在其已於側壁間隔件122遮蔭的區域中被沉積之後摻雜矽鍺。一般熟習該技術者將瞭解,亦可使用其他技術來摻雜矽鍺層302。
一實施例中,矽鍺沉積期間所添加之硼摻雜物有一比例部分此時並未被活化。亦即,沉積之後,硼原子係位於矽鍺層302中但尚未置換至其中可提供一電洞處(亦即缺乏一電子)之晶格中的矽部位內。一實施例中,摻雜物的熱活化受到阻撓直到後續處理步驟(諸如矽化物退火)為止,故降低熱預算及所產生的摻雜物擴散以能夠形成很驟然的源極/汲極接面,而改善裝置效能。
如介紹,經沉積的矽鍺具有一較大的晶格常數,其量值依據矽鍺合金中的原子百分比鍺而定。當沉積在矽基材106上時,矽鍺的晶格被壓縮以容納晶性成長。用以形成源極及汲極區之矽鍺層302中的壓縮係進一步生成位於矽鍺源極及汲極區之間及閘極介電層114下方(亦即電晶體102的通路206)的矽基材106區中之壓縮。壓縮係生成一異向性原子結構於通路區中,更改了通路材料的傳導及價帶。壓縮性應力進一步降低矽基材106的通路區中之電洞有效質量,轉而增高電洞活動力。經增加的電洞活動力係增大所產生的MOS電晶體之飽和通路電流,藉以改良裝置效能。
第4圖顯示根據一實施例之沉積一可犧牲層之後的第3圖之結構。一實施例中,可犧牲層包括一薄層的矽402,其選擇性地沉積在矽鍺層302的經曝露表面上。應注意矽選擇性地成長在矽鍺層302的材料上,而非淺溝道隔離區112、閘極介電層114、側壁間隔件122、及硬罩幕126之材料上。矽層402未成長於SiO2
或Si3
N4
介電層上。矽層402的厚度可依據沉積於矽層402上之金屬類型及厚度而介於200A至400A之間。一實施例中,沉積技術可包括降壓化學氣相沉積(CVD)磊晶沉積。其他實施例中,沉積技術包括大氣性CVD磊晶及超高真空CVD磊晶。由於經沉積矽層402由單晶形成,各沉積技術係為一特定形式的氣相磊晶。另一實施例中,可犧牲層包括比矽鍺層中的鍺具有更少鍺組成物之矽鍺。譬如,可犧牲層可包括具有最高達到約30%的鍺組成物之矽鍺。
沉積製程可基於下列兩項理由包括將氣體繞佈至通口:(1)用以在所想要的設定點穩定化DCS及HCL流;(2)用以容許溫度爬升至一所想要的溫度(777℃至825℃之間)。
第5圖顯示根據一實施例之自電晶體104移除罩幕126後之第4圖的結構。罩幕126被移除以留下曝露之電晶體104的結構,如第5圖所示。特定言之,電晶體104的經曝露組件係包括源極汲極區130、側壁間隔件124、及閘極電極120。電晶體102的經曝露組件包括矽層402、側壁間隔件122、及閘極電極118。
第6圖顯示一金屬沉積後之第5圖的結構。一諸如鎳等金屬602係沉積在電晶體102及104兩者上。一般熟習該技術者將瞭解,具有許多沉積金屬602之方式。一沉積技術的範例係包括標準濺鍍技術(亦即,物理氣相沉積或“PVD”)。金屬602與電晶體102及104的特定組件起反應。隨後移除尚未與電晶體102及104的組件起反應之金屬602。
第7圖顯示根據一實施例之金屬與第6圖的電晶體102及104起反應後之一電晶體的橫剖側視圖。第7圖亦顯示自動對準矽化物層702及704之形成。熟習該技術者將瞭解,藉由沉積一薄層的耐火金屬來形成一矽化物層。
耐火金屬係包括鈷、鈦及鎳、及其他。一實施例中,耐火金屬為鎳。耐火金屬的選擇不只需要考慮與佔據源極及汲極區的下方矽鍺層302以及相同基材上之對應的NMOS裝置的經曝露源極及汲極區之電性相容性,亦需考慮機械及化學相容性。譬如,矽化物層必須為連續性且均勻以幫助降低矽化物層與下方矽鍺層302之間的介面電阻。鎳傾向於與矽及鍺兩者均勻地起反應,形成一穩定三成份Ni(SiGe)相,而鈷及鈦則優先與矽起反應且離析矽鍺合金302的鍺組份。並且,以鈦及鈷為基礎之矽鍺矽化物比起鎳矽鍺矽化物係具有降低的熱穩定度。不當的耐火金屬選擇將在矽化物與半導體之間生成一不理想介面使得介面電阻增大而與原本電性相容的材料獨立無關。
第7圖顯示一其中耐火金屬為PVD鎳之實施例。就環境來說,PVD鎳沉積發生於小於50毫托耳(millitorr)之20℃至200℃之間。鎳的厚度可為50至200埃之間。鎳沉積後係為譬如利用迅速熱退火(RTA)設備之一小於或等於60秒之325℃至450℃間的迅速形成退火。形成退火期間,矽層402頂上之鎳層602起反應以形成一第一層的鎳矽鍺矽化物702及一第二層的鎳矽矽化物704,如第7圖所示。一實施例中,經沉積的鎳602可具有約200至400埃間之厚度。隨著鎳602沉積於矽基材106的整體經曝露表面上方,利用譬如熱H2
O2
及熱H2
SO4
的一混合物之一濕蝕刻化學作用來移除未起反應的鎳(亦即,沉積於側壁間隔件122或隔離區112頂上時尚未與矽或矽鍺起反應以與其下方層形成一矽化物之鎳)。閘極118以及矽鍺層302(源極及汲極區)頂上之留存的未反應鎳隨後係經歷400℃至550℃間之一最後退火以完成鎳矽鍺矽化物702及鎳矽矽化物704形成,如第7圖所示。矽化物層702及704可進一步覆蓋有譬如一鈦氮化物蓋(未圖示)以防止鎳矽鍺矽化物層702及鎳矽矽化物層704在此技藝所熟知的後續處理步驟期間氧化。一實施例中,各矽化物層可具有200至400埃間之厚度。
第8圖顯示根據另一實施例之從電晶體104移除罩幕126後之第3圖的結構。罩幕126隨後被移除以留下曝露之電晶體104的結構,如第8圖所示。特定言之,電晶體104的經曝露組件係包括源極汲極區130、側壁間隔件124、及閘極電極120。
第9圖顯示根據一實施例之一可犧牲層沉積後之第8圖的結構。可犧牲層可譬如包括矽。一薄層的矽902選擇性地沉積在電晶體106的矽鍺層302之經曝露表面上。一薄層的矽902係沉積在電晶體104的源極汲極區130之經曝露表面上。矽層902的厚度可依據矽層902上所沉積的金屬類型及厚度而介於從200A至400A。參照第4圖先行描述矽902層的沉積製程。
第10圖顯示一諸如鎳等金屬1002沉積後之第9圖的結構。參照第6圖先行描述金屬層1002的沉積製程。
第11圖顯示金屬已與電晶體102及104起反應後之第10圖的結構。參照第7圖先行描述反應製程。
第12圖為顯示一用以製造第7及11圖的電晶體之方法的流程圖。在1202,形成一閘極電極,如第1圖所示。在1204,源極及汲極區被蝕刻於基材中,如第2圖所示。在1206,一矽鍺合金沉積於源極及汲極區中,如第3圖所示。在1208,一可犧牲層的一材料係沉積於矽鍺合金上,如第4及9圖所示。一實施例中,可犧牲層包括矽。在1210,一諸如鎳等金屬係沉積在可犧牲層上,如第6及10圖所示。金屬及可犧牲層及矽鍺合金之間的接觸係形成兩層的矽化物。在1212,金屬與矽鍺起反應以形成一第一層的矽化物。一實施例中,第一層的矽化物係包括鎳與矽鍺起反應所形成之鎳矽鍺矽化物。在1214,金屬與可犧牲層起反應以形成一第二層的矽化物。一實施例中,第二層的矽化物係包括鎳與矽起反應所形成之鎳矽矽化物。
雖然此處以一特定次序顯示及描述一(或多)個方法的操作,可更改各方法的操作次序故可以一相反次序來進行特定操作或可至少部分地與其他操作同時進行特定操作。另一實施例中,不同操作的次操作或指令可處於一間歇及/或交錯方式。
上文說明書中,已經參照本發明的特定示範性實施例來描述本發明。然而,顯然可作出不同修改及改變而不脫離申請專利範圍所界定之本發明的較寬廣精神與範圍。為此,說明書及圖式被視為示範性意義而非限制性意義。
102,104...電晶體
106...矽基材
108...P-井
110...N-井
112...二氧化矽淺溝道隔離(STI)區
114,116...閘極介電層
118,120...多晶矽閘極電極
122,124...垂直側壁間隔件
126...硬罩幕
128,130...源極汲極延伸部
202...凹部
204...凹部的梢部分
206...通路,通路區
302...矽鍺層
402,902...矽層
602...金屬,鎳層
702...第一層的鎳矽鍺矽化物,自動對準矽化物層
704...第二層的鎳矽矽化物,自動對準矽化物層
1202,1204,1206,1208,1210,1212,1214...步驟
第1圖為顯示根據一實施例之相鄰電晶體的橫剖側視圖;第2圖為顯示第1圖的基材中之凹部的形成之橫剖側視圖;第3圖為顯示第2圖的基材之凹部中的一矽鍺合金的形成之橫剖側視圖;第4圖為顯示根據一實施例之第3圖的基材之矽鍺合金上的矽沉積之橫剖側視圖;第5圖為顯示根據一實施例之第4圖的基材上之罩幕的移除之橫剖側視圖;第6圖為顯示根據一實施例之第5圖的基材上之一金屬的沉積之橫剖側視圖;第7圖為顯示根據一實施例之第6圖中金屬反應後之一電晶體的橫剖側視圖;第8圖為顯示根據另一實施例之第3圖的基材上之罩幕的移除之橫剖側視圖;第9圖為顯示根據另一實施例之第8圖的基材上之矽的沉積之橫剖側視圖;第10圖為顯示根據另一實施例之第9圖的基材上之一金屬的沉積之橫剖側視圖;第11圖為顯示根據另一實施例之第10圖中金屬的反應後之一電晶體的橫剖側視圖;第12圖為顯示根據一實施例之一用以製造第7及11圖的電晶體之方法的流程圖。
102,104...電晶體
106...矽基材
108...P-井
110...N-井
112...二氧化矽淺溝道隔離(STI)區
114,116...閘極介電層
118,120...多晶矽閘極電極
122,124...垂直側壁間隔件
126...硬罩幕
128,130...源極汲極延伸部
Claims (16)
- 一種用於製造電晶體之方法,其包含下列步驟:形成一閘極電極於一基材的一表面上;於該基材中等向地蝕刻一源極區及一汲極區;沉積一矽鍺合金於該源極區中及該汲極區中;在該矽鍺合金上沉積一可犧牲層,該可犧牲層之材料具有比該矽鍺合金之鍺濃度為低的鍺濃度;沉積一金屬於該可犧牲層上;形成一第一矽化物層於該矽鍺合金上;及形成一第二矽化物層於該第一矽化物層上。
- 如申請專利範圍第1項之方法,其進一步包含以硼原位摻雜該矽鍺合金的步驟。
- 如申請專利範圍第1項之方法,其中該矽鍺合金係具有一位於該基材的表面所界定的一平面上方之頂表面。
- 如申請專利範圍第1項之方法,其中該矽鍺合金所具有之鍺成份係在約5%至約50%之間。
- 如申請專利範圍第1項之方法,其中該矽鍺合金所具有之厚度係在約200至約1000埃之間。
- 如申請專利範圍第1項之方法,其中該可犧牲層包括矽。
- 如申請專利範圍第6項之方法,其中該矽所具有之厚度係在約200至約400埃之間。
- 如申請專利範圍第1項之方法,其中該可犧牲層包括具有上至30%之鍺成份的矽鍺。
- 如申請專利範圍第1項之方法,其中該金屬包括鎳。
- 如申請專利範圍第9項之方法,其中該鎳所具有之厚度係在約200至約400埃之間。
- 如申請專利範圍第9項之方法,其中該第一矽化物層包括一鎳矽鍺矽化物。
- 如申請專利範圍第11項之方法,其中該鎳矽鍺矽化物所具有之厚度係在約200至約400埃之間。
- 如申請專利範圍第9項之方法,其中該第二矽化物層包括一鎳矽矽化物。
- 如申請專利範圍第13項之方法,其中該鎳矽矽化物所具有之厚度係在約200至約400埃之間。
- 一種用於製造電晶體之方法,其包含下列步驟:形成一閘極電極於一基材的一表面上;於該基材中等向地蝕刻一源極區及一汲極區;沉積一矽鍺合金於該源極區中及該汲極區中;以硼原位摻雜該矽鍺合金;沉積矽於該矽鍺合金上;沉積鎳於該矽上;及形成一鎳矽矽化物層於該矽鍺合金上;及形成一鎳矽鍺矽化物層於該鎳矽矽化物層上。
- 如申請專利範圍第15項之方法,其中該矽鍺合金係具有一位於該基材之該表面所界定的一平面上方之頂表面。
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KR101561059B1 (ko) * | 2008-11-20 | 2015-10-16 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US8598003B2 (en) * | 2009-12-21 | 2013-12-03 | Intel Corporation | Semiconductor device having doped epitaxial region and its methods of fabrication |
US9484432B2 (en) * | 2010-12-21 | 2016-11-01 | Intel Corporation | Contact resistance reduction employing germanium overlayer pre-contact metalization |
US8901537B2 (en) | 2010-12-21 | 2014-12-02 | Intel Corporation | Transistors with high concentration of boron doped germanium |
FR2989517B1 (fr) * | 2012-04-12 | 2015-01-16 | Commissariat Energie Atomique | Reprise de contact sur substrat semi-conducteur heterogene |
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US20070238236A1 (en) | 2007-10-11 |
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