TWI483399B - 具有無尖端磊晶源極／汲極區域之半導體裝置 - Google Patents

具有無尖端磊晶源極／汲極區域之半導體裝置 Download PDF

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TWI483399B
TWI483399B TW097116826A TW97116826A TWI483399B TW I483399 B TWI483399 B TW I483399B TW 097116826 A TW097116826 A TW 097116826A TW 97116826 A TW97116826 A TW 97116826A TW I483399 B TWI483399 B TW I483399B
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source
channel region
drain regions
substrate
gate
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TW200913274A (en
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Mark Bohr
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Intel Corp
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Description

具有無尖端磊晶源極/汲極區域之半導體裝置
本發明有關於半導體裝置的領域。
近年來，已藉由將應變通道區域包含在半導體基底之主動部分中而大幅改善半導體裝置(如金屬氧化物半導體場效應電晶體(MOS-FETs))之性能，例如使用壓縮式應變矽通道區域來改善P型金氧半導體場效電晶體(PMOS-FETs)的電洞遷移率。此種應變通道區域的存在可在半導體裝置處於啟通(ON)狀態時，大幅增進電荷於通道中遷移的速度。
第1A至C圖描繪代表根據先前技術於PMOS-FET中形成引起應變的源極/汲極區域之典型程序流程的剖面圖。參照第1A圖，首先形成非應變PMOS-FET 100。非應變PMOS-FET 100是由通道區域102構成。閘極介電質層104坐落於通道區域102上方並且閘極電極106坐落於閘極介電質層104上方。藉由閘極孤立間隔體108孤立閘極介電質層104與閘極電極106。藉由佈植摻雜原子到基底114中形成尖端延伸110及源極/汲極區域112，且部分形成以減少非應變PMOS-FET 100的寄生電阻。因此，源極/汲極區域112一開始是由與通道區域102相同的材料所形成。故，源極/汲極區域112與通道區域102間之晶格不匹配微不足道，因而不會在通道區域102上實際產生 應變。
參照第1B圖，藉由一蝕刻程序移除基底114的一部分，包括源極/汲極區域112，以在基底114中形成凹陷區域116。接著，藉由選擇性生長磊晶薄膜於凹陷區域116之中而形成引起應變之源極/汲極區域120，如第1C圖中所示。引起應變之源極/汲極區域120可摻雜有電荷-載體原子，如在PMOS-FET的情況中硼，此可原位地或於磊晶薄膜生長之後進行，或兩者皆進行。在一範例中，基底114，及因而通道區域102，係由結晶矽所構成，並且生長而形成引起應變之源極/汲極區域112的薄膜係由磊晶矽/鍺所形成。磊晶矽/鍺之晶格常數比結晶矽的大～1%(針對70% Si 30% Ge)，因此引起應變之源極/汲極區域120係由具有比通道區域102更大之晶格常數的材料所構成。故，由第1C圖中之箭頭所示，於應變PMOS-FET130中的通道區域102上發生單軸壓縮應變，其可增進裝置中之電洞遷移率。
此種方法的一項缺點在於需要閘極孤立間隔體108，以在形成引起應變之源極/汲極區域120之磊晶薄膜生長期間，禁止在閘極電極106上生長不希望之材料，例如禁止在多晶矽閘極電極上生長矽/鍺。引起應變源極/汲極區域120相較於通道區域102的位置因此受限於閘極孤立間隔體108的寬度。故，減少寄生電阻的能力並且引起應變之源極/汲極區域120之引起應變的能力有限。可在基底114中形成尖端延伸110以減少應變PMOS-FET 130的電 阻。然而，以和通道區域102相同的材料形成尖端延伸110。因此，尖端延伸110與通道區域102間之晶格不匹配微不足道，因而尖端延伸110不會在通道區域102上實際產生額外的應變。
故，在此描述具有無尖端磊晶源極/汲極區域之半導體裝置及其之形成方法。
描述具有無尖端磊晶源極/汲極區域之半導體裝置及其之形成方法。在下列說明中，提出各種特定細節，如特定尺寸及化學狀態，以提供本發明之詳盡的了解。對熟悉此技藝者而言很明顯地可在無這些特定細節的情況下實施本發明。在其他例子中，並未詳細描述如圖案化步驟或濕化學清除之眾所週知的製程步驟，以不非必要地模糊本發明。此外，應了解到圖中所示之各種實施例僅為例示性且非絕對按比例繪製。
在此揭露具有無尖端磊晶源極/汲極區域之半導體裝置及形成此種裝置之方法。在一實施例中，半導體裝置包含於基底上之閘極堆疊。閘極堆疊是由閘極電極構成，其在閘極介電質層上，並可在基底中的通道區域上。在一實施例中，半導體裝置亦包含於基底中在通道區域的兩側之一對源極/汲極區域。該對源極/汲極區域可與閘極介電質層直接接觸，並且該對源極/汲極區域的晶格常數可與通道區域的晶格常數不同。在一特定實施例中，半導體裝置 可用介電質閘極堆疊佔位件形成半導體裝置。
包含無尖端磊晶源極/汲極區域之半導體裝置可因此種源極/汲極區域的應變引起能力的增加而呈現出改善的性能。換言之，在無閘極孤立間隔體的情況下形成引起應變之源極/汲極區域得直接在閘極堆疊旁形成引起應變之源極/汲極區域，且因此更靠近閘極堆疊下方的通道區域。故，根據本發明之一實施例，形成與半導體裝置的閘極介電質層直接接觸的引起應變之源極/汲極區域，使引起應變之源極/汲極區域能最靠近半導體裝置的通道區域。在一實施例中，此結構上的配置在半導體裝置為啟通狀態時增加通道區域中電荷-載體的遷移率。在一特定實施例中，此結構上的配置無需尖端延伸，因為藉由在通道區域附近形成引起應變之源極/汲極區域而緩和寄生電阻。
可藉由在取代閘極方法中使用介電質閘極堆疊佔位件來進行直接在閘極堆疊旁形成引起應變之源極/汲極區域。因此，根據本發明之一實施例，禁止在介電質閘極堆疊佔位件上生長材料，而無需在製造引起應變之源極/汲極區域的期間有閘極孤立間隔體。在一實施例中，介電質閘極堆疊佔位件在形成引起硬變得磊晶源極/汲極區域之後以真實的閘極堆疊加以取代。
可形成磊晶源極/汲極區域與閘極堆疊直接接觸的半導體裝置。第2圖描繪代表具有無尖端之磊晶源極/汲極區域的平面MOS-FET的剖面圖。
參照第2圖，半導體裝置200是由具有通道區域204之基底202所構成。閘極堆疊是由構成閘極介電質層206及坐落於通道區域204上方的閘極電極218所構成。引起應變之磊晶源極/汲極區域208形成於基底202中通道區域204的兩側上並底切通道區域204。引起應變之磊晶源極/汲極區域208與閘極堆疊直接接觸，尤其閘極介電質層206。層間介電質薄膜210形成於引起應變之磊晶源極/汲極區域208之上並且與閘極堆疊的側壁直接接觸。
半導體裝置200可為包含閘極、通道區域及一對源極/汲極區域之任何半導體裝置。根據本發明之一實施例，半導體裝置200選自由平面MOS-FET、記憶體電晶體或微電機系統所組成之群組。在一實施例中，半導體裝置200為平面MOS-FET，並且為孤立的裝置或複數個成堆裝置中的一裝置。在一特定實施例中，半導體裝置為平面孤立PMOS-FET，具有在引起應變之磊晶源極/汲極區域208兩側的孤立區域214，如第2圖中所示。可理解到針對典型的積體電路，可在單一基底上製造N型與P型通道電晶體以形成CMOS積體電路。
基底202，以及因而通道區域204可由能承受製程且其中可遷移電荷的任何半導體材料構成。在一實施例中，基底202是由結晶矽、矽/鍺或摻雜電荷載體之鍺層所構成，該電荷載體例如但不限於磷、砷、硼或上述之結合。在一實施例中，基底202中之矽原子的濃度大於97%。在另一實施例中，基底202是由分別的結晶基底上方之一磊 晶層所構成，如在摻雜硼之大塊矽單晶基底上方生長之矽磊晶層。基底202亦可包含在大塊晶體基底與磊晶層之間的絕緣層，以例如形成絕緣體上覆矽之基底。在一實施例中，絕緣層是由選自由二氧化矽、氮化矽、氧氮化矽或高k介電質層所組成之群組所構成。基底202可替代地包含三-五族材料。在一實施例中，基底202是由三-五族材料構成，例如但不限於，氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、砷化銦鎵、砷化鋁鎵、磷化銦鎵、或上述之結合。通道區域204可形成在電荷-載體摻雜物雜質原子之井中。在一實施例中，基底202是由結晶矽所構成，並且電荷-載體摻雜物雜質原子選自由碳、矽、鍺、氧、硫、硒或碲所組成之群組。
引起應變之磊晶源極/汲極區域208可由低缺陷密度單晶薄膜所構成，其具有與基底202之晶格常數不同的晶格常數。晶格常數係根據通道區域204及引起應變之磊晶源極/汲極區域208的每一個之內的原子間隔及晶胞方位。因此，形成在結晶基底之內且具有與結晶基底不同之晶格常數的一對半導體區域會在該對半導體區域之間中的結晶基底部分造成單軸應變。例如，根據本發明之一實施例，引起應變之磊晶源極/汲極區域208的晶格常數大於通道區域的晶格常數並且對通道區域204造成單軸壓縮應變。因此，當引起應變之磊晶源極/汲極區域208的晶格常數大於通道區域204的晶格常數時，引起應變之磊晶源極/汲極區域208之形成晶格的原子會從其正常靜止狀態 推擠在一起，並當嘗試放鬆時對通道區域204造成壓縮應變。在一特定實施例中，在通道區域204上引起之此單軸壓縮應變增加通道區域204中之電洞遷移率。在本發明之一替代實施例中，引起應變之磊晶源極/汲極區域208之晶格常數小於通道區域204的晶格常數，並對通道區域204之晶格造成伸張應變。因此，當引起應變之磊晶源極/汲極區域208之晶格常數小於通道區域204的晶格常數時，引起應變之磊晶源極/汲極區域208之形成晶格的原子會從其正常靜止狀態拉扯開來，並當嘗試放鬆時對通道區域204造成伸張應變。在一特定實施例中，在通道區域204上引起之此單軸壓縮應變增加通道區域204中之電洞遷移率。
引起應變之磊晶源極/汲極區域208可由具有與通道區域204之晶格常數不同的晶格常數且具有電阻性低到足以緩和寄生電阻之任何材料所構成。在一實施例中，通道區域是由Six Ge1-x 所構成，並且引起應變之磊晶源極/汲極區域208是由Siy Ge1-y 所構成，其中0≦x,y≦1以及x≠y。在一特定實施例中，半導體裝置200為PMOS-FET，通道區域是由矽所構成(亦即x=1)並且引起應變之磊晶源極/汲極區域208是由具有70:30原子比例之矽/鍺所構成(亦即y=0.7)。在另一實施例中，通道區域204是由矽所構成，並且引起應變之磊晶源極/汲極區域208是由摻雜碳之矽所構成。在一特定實施例中，半導體裝置200為NMOS-FET，通道區域204是由矽所構成，並且引 起應變之磊晶源極/汲極區域208是由具有替換碳原子在0.5至1.5%範圍之中的原子濃度的摻雜碳之矽所構成。在一替代實施例中，通道區域204是由三-五族材料所構成，選自由Alx Ga1-X As、Inx Ga1-x As、Inx Ga1-x P或Alx In1-x Sb所組成之群組，並且引起應變之磊晶源極/汲極區域208分別由Aly Ga1-y As、Iny Ga1-y As、Iny Ga1-y P或Aly In1-y Sb所構成，其中0≦x,y≦1以及x≠y。在一特定實施例中，源極/汲極區域208是由具有與通道區域204之晶格常數至少差0.1%的晶格常數之材料所構成。
引起應變之磊晶源極/汲極區域208可進一步包含電荷-載體摻雜物雜質原子。在一實施例中，引起應變之磊晶源極/汲極區域208是由磊晶矽/鍺所構成，並且電荷-載體摻雜物雜質原子為硼原子。在一特定實施例中，半導體裝置200為PMOS-FET，通道區域204是由矽構成，並且引起應變之磊晶源極/汲極區域208是由具有在20至35%範圍內之鍺原子濃度並且在5×1019 至5×1020 原子/立方公分範圍的硼摻雜物雜質原子濃度內之矽/鍺所構成。在另一實施例中，引起應變之磊晶源極/汲極區域208是由三-五族材料所構成，並且電荷-載體摻雜物雜質原子選自由碳、矽、鍺、氧、硫、硒或碲所組成之群組。從引起應變之磊晶源極/汲極區域208並且在基底202中之外擴散區域212可形成在引起應變之磊晶源極/汲極區域208的周圍旁，如第2圖中所示。在一實施例中，引起應變之磊晶源極/汲極區域208是由摻雜硼的矽/鍺所構成並且外 擴散區域212是由硼原子所構成。在一特定實施例中，在外擴散區域212中之硼原子的濃度在1×1017 至5×1020 原子/立方公分的範圍內。
與引起應變之磊晶源極/汲極區域208直接接觸並且由閘極介電質層206及在通道區域204上方的閘極電極218所構成之閘極堆疊可為任何材料堆疊，其具有導電區域以及在通道區域204及閘極堆疊之間的介電質層。在一實施例中，閘極介電質層僅形成在閘極電極218及通道區域204之間。在另一實施例中，閘極介電質層延著閘極電極218的側壁延伸並直接與層間介電質薄膜210相鄰，如第2圖中所示。
閘極介電質層206可包含任何介電質材料，適合將導電區域218與通道區域204絕緣。例如，根據本發明之一實施例，閘極介電質層206是由高k介電質層所構成。在一實施例中，高k介電質層選自由氧化鉿、氧氮化鉿、矽酸鉿、氧化鑭、氧化鉻、矽酸鉻、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅或上述之結合組成之群組。此外，閘極介電質層206的一部分可包含一層天然氧化物，從基底202的上幾層形成而來。在一實施例中，閘極介電質層206是由上高k部分及由半導體材料的氧化物構成之下部分所構成。在一實施例中，閘極介電質層206是由氧化鉿之上部分及二氧化矽或氧氮化矽之下部分所構成。在一替代實施例中，閘極介電質層206實質上是由基底202之半導體材料的氧化物層所 構成。在一特定實施例中，基底202實質上是由矽所構成，並且閘極介電質層206實質上是由二氧化矽或氧氮化矽所構成。
閘極電極218可由具有適當工作函數之任何導電材料所構成。在一實施例中，閘極電極218為金屬電極。在一實施例中，閘極電極218是由選自由金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鉻、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳或如氧化釕之導電金屬氧化物所組成之群組的金屬層所構成。在一特定實施例中，閘極電極218是由形成於金屬工作函數設定層上方的非工作函數設定填充材料所構成。在一替代實施例中，閘極電極218是由經摻雜的多晶矽所構成。
層間介電質薄膜210覆蓋引起應變之磊晶源極/汲極區域208並且與閘極堆疊直接相鄰。層間介電質薄膜可由適合承受在半導體裝置200上方製造複數個互連同時維持半導體裝置200與任何附近的半導體裝置間之電性隔離的任何材料所構成。在一實施例中，層間介電質薄膜210是由二氧化矽或氧氮化矽所構成。在另一實施例中，層間介電質薄膜210是由低k介電質材料所構成。在一特定實施例中，層間介電質薄膜210是由具有在2.5至4範圍內之介電質常數的摻雜碳之二氧化矽所構成。
可藉由以替代閘極整合方式使用介電質閘極堆疊而將無尖端引起應變之磊晶源極/汲極區域包含入半導體裝置中。第3A至J圖描繪代表根據本發明之一實施例的具有 無尖端引起應變之磊晶源極/汲極區域的平面MOS-FET的形成之剖面圖。
參照第3A圖，在基底302上形成預先圖案化之介電質閘極堆疊佔位層330。基底302可為連圖來自第2圖之基底202所述之任何基底。根據本發明之一實施例，孤立區域314包含入基底302中，如第3A圖中所示。在一特定實施例中，孤立區域314實質上是由二氧化矽所構成，並且以淺溝渠孤立(STI)整合方式製造。
預先圖案化之介電質閘極堆疊佔位層330可由任何適合對基底302及孤立區域314選擇性圖案化，並且適合在後續磊晶沈積程序期間禁止半導體材料生長之任何介電質材料構成。在一實施例中，預先圖案化之介電質閘極堆疊佔位層330是由選自由二氧化矽、氧氮化矽、及氮化矽所組成之材料所構成。在一特定實施例中，基底302實質上是由矽所構成、孤立區域314是由二氧化矽所構成，並且預先圖案化之介電質閘極堆疊佔位層330實質上是由氮化矽所構成。可在預先圖案化之介電質閘極堆疊佔位層330與基底302之間納入保護層。在一實施例中，在預先圖案化之介電質閘極堆疊佔位層330與基底302之間形成二氧化矽天然層。然而，在一替代實施例中，預先圖案化之介電質閘極堆疊佔位層330直接形成在基底302的上表面上，如第3A圖中所示。因此，在一實施例中，在替代閘極整合方法中不需單獨的閘極介電質堆疊佔位件。
預先圖案化之介電質閘極堆疊佔位層330可由適合在 基底302的上表面上方提供可靠的(亦即均勻成分與厚度)介電質層的任何技術沈積。根據本發明之一實施例，由化學蒸氣沈積(CVD)程序形成預先圖案化之介電質閘極堆疊佔位層330。在一實施例中，預先圖案化之介電質閘極堆疊佔位層330是由化學計量之氮化矽(Si3 N4 )，並且是由CVD程序沈積，其中利用先質SiH4 及NH3 並且在攝氏500至850度範圍中之溫度。預先圖案化之介電質閘極堆疊佔位層330可沈積至適合界定後續形成之閘極堆疊的高度之任何厚度。根據本發明之一實施例，預先圖案化之介電質閘極堆疊佔位層330沈積至50至200奈米範圍中之厚度。
參照第3B圖，將預先圖案化之介電質閘極堆疊佔位層330圖案化以形成閘極堆疊佔位件332，而不實質影響基底302或孤立區域314。根據本發明之一實施例，使用微影/蝕刻程序來提供閘極堆疊佔位件332。例如，在一實施例中，藉由先在預先圖案化之介電質閘極堆疊佔位層330上以選自由248 nm、193 nm及157 nm所組成的群組之光的波長加以暴露而圖案化一正光阻層來圖案化預先圖案化之介電質閘極堆疊佔位層330。在另一實施例中，使用e光束直接寫入程序來圖案化正光阻層。接著使用蝕刻程序將預先圖案化之介電質閘極堆疊佔位層330圖案化。在一實施例中，使用乾蝕刻程序。在一特定實施例中，預先圖案化之介電質閘極堆疊佔位層330實質上是由矽構成，並且乾蝕刻程序包含各向異性電漿蝕刻程序，其中從 HBr及Cl2 所組成之群組選擇之氣體產生電漿。在一實施例中，於正光阻層與預先圖案化之介電質閘極堆疊佔位層330之間利用硬遮罩層。可將閘極堆疊佔位件332圖案化至任何適合提供基底302中具有希望的通道寬度之通道區域的任何寬度。換言之，閘極堆疊佔位件332的寬度後續將決定基底302上方之閘極堆疊的寬度。在一實施例中，閘極堆疊佔位件332的寬度為用來圖案化預先圖案化之介電質閘極堆疊佔位層330之微影程序的關鍵尺寸的寬度。在另一實施例中，閘極堆疊佔位件332的寬度在5至500奈米的範圍中。在一特定實施例中，閘極堆疊佔位件332的寬度在10至100奈米的範圍中。
參照第3C及3C'圖，於基底302中形成蝕刻掉區域340及340'，其中選擇性不蝕刻閘極堆疊佔位件332與孤立區域314。可以適合選擇性蝕刻基底302之一部分並底切閘極堆疊佔位件332之任何技術形成蝕刻掉區域340及340'。在一實施例中，藉由以乾蝕刻程序、濕蝕刻程序或上述之結合來蝕刻任何基底302暴露的部份而形成蝕刻掉區域340及340'。在一實施例中，藉由使用從由NF3 或SF6 所組成之氣體選擇而來的電漿的乾蝕刻程序來形成蝕刻掉區域340，以形成等向蝕刻掉區域340，如第3C圖中所示。濕蝕刻可為各向異性，亦即蝕刻率在高晶體密度的方向中明顯較慢。例如，在一特定實施例中，在(100)矽基底中由<111>晶面阻礙濕蝕刻，而提供具有大約55度的底切輪廓之蝕刻掉區域340'，如第3C'圖中所示。可藉 由首先進行簡短的乾蝕刻後進行各向異性濕蝕刻程序來增加介電質閘極堆疊佔位件332下方之底切的程度。蝕刻掉區域340及340'可具有適合界定磊晶生長之引起應變源極/汲極區域的深度之任何深度。在一實施例中，蝕刻掉區域340及340'之深度在50至150奈米範圍中。蝕刻掉區域340及340'底切閘極堆疊佔位件332的量可為適合使後續形成的半導體裝置之性能最佳化的量。在一實施例中，蝕刻掉區域340及340'在閘極堆疊佔位件332兩側底切閘極堆疊佔位件332的量為閘極堆疊佔位件332之剖面寬度的2至20%。
參照第3D及3D'圖，分別在蝕刻掉區域340及340'之中形成引起應變的磊晶源極/汲極區域308及308'，並因此在基底302中界定一通道區域304。引起應變的磊晶源極/汲極區域308及308'可由與第2圖之引起應變的磊晶源極/汲極區域208關連描述之任何材料所構成。此外，根據本發明之一實施例，引起應變的磊晶源極/汲極區域308及308'可具有與通道區域304之晶格常數不同的晶格常數。因此，在一實施例中，對通道區域304造成單軸應變。在一特定實施例中，引起應變的磊晶源極/汲極區域308及308'的上表面高於通道區域304的上表面，如第3D及3D'圖中所示。
引起應變的磊晶源極/汲極區域308及308'可由適合形成高度均勻且低缺陷的磊晶層之任何技術所形成。詳言之，可藉由不會在極性介電質表面上沈積任何材料的程序 來形成引起應變的磊晶源極/汲極區域308及308'。因此，根據本發明之一實施例，可用完全選擇性沈積程序來於基底302中形成引起應變的磊晶源極/汲極區域308及308'。在一實施例中，藉由選自由化學蒸氣磊晶、分子束磊晶或雷射消滅磊晶組成之群組的程序沈積引起應變的磊晶源極/汲極區域308及308'。在一實施例中，引起應變的磊晶源極/汲極區域308及308'是由矽/鍺所構成並用先質SiH4 及GeH4 沈積。在一實施例中，濕化學清除程序步驟包含施加氫氟酸、氟化氨或兩者的水溶液至矽基底302。在本發明之一特定實施例中，在沈積了引起應變的磊晶源極/汲極區域308及308'，外擴散區312可形成於引起應變的磊晶源極/汲極區域308周圍旁，如第3D及3D'圖中所示。在一實施例，外擴散區312為用來沈積引起應變的磊晶源極/汲極區域308及308'之沈積溫度的結果。為了方便，具有引起應變的磊晶源極/汲極區域308'之第3D'圖的結構亦顯示在所有接下來的第3E至J圖中。
參照第3E圖，在孤立區域314、引起應變的磊晶源極/汲極區域308'及介電質閘極堆疊佔位件332之上沈積覆被介電質薄膜350。覆被介電質薄膜350可由與第2圖之層間介電質薄膜210關連描述之任何材料所構成。可由在孤立區域314、引起應變的磊晶源極/汲極區域308'及介電質閘極堆疊佔位件332之上提供實質上保角薄膜的任何技術沈積覆被介電質薄膜350。在一實施例中，由選自 由CVD程序及旋塗程序所組成之群組的技術沈積覆被介電質薄膜350。覆被介電質薄膜350可沈積至適合完全覆蓋孤立區域314、引起應變的磊晶源極/汲極區域308'及介電質閘極堆疊佔位件332的任何厚度。在一實施例中，沈積覆被介電質薄膜350至250至400奈米範圍內之厚度。
參照第3F圖，將覆被介電質薄膜350平坦化以形成層間介電質薄膜310並且暴露出閘極堆疊佔位件332的上表面。可藉由適合提供層間介電質薄膜310實質上扁平表面而不會低於介電質閘極堆疊佔位件332的上表面之任何技術平坦化覆被介電質薄膜350。在一實施例，利用時控之平坦化步驟。在另一實施例中，用化學機械研磨步驟來平坦化覆被介電質薄膜350，並且介電質閘極堆疊佔位件332的上表面作為止研磨指標。
參照第3G圖，移除介電質閘極堆疊佔位件332以在層間介電質薄膜310之中、通道區域340之上及直接相鄰引起應變磊晶源極/汲極區域308'的溝渠360。可藉由適合影響層間介電質薄膜310、通道區域304及引起應變磊晶源極/汲極區域308'的暴露表面最小之任何技術移除介電質閘極堆疊佔位件。根據本發明之一實施例，藉由使用乾或濕蝕刻程序步驟來移除介電質閘極堆疊佔位件332。在一實施例中，介電質閘極堆疊佔位件332實質上是由氮化矽所構成、層間介電質薄膜310是由二氧化矽所構成、通道區域304是由矽所構成、引起應變磊晶源極/汲極區 域308'是由矽/鍺所構成，並使用利用至少氣體HBr的乾蝕刻程序來移除介電質閘極堆疊佔位件332。在另一實施例中，藉由使用具有在攝氏130至165度之溫度的水磷酸所構成之濕蝕刻移除介電質閘極堆疊佔位件332。在一特定實施例，在介電質閘極堆疊332與通道區域304之間使用薄二氧化矽層作為止蝕刻件。後續藉由包含超稀釋水HF的快速濕蝕刻步驟來移除薄二氧化矽層。
參照第3H圖，於溝渠360中通道區域304之上並與引起應變磊晶源極/汲極區域308'直接接觸地沈積閘極介電質層306。閘極介電質層306可由與第2圖之閘極介電質層206關聯描述的任何材料或材料結合所構成。可由提供通道區域304之暴露的表面之實質上保角覆蓋的任何技術來沈積閘極介電質層306。此外，可由提供層間介電質薄膜310的側壁之保角覆蓋之任何技術來沈積閘極介電質層306，如第3H圖中所示。根據本發明之一實施例，藉由選自由原子層沈積、化學蒸氣沈積及通道區域304的上表面之熱消耗組成之群組的技術來沈積閘極介電質層306。可將閘極介電質層沈積至適合形成與通道區域304之高性能電容器及後續形成之閘極電極的任何厚度。在一實施例中，閘極介電質層是由具有10至60埃範圍內之厚度的高k介電質層所構成。在一特定實施例中，閘極介電質層是由具有5至40埃範圍內之厚度的氧化鉿上層以及具有3至6埃範圍內之厚度的二氧化矽下層所構成。在一替代實施例中，在來自第2圖之預先圖案化的介電質閘極 堆疊佔位件層330與基底302之間形成閘極介電質層。後續圖案化閘極介電質層並執行與第3B至G圖關連描述的所有程序。
參照第3I圖，在閘極介電質層306的上表面上及溝渠360中形成導電層370。導電層370可由與第2圖之閘極電極218關連描述的任何材料所構成。在一實施例中，導電層370是由大塊溝渠填充部分之下的薄工作函數設定部分所構成。導電層370可由任何技術加以沈積，並且能以最不會形成孔洞的方式實質上填充溝渠360。在一實施例中，可由選自由電沈積、無電電鍍、原子蒸氣沈積、化學蒸氣沈積及物理蒸氣沈積組成之群組的技術沈積導電層370。
參照第3J圖，移除在層間介電質薄膜310之上的閘極介電質層306及導電層370的部份，以提供閘極電極318。可藉由適合提供層間介電質薄膜310的實質上平坦表面的任何技術來移除在層間介電質薄膜310之上的閘極介電質層306及導電層370的部份。在一實施例中，由化學機械研磨步驟來移除在層間介電質薄膜310之上的閘極介電質層306及導電層370的部份。
因此，可藉由以替代閘極整合方式使用介電質閘極堆疊而將無尖端引起應變之磊晶源極/汲極區域包含入半導體裝置中。在一實施例中，磊晶源極/汲極區域308'實質上是由摻雜硼的矽/鍺所構成，通道區域304實質上是由矽所構成，並且在通道區域304上引發壓縮單軸應變，如 第3J圖中的箭頭所示。與第3J圖關連描述的結構可能會經過典型的製程步驟以完成半導體裝置的形成並將裝置納入積體電路中。例如，根據本發明之一實施例，後續在層間介電質薄膜310之中以及引起應變磊晶源極/汲極區域308'之上形成接觸孔。接著在形成後端金屬層之前進行通過接觸矽化步驟。在一替代實施例中，在沈積第3E圖中之被覆介電質薄膜350之前，於引起應變磊晶源極/汲極區域308'之上形成矽化物層。
本發明不限於平面半導體裝置。第4A至G圖描繪代表根據本發明之一實施例的具有無尖端磊晶源極/汲極區域之三閘極MOS-FET的形成之剖面圖。
參照第4A圖，在包含大塊半導體部分402A及孤立部分402B的立體基底402上形成介電質閘極堆疊佔位件432。在立體基底402的大塊半導體部分402A之暴露的部份中形成蝕刻掉區域440，如第4B圖中所示。根據本發明之一實施例，在介電質閘極堆疊佔位件432之下保留通道區域404。參照第4C圖，在蝕刻掉區域440中選擇性形成引起應變磊晶源極/汲極區域408，其與通道區域404直接鄰接並且與介電質閘極堆疊佔位件432直接接觸。接著在介電質閘極堆疊佔位件432、引起應變磊晶源極/汲極區域408及立體基底402的孤立部分402B之上沈積被覆介電質層450，如第4D圖中所示。參照第4E圖，將被覆介電質層450及介電質閘極堆疊佔位件432的上部分平坦化以形成層間介電質薄膜410及平坦化的介電質閘 極堆疊佔位件434。接著移除平坦化的介電質閘極堆疊佔位件434以於層間介電質薄膜410中形成溝渠460並暴露出通道區域404，如第4F圖中所示。參照第4G圖，接著於溝渠460中形成閘極介電質層406及閘極電極418。因此，可藉由以替代閘極整合方式使用介電質閘極堆疊而將無尖端引起應變之磊晶源極/汲極區域包含入三閘極裝置中。可藉由傳統製程步驟將三閘極裝置包含到積體電路中，這為此技藝中已知者。
本發明亦不限於無間隔體之半導體裝置的形成。可使用一種半導體閘極堆疊佔位件，其具有薄外面介電質間隔體，以禁止於磊晶生長程序期間於半導體閘極堆疊佔位件上之沈積。第5A至B圖描繪根據本發明之一實施例的代表具有無尖端磊晶源極/汲極區域及介電質間隔體的平面MOS-FET之形成的剖面圖。
參照第5A圖，提供具有介電質側壁間隔體590之半導體閘極堆疊佔位件332。此結構對應至上述之第3B圖，但添加有介電質側壁間隔體的特徵。在一實施例中，半導體閘極堆疊佔位件332實質上是由多晶矽所構成，並且介電質側壁間隔體590是由介電質材料所構成。參照第5B圖，在介電質側壁間隔體590的兩側上形成底切介電質側壁間隔體590與替代閘極電極518的引起應變磊晶源極/汲極區域508。此結構對應至上述之第3J圖，但添加有介電質側壁間隔體的特徵。
因此，已揭露具有無尖端磊晶源極/汲極區域之半導 體裝置及其形成方法。在一實施例中。半導體裝置包含於基底上之閘極堆疊。閘極堆疊是由在閘極介電質層上的閘極電極所構成，該閘極堆疊並且在基底的通道區域上。此半導體裝置亦包含在基底中通道區域兩側上之一對源極/汲極區域。該對源極/汲極區域與閘極介電質層直接接觸，並且該對源極/汲極區域的晶格常數與通道區域的晶格常數不同。在一實施例中，藉由使用介電質閘極堆疊佔位件來形成半導體裝置。
100‧‧‧非應變PMOS-FET
102‧‧‧通道區域
104‧‧‧閘極介電質層
106‧‧‧閘極電極
108‧‧‧閘極孤立間隔體
110‧‧‧尖端延伸
112‧‧‧源極/汲極區域
114‧‧‧基底
116‧‧‧凹陷區域
120‧‧‧引起應變之源極/汲極區域
130‧‧‧應變PMOS-FET
200‧‧‧半導體裝置
202‧‧‧基底
204‧‧‧通道區域
206‧‧‧閘極介電質層
208‧‧‧引起應變之磊晶源極/汲極區域
210‧‧‧層間介電質薄膜
212‧‧‧外擴散區域
218‧‧‧閘極電極
302‧‧‧基底
304‧‧‧通道區域
306‧‧‧閘極介電質層
308、308'‧‧‧引起應變之磊晶源極/汲極區域
310‧‧‧層間介電質薄膜
314‧‧‧孤立區域
330‧‧‧預先圖案化之介電質閘極堆疊佔位層
318‧‧‧閘極電極
332‧‧‧閘極堆疊佔位件
340、340'‧‧‧蝕刻掉區域
350‧‧‧覆被介電質薄膜
360‧‧‧溝渠
370‧‧‧導電層
402‧‧‧立體基底
402A‧‧‧大塊半導體部分
402B‧‧‧孤立區域
404‧‧‧通道區域
406‧‧‧閘極介電質層
408‧‧‧引起應變之磊晶源極/汲極區域
410‧‧‧層間介電質薄膜
418‧‧‧閘極電極
432‧‧‧介電質閘極堆疊佔位件
434‧‧‧平坦化的介電質閘極堆疊佔位件
440‧‧‧蝕刻掉區域
450‧‧‧覆被介電質薄膜
460‧‧‧溝渠
508‧‧‧引起應變之磊晶源極/汲極區域
518‧‧‧閘極電極
590‧‧‧介電質側壁間隔體
第1A至C圖描繪代表根據先前技術於PMOS-FET中形成引起應變的源極/汲極區域之典型程序流程的剖面圖。
第2圖描繪代表具有無尖端之磊晶源極/汲極區域的平面MOS-FET的剖面圖。
第3A至J圖描繪代表根據本發明之一實施例的具有無尖端引起應變之磊晶源極/汲極區域的平面MOS-FET的形成之剖面圖。
第4A至G圖描繪代表根據本發明之一實施例的具有無尖端磊晶源極/汲極區域之三閘極MOS-FET的形成之剖面圖。
第5A至B圖描繪根據本發明之一實施例的代表具有無尖端磊晶源極/汲極區域及介電質間隔體的平面MOS-FET之形成的剖面圖。
200‧‧‧半導體裝置
202‧‧‧基底
204‧‧‧通道區域
206‧‧‧閘極介電質層
208‧‧‧引起應變之磊晶源極/汲極區域
210‧‧‧層間介電質薄膜
212‧‧‧外擴散區域
214‧‧‧孤立區域
218‧‧‧閘極電極

Claims (10)

  1. 一種半導體裝置，包含設置於基底上之閘極堆疊，其中該閘極堆疊是由在高k閘極介電質層上的金屬閘極電極所構成，並且在該基底中的通道區域上，其中該高k閘極介電質層是在該金屬閘極電極與該通道區域之間，並沿著該金屬閘極電極的側壁；層間介電質薄膜，其與沿著該金屬閘極電極的該些側壁之該高k閘極介電質層的該些部分直接鄰接；以及於該基底中在該通道區域的兩側上之一對源極/汲極區域，其中該對源極/汲極區域與該高k閘極介電質層直接接觸，且其中該對源極/汲極區域之晶格常數與該通道區域的晶格常數不同。
  2. 如申請專利範圍第1項之半導體裝置，其中該通道區域實質上由矽原子所構成，且其中該對源極/汲極區域實質上由矽/鍺所構成，其具有在20至35%範圍中之鍺原子的原子濃度。
  3. 如申請專利範圍第2項之半導體裝置，進一步包含：在該基底中並且與該對源極/汲極區域的周邊鄰接之硼外擴散區域。
  4. 如申請專利範圍第1項之半導體裝置，其中該對源極/汲極區域之晶格常數與該通道區域的晶格常數差至少0.1%。
  5. 如申請專利範圍第1項之半導體裝置，其中該對源極/汲極區域具有大約55度之底切輪廓。
  6. 一種形成半導體裝置之方法，包含：於基底上形成閘極堆疊，其中該閘極堆疊是由在高k閘極介電質層上的金屬閘極電極所構成，其中該高k閘極介電質層是形成在該金屬閘極電極與該通道區域之間，並沿著該金屬閘極電極的側壁；於該基底中以及於該閘極堆疊的兩側上形成一對源極/汲極區域，以界定該基底中之通道區域，其中該對源極/汲極區域與該高k閘極介電質層直接接觸，且其中該對源極/汲極區域之晶格常數與該通道區域的晶格常數不同；以及形成層間介電質薄膜，其與沿著該金屬閘極電極的該些側壁之該高k閘極介電質層的該些部分直接鄰接。
  7. 如申請專利範圍第6項之方法，其中該通道區域實質上由矽原子所構成，且其中該對源極/汲極區域實質上由矽/鍺所構成，其具有在20至35%範圍中之鍺原子的原子濃度。
  8. 如申請專利範圍第7項之方法，進一步包含：在形成該對源極/汲極區域後，形成在該基底中並且與該對源極/汲極區域的周邊鄰接之硼外擴散區域。
  9. 如申請專利範圍第6項之方法，其中該對源極/汲極區域之晶格常數與該通道區域的晶格常數差至少0.1%。
  10. 如申請專利範圍第6項之方法，其中以大約55度之底切輪廓形成該對源極/汲極區域。
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