^005-0706 18973twf.doc/e 200805507 九、發明說明： 【發明所屬之技術領域】 、、>，金氧半場效電晶體及其製造方 及其f造t。關於—種具有應變層的金氧半場效電晶體 【先前技術】 低成ίϋϊ效電晶體由於具有高可靠度、低能量消耗及 =成^優勢，已成為積體電路中的最重要元件。典型的 效電晶體是建構切基底上，包括—閘極、源極 及位於閘極與基底之_閘介電層。隨著通訊 來侖椒的進步^金氧半場效電晶體的運作速度必須愈 +二j :、$而’因為文限於電子與電洞在石夕中的移動_速度， 、，氧，場效電晶體的應用範圍也受到限制。 ~ 曰笼已提出—種金氧半場效電晶體’利用石夕鍺蟲 曰曰=材料來做為源極無極區，以提高電子與電洞的移動 上度_。射相比，鍺具有較小的電子有效質量（electr〇n ra ^Ve峨）及電洞有效質量（硫effective mass)， 電、、同Si為材料可以提高源極與汲極區的電子遷移率與 /°遷移率。再者，因為鍺的晶格常數大於矽，因此 晶具有應變層（Gained layer)的功能，進一 Y提向了金氧半場效電晶體的效能。 ☆二：而以石夕錯蠢晶為源極與汲極區的金氧半場效電晶 。睛參照圖1 ’圖1是習知一種金 虱—場效電晶體的剖面示意圖。此金氧半場效電晶體包括 200805507„ 18973twf.doc/e 基底100、閘極102、閘介電層104、源極與汲極區106及 金屬矽化物層108。其中，金屬矽化物層1〇8是圖1的結 構中最後製造的部分。金屬矽化物層108的製造方法包括 自行對準金屬碎化物製程（Self-aligned Silicide Process， SALICID Process)，此製程容易在源極與汲極區ι〇6及隔 離結構110的交界處112產生尖峰現象（Spiking)，使金 屬石夕化物層108與基底1〇〇接觸，因而造成接合漏電 (Junction Leakage ) 〇 【發明内容】 有鑑於此，本發明之目的是提供一種金氧半場效電晶 體的製造方法，以避免發生上述之尖峰現象。 士發明之另—目岐提供—種金氧半場效電晶體，以 屬⑦化物層與墓底連接，換言之，能夠避免接合漏.^005-0706 18973twf.doc/e 200805507 IX. Description of the invention: [Technical field to which the invention pertains], , >, gold-oxygen half-field effect transistor and its manufacturing method. About a gold-oxygen half-field effect transistor with a strained layer [Prior Art] Due to its high reliability, low energy consumption and advantages, it has become the most important component in integrated circuits. A typical effect transistor is constructed on a substrate, including a gate, a source, and a gate dielectric layer at the gate and the substrate. With the progress of the communication to the pepper, the operating speed of the gold-oxygen half-field effect transistor must be more than two j:, $ and 'because the text is limited to the movement of electrons and holes in the stone _ speed, ,, oxygen, field effect The range of applications of transistors is also limited. ~ The cage has been proposed - a kind of gold-oxygen half-field effect transistor 'Using the stone 锗 锗 曰曰 = material as the source electrodeless zone to improve the movement of electrons and holes _. Compared with the shot, the crucible has a small electron effective mass (electr〇n ra ^Ve峨) and a hole effective mass. The electric and Si materials can improve the electron migration in the source and drain regions. Rate and /° mobility. Furthermore, since the lattice constant of germanium is larger than that of germanium, the crystal has a function of a Gained layer, and the efficiency of the gold oxide half-field effect transistor is further improved. ☆ 2: The stone oxygen half-field effect electric crystal is used as the source and the bungee area. 1 is a schematic cross-sectional view of a conventional gold-based field effect transistor. The MOS field effect transistor includes a 200805507 „ 18973 twf.doc/e substrate 100, a gate 102, a gate dielectric layer 104, a source and drain region 106, and a metal telluride layer 108. The metal telluride layer 1〇 8 is the last fabricated part of the structure of Figure 1. The method of manufacturing the metal telluride layer 108 includes a Self-aligned Silicide Process (SALICID Process), which is easy to use in the source and drain regions. The junction 112 of the crucible 6 and the isolation structure 110 generates a spike phenomenon, causing the metal-lithium layer 108 to contact the substrate 1〇〇, thereby causing junction leakage (Junction Leakage). [Invention] In view of this, the present invention The purpose of the invention is to provide a method for manufacturing a gold-oxygen half-field effect transistor to avoid the occurrence of the above-mentioned peak phenomenon. In addition, the invention provides a gold-oxygen half-field effect transistor, which is connected to the tomb bottom by a 7-layer layer. In other words, it is possible to avoid joint leakage.
電的問題 電晶金氧半場效 結構，#日*心私供基底，基底上已形成有閘極 構。於閘極㈣^結構兩_基底中形成有數個隔離結 .Ιώ 、、、口構兩側形成第一間隙壁。移除篦Ρ卩咕辟兩 侧與隔離結構之L移料—間隙壁兩 積-層源極與汲極層，：二：成凹陷。於凹陷中沉 隔離結構的頂表面。於、、祕^雜與錄層的頂表面高於 成第二間㈣。之4、雜4極層兩側與隔離結構上形 化物層。 土 於源極與汲極層上形成-層金屬石夕 在本發明之一實施例中， 於形成第二間隙壁之前 ，更 2005-0706 18973twf.doc/e 200805507 包括移除部分隔離結構，而降低隔離結構的頂表面高度。 、在本發明之一實施例中，上述之源極與汲極層成 方法例如是選擇性磊晶沉積製程。 y 本發明再提出一種金氧半場效電晶體的製造方法，包 括提供基底，基底上已形成有閘極結構，並且於基底中^ 成有數個隔離結構。移除閘極結構兩侧與這些隔離結構之 =的部分基底，以形成凹陷。於凹陷中沉積源極與沒極層， 其中源極與汲極層的頂表面高於隔離結構的頂表面。於閘 =結構兩側及源極與汲極層兩側與隔離結構上形成間^ 壁。之後，於源極與汲極層上形成一層金屬矽化物層曰。’、 在本發明之一實施例中，於形成間隙壁之前，更包括 移除部分隔離結構，而降低隔離結構的頂表面高度。 /本發明之一實施例中，上述之源極與汲極層之形成 法例如是選擇性磊晶沉積製程。 例如明之一實施例中，上述孓源極與汲極層之材料 例如發明之一實施例中，上述之源極與汲極層之材料 面 構的頂表面。間隙壁位於閘極結構之側壁 電曰本，明又提出一種金氧半場效電晶體，此金氧半場欵 層曰曰體是由基底、數個隔離結構、閘極結構、源極與汲極 置二，，壁所構成。隔離結構配置於基底中。閘極結構配 兩;I隔離結構之間的基底上。源極與汲極層位於閘極結構 高隔離結構之間的基底中，且源極與汲極層的頂表 200805507 uivi^-z〇〇5-〇7〇6 18973twf.doc/e 及源極與汲極層之側壁與隔離結構上。 在本發明之一實施例中，上述之源極與汲極層之結構 例如是蟲晶。 在本發明之一實施例中，上述之源極與汲極層之材料 例如是梦鍺。 在本發明之一實施例中，上述之源極與汲極層之材料 例如是矽碳。 本發明另提出一種互補式金氧半場效電晶體的製造 方法，包括提供基底。基底可分為第一元件區及第二元件 區，且第一元件區及第二元件區的基底上分別形成有數個 隔離結構及一閘極結構。此外，第一元件區及第二元件區: 是以隔離結構為界。然後，於第一元件區上形成一層帽= 層，並移除第二元件區的閘極結構兩側與隔離結構之間的 部分基底，以形成凹陷。接著，於凹陷中沉積源極與汲極 層’其中源極與汲極層的頂表面高於隔離結構的頂表面j 之後，移除帽蓋層及第二元件區的部分隔離結構，同時 低隔離結構的頂表面·高度。繼之，於源極與汲極層兩側與 隔離結構上形成間隙壁，並於第一元件區的閘極結構兩侧 與隔離結構之間的基底中形成源極與汲極區。隨後，於、 極與汲極層上形成一層金屬矽化物層。 、雨、 在本發明之一實施例中，上述之源極與汲極層之形 方法包括選擇性磊晶沉積製程。 / 在本發明之一實施例中，上述之源極與汲極層之材 包括石夕鍺。然而在本發明另-實施例中，上述之源極與及 200805507 005-0706 18973twf.doc/( 極層之材料包括石夕碳。 ^曰在本發明的金氧半場效電晶體或互補式金氧半場效 γ —的製程中’由於在源極與没極層的側壁與隔離結構 上形成有間隙壁，以阻擋金屬矽化物層在隔離結構和源極 與/及極層的父界處成長，因此能夠防止金屬秒化物層與基 底連接，從而避免接合漏電。 #為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 【第一實施例】 圖2Α至圖2Ε是本發明之第一實施例之金氧半場效電 晶體的製造流程剖面圖。 了先，請參照圖2Α，首先提供一基底200。基底2〇〇 例如疋矽基的（sllic〇nbased)基底。基底2⑻上已形成數 個隔離結構202。隔離結構2G2之材料例如是氧化石夕。隔 離結構202之間的基底2〇〇上已形成有閘極結構2〇4。閘 極結構204是由閘介電層204a及閘極2〇4b所構成。其中 閘$電層204a之材料例如是氧化矽，閘極204b之材料例 如是摻雜多晶矽。此外，閘極結構2〇4下方的基底2〇〇是 做為此金氧半場效電晶體的通道區206。 ^接著，請參照圖2B，於閘極結構204兩側形成一層補 償間隙壁208a，並於補償間隙壁2〇8a的表面形成一層第 一間隙壁208b。補償間隙壁208a的材料例如是氮化矽， 200805507 Q7“d/ uivi^-^005-0706 18973twf.doc/e 且第一間隙壁208b的材料例如是氧化矽或氮化矽。補償間 隙壁208a與第一間隙壁208b的形成方法例如是先於二才^ 204b表面以及基底200上沉積一層氮化石夕層（未緣示）， 於閘極結構204及基底200上覆蓋一層絕緣層（未緣示）， 然後進行一非專向性姓刻製程’直到暴露閘極2〇4b及基底 200，而形成之。 一 然後，請參照圖2C，以閘極結構204、間隙壁2〇8a、 間隙壁208b及隔離結構202為罩幕，進行乾式二刻製程 f 212，以移除間隙壁208b兩側與隔離結構202之間的部分 基底200,而形成凹陷214。乾式蝕刻製程212例如是反應 性離子蝕刻（reactive ion etching , RIE)製程，且乾式蚀 刻製程212的反應氣體例如是六氟化二碳(€；2176)及氦氣。 值得注意的是，在進行乾式蝕刻製程212時，閘極結構2〇4 的閘極204b也會被移除一部分。 - 繼之、，請參照圖2D，於凹陷214中沉積源極與汲極層 216其中源極與汲極層216的頂表面例如是高於隔離結構 . 1的頂表面。在，佳實施射，此金氧半場效電晶體 的裝程更包括於通道區施與凹陷214之間形成一淺摻雜 lightly doped )的源極與汲極延伸區（犯以似他― eXtenS1〇n)，以避免發生短通道效應（short channel effect)。 源極/、及，延伸區的形成方法例如是傾斜角離子植入法。 、、f實轭例中，此金氧半場效電晶體為PM0S，源極 圣層216之材料例如是石夕錯。石夕錯的組成結構通常以 1X〜來表*，或直接以SiGe來表示。其中X的範 18973twf.doc/e 200805507— ______ —005-0706 圍疋介於0至1。此外，源極與汲極層216之結構例如 是磊晶。源極與汲極層216的形成方法例如是選擇性磊晶 /儿積I程（selective epitaxial deposition)，以使石夕錯僅在 矽上成長，而不會在氧化矽或氮化矽上成長。換言之，矽 鍺僅會在凹陷214上成長，而不會在隔離結構2〇2、補償 間隙壁208a、第一間隙壁2〇8b及介電層210上成長。因 此，於進行選擇性磊晶製程時，會同時在閘極2〇4b上形成 與源極與汲極層216相同材料的半導體層217。選擇性磊 晶沉積製程例如是氣相磊晶製程（vap〇rphaseepitaxy)， 其包括減壓化學氣相沉積磊晶沉積法（re4uced扒以犯代 chemical vapor deposition epitaxial dep〇siti〇n)、常壓化學 氣相沉積磊晶法（atmosphere chemical vapor dep〇siti〇n epitaxy)以及超高真空化學氣相沉積磊晶法（111加 vacuum chemical vapor depositi〇n epitaxy)。此外，源極與 汲極層216例如含有P型摻質。p雜質例如是在形成[原 極與汲極層216時進行臨場（in_situ)摻雜而注入。當然， p型摻質也可以在形·成源極與汲極層216之後進行非臨'場 的摻雜而注入。另外，P型摻質例如是硼離子。 ^此外，請繼續參照圖2D。在另一實施例中，此金氧半 %效電晶體為NM0S，則源極與汲極層216之材料例如是 矽碳。矽碳的組成結構通常以SlxCix來表示，或直接以 SiC來表示。其中X的範圍是介於〇至丨。此外，源 極與汲極層216之結構例如是磊晶。源極與汲極層216的 形成方法例如是選擇性磊晶沉積製程，以使矽碳僅在矽上 11 200805507 -------005-0706 18973twf.doc/e 上成長。換言之謂 壁、第-間： 於進行選擇性蟲晶製程時，會同長。因此， 極與汲極層2i6相同材料的半導體/21 ^形成與源 _及極層雜在形成源 ::以Π:極與酬-之後進行二的二質 体f N型摻f例如是磷離子或珅離子。 結構=::==216兩側與隔離 ΐ: 圖，所有結構上形成-層絕緣層(未繪 ; 202、、U仃一非等向性蝕刻製程，直到暴露隔離結 2^ Π 及源極與汲極層216，而於隔離結構 Λ二亟。汲極層216的交界處形成第二間隙壁218。 麻人Ϊ著，於半導體層217及源極與没極層216上形成一 了化物層220’以降低後續形成的接觸窗(c〇ntact) 二’、亟及極層216的接觸電阻。金屬矽化物層22〇的材 厂例如疋鎳石夕化物或麵石夕化物’而金屬石夕化物層22〇的形 成方法=^自行對準金屬石夕化物製程（salicide process)。 ^值得一提的是，本發明可以在形成第二間隙壁218之 二先移除隔離結構2〇2白勺一部分厚度，以使隔離結構搬 、頂表面及源極與汲極層216的頂表面的高度差變大。而 12 ! 2005-0706 18973twf.doc/e 藉由使隔離結構202的頂表面及源極與没極層2i6的頂表 面的高度差變大，在形成第二間隙壁218的製程中，將^ 以完全去除第一間隙壁208b表面的絕緣層，而留下源極與 汲極層216兩側的絕緣層。因為第一間隙壁2〇訃的表面沒 有形成第二間隙壁218，所以會增加源極與汲極層216所 暴露的面積，以利於在源極與汲極層216上形成接觸窗 時’能夠有較大的製程裕度（process wind〇w)，如圖2E， 所示。 本發明的金氧半場效電晶體由於在源極與汲極層的兩 側以及隔離結構上形成有第二間隙壁，以阻擋金屬矽化物 層在隔離結構和源極與汲極層的交界處成長，因此能夠防 止金屬矽化物層與基底連接，從而避免接合漏電。 【第二實施例】 圖3A至圖3D是本發明的另一實施例之金氧半場效電 晶體的製造流程剖面圖。 首先，請參照圖3A，提供基底300，且基底300上例 如已形成有隔離結欉302與閘極結構304。閘極結構304 位於隔離結構302之間的基底300上。閘極結構304是由 閘介電層304a、閘極304b及補償間隙壁304c所構成。其 中閘介電層304a位於閘極304b及基底300之間，而補償 間隙壁304c位於閘極304b的兩側。閘介電層304a的材料 例如是氧化石夕，閘極304b的材料例如是摻雜多晶石夕，補償 間隙壁304c的材料例如是氮化矽。此外，閘極結構3〇4 下方的基底300是做為此金氧半場效電晶體的通道區3〇6。 13 1005-0706 18973twf.doc/e 200805507 接著，請參照圖3β，進行乾式蝕刻製程3〇8，而移除 口ί5分基底300，以於閘極結構304兩側與隔離結構302之 間的基底300中形成凹陷31〇。乾式蝕刻製程3〇8例如是 反，性離子韻刻，且乾式银刻製程3〇8的反應氣體例 六氟化工碳咖6)及氦氣。值得注意的是，在進行乾式蝕 刻製程308時，閛極結構3〇4的閘極3〇扑也會被移除一 分。 口 ^之，請參照圖3C，於凹陷31〇中沉積源極與沒極層 。-杈佳實施例中，此金氧半場效電晶體的製程更包 區3〇6與凹陷310之間形成一淺捧雜的源極弟及 ’以避免發生短通道效應。源極與沒極延伸區的 形成方法例如是傾斜角離子植入法。 例^此金氧半場效電晶體為_s，源極 L士構J丨如3 ί才料例如是石夕鍺。此外，源極與汲極層312 °源極層312的形成方法例如是 之’石夕鍺僅會在間極及凹陷31〇 長L It _結構302或補償間隙壁304c上成 ^形成與源極^f擇性遙晶製程時，會同時在閘極304b 外，源二、::極層312相同材料的半導體層314。此 是在^成二才f層312例如含有p型推質。p型摻質例如 注入ΐϊ == 312時進行臨W)摻雜而 子。 乃卜p型摻質例如是硼離 14 005-0706 18973twf.d〇c/e 200805507 此外，請繼續參照圖I在另一實施例中 場妓晶體為NM0S，則源極與汲極層312之材料 ，石厌。此外’源極與汲極層312之結構例如是 = 與汲極層312的形成方法例如是選擇㈣晶沉積j：程= 使石夕碳僅切上成長，而不會在氧切上成長。、$之以 矽碳僅會在閘極304b及凹陷31〇上成長 在二 構302及補償間隙壁綱c上成長。因此, ，製程時’會同時在閘極鳩上形成與源極 相同材料的半導體層314。另外， 型摻質。N型摻質例如是在形成源極與;及極層= 枯進仃場摻絲注人。，N型 # 極與沒極層312之後進行非臨場的摻雜而注入在= 面，N型摻質例如是磷離子或砷離子。 u ’請參照_ 3D ’於閉極結構304兩側及源極盘汲 極層312兩側與隔離結構302上形成間隙壁316。間隙辟 316的材料例如是氧切或氮切，而間隙壁316的形^ 方法例如是於圖3C的結構上覆蓋一層絕緣層（未繪示）， Μ性勤燦程’直縣露雜與沒極區 3=3層/Μ。而於源極與汲極層312及隔離結構 302的父界處形成間隙壁316。此外，部分間隙壁3 = 形成於閘極結構304的兩側。 ~曰 值^-提的是，在間隙壁316形成之前，可以先移除 隔離結f搬❺一部分厚度，以使隔離結構202的頂表面 及源極纽極層216的頂表面的高度差變大。從而續保間 15 W05-0706 18973twf.doc/e 隙壁316能夠同時形成於閘極結構3〇4的兩側以及源極與 及極層312與隔離結構302的交界處上。 隨後，於源極與汲極層312及半導體層314上形成一 層金屬秒化物層训，以降低後續形成的接觸窗與源極與 /及極層312的接觸電阻。金屬石夕化物層318例如是錄石夕化 ^勿或姑破化物，而金屬魏物層318的製造方法例如是自 行對準金屬石夕化物製程。 本發明的金氧半場效電晶體由於在源極與汲極層的兩 H、隔離t構上形成有間隙壁，以阻擔金屬矽化物層在隔 離結構和雜與汲極層的交界處成長，因此能夠防止金屬 石夕化物層與基底連接，從_免接合漏電。 以下說明上述兩種製造方法所製作的金氧半場效電 f體結構。請同時參照圖2E及圖3D，因為第一實施例是 於閘極結構204兩側製作第一間隙壁2_，再形成源極 及極層216 ’第二實施例是先在閘極結構綱兩側形成 源極與汲極層312,再形成間隙壁316，所以，大體而言， 圖2E與圖3D為具有不同製造程序的相似結構。因此，以 :僅就圖3D的結構進行說明。此外，圖2E與圖3D的結 冓並不限於以上述的製造方法來製作。 I本發明的金氧半場效電晶體包括基底 隔離結構302、閘極結構3〇4、源極與;及極層312、 半導體層314、間隙壁316及金屬砍化物層318。基底· =如=絲的基底。閘極結構綱配置於基底細上，包 間介電層304a、間極麟及補償間隙壁職。間隙壁 16 18973twf.doc/e 200805507!005,706 316位於閘極結構3G4之側壁上’以及位於源極與沒極層 ϋ之侧壁與隔離結構302上，且間隙壁216的材料例如 是氧化碎錢切。金屬魏物層318位於源極與沒極層 3曰12及半導體層314上，且金屬石夕化物層318的材料例: 是鎳矽化物及始矽化物。 源極與汲極層312位於閘極結構3〇4兩側的基底3〇〇 中，並且源極與汲極層312的頂表面高於隔離結構的 頂表面，半導體層314位於閘極304b上。源極與汲極層 3J2及f導體層314之結構例如是磊晶。在一實施例中： 右此金氧半場效電晶體為PMOS，源極與汲極層312及半 導體層314的材料例如是矽鍺，且可以含有p型摻質。在 另一貫施例中，若此金氧半場效電晶體為NM〇s，源極與 及極層312及半導體層的材料例如是石夕碳，且可以 型摻質。 . 由上述可知，本發明由於在源極與汲極層側壁以及隔 離、、”構上没置有間隙壁，因此在製造過程中，金屬石夕化物 層不會於源極與汲極層與隔離結構的交界處成長，從而防 止金屬矽化物層與基底連接，避免接合漏電的問題。 【第三實施例】 圖4A至圖4F是本發明一實施例的互補式金氧半場效 電日日體的製造流程剖面圖。 請參照圖4A，提供基底4〇〇，且基底4〇〇上例如已形 成有隔離結構402與閘極結構404。基底400可分為第一 元件& 400a及第—元件區400b。在本實施例中，後續的 製程是在第一元件區400a上形成NMOS，並於第二元件 17 200805507露嶋 18973twf.doc/e 區400b上形成PMOS。閘極結構404是由閘介電層404a、 及閘極404b所構成。其中閘介電層4〇4a位於閘極404b 及基底400之間，且閘介電層4〇4a的材料例如是氧化矽， 閘極404b的材料例如是摻雜多晶矽。此外，閘極結構404 下方的基底400是做為此互補式金氧半場效電晶體的通道 區 406。 接著，請參照圖4B，於閘極結構4〇4的側壁上形成 補償間隙壁408 ,並接著於基底4〇〇上覆蓋一層帽蓋層 410。其中補償間隙壁408的材料例如是氮化石夕，而帽蓋層 物的材料例如是氧化梦。隨後，於第一元件區 盍一層圖案化光阻層411。 —接著，請參照圖4C，以圖案化光阻層41〇為罩幕，進 仃一溼式蝕刻製程，而移除第二元件區4〇〇b的帽蓋層 410之後’以巾目蓋層41〇為罩幕，進行一乾式银刻製程 412’而移除部分基底·，以於第二元件區的閘極結構撕 兩側與隔離結構4〇2之間的基底铜中形成凹陷414。乾 式侧製程412例如是反應性離子_， 化的反應氣體例如是六氟化二碳及氦氣。Λ則衣知 居Alt之^請f照圖4D，於凹陷414中沉積源極與汲極 層416。在—難實施财，此互 才 的製程更包括於第二元件區彻b _ #^電曰曰體 . 几什L4u0b的通道區406與凹陷416 成-淺摻雜的源極與汲極延伸區， =:源極與汲極延伸區的形成方法例如是傾斜角離； 此外，源極與 源極與汲極層416之材料例如是矽鍺 18 200805507 >005-0706 18973twf.doc/e ^層416之結構例如是蟲晶。源 是選擇⑽晶沉積製程，以使魏僅在^^ 及凹mnn財< ’ 會在_4〇4b 繼且成長會在隔離結構402或補償間隙壁 u。因此，於進行選_晶製程時，會同時在 ί = 1 的閘極上形成與源極與汲極層416The problem of electricity is electro-crystal gold oxide half-field effect structure, #日*心私基基基, the gate structure has been formed on the substrate. A plurality of isolation junctions are formed in the base of the gate (four)^ structure. The first spacers are formed on both sides of the mouth, and the mouth. Remove the L-shift material from the two sides and the isolation structure—the two-product layer and the drain layer of the spacer layer: two: forming a depression. The top surface of the isolation structure is sunk in the recess. The top surface of the Yu, Mi Mi and the recording layer is higher than the second (four). 4. On both sides of the heterotetrapole layer and the layer on the isolation structure. Forming a layer of metal on the source and the drain layer. In an embodiment of the invention, before the formation of the second spacer, 2005-0706 18973 twf.doc/e 200805507 includes removing a portion of the isolation structure, and Reduce the height of the top surface of the isolation structure. In an embodiment of the invention, the source and drain layers are formed, for example, by a selective epitaxial deposition process. The invention further provides a method for fabricating a gold oxide half field effect transistor, comprising providing a substrate on which a gate structure has been formed and having a plurality of isolation structures in the substrate. A portion of the substrate on both sides of the gate structure and = of the isolation structure is removed to form a recess. A source and a gate layer are deposited in the recess, wherein a top surface of the source and drain layers is higher than a top surface of the isolation structure. The gates are formed on both sides of the structure and on both sides of the source and the drain layer and the isolation structure. Thereafter, a layer of metal telluride layer is formed on the source and drain layers. In an embodiment of the invention, before the formation of the spacer, the partial isolation structure is removed to reduce the height of the top surface of the isolation structure. In one embodiment of the invention, the method of forming the source and drain layers described above is, for example, a selective epitaxial deposition process. For example, in one embodiment, the material of the source and the drain layer is, for example, in the embodiment of the invention, the top surface of the material of the source and the drain layer. The spacer is located on the sidewall of the gate structure, and a gold-oxygen half-field effect transistor is proposed. The gold-oxide half-field layer is composed of a substrate, a plurality of isolation structures, a gate structure, a source and a drain. Set two, the wall is composed. The isolation structure is disposed in the substrate. The gate structure is provided with two; I is isolated on the substrate between the structures. The source and drain layers are located in the substrate between the high isolation structures of the gate structure, and the top and bottom of the source and drain layers are 200805507 uivi^-z〇〇5-〇7〇6 18973twf.doc/e and the source With the sidewall of the bungee layer and the isolation structure. In an embodiment of the invention, the structure of the source and drain layers is, for example, insect crystal. In an embodiment of the invention, the material of the source and drain layers is, for example, a nightmare. In an embodiment of the invention, the material of the source and drain layers is, for example, germanium carbon. The present invention further provides a method of fabricating a complementary MOS field effect transistor comprising providing a substrate. The substrate can be divided into a first component region and a second component region, and a plurality of isolation structures and a gate structure are formed on the substrates of the first component region and the second component region, respectively. In addition, the first component region and the second component region are bounded by an isolation structure. Then, a cap = layer is formed on the first element region, and a portion of the substrate between the sides of the gate structure of the second element region and the isolation structure is removed to form a recess. Then, after depositing the source and drain layers in the recess, wherein the top surface of the source and drain layers is higher than the top surface j of the isolation structure, the partial isolation structure of the cap layer and the second element region is removed while being low. The top surface and height of the isolation structure. Then, a spacer is formed on both sides of the source and the drain layer and the isolation structure, and a source and a drain region are formed in the substrate between the two sides of the gate structure of the first element region and the isolation structure. Subsequently, a layer of metal telluride is formed on the sol, the pole and the drain layer. Rain, in an embodiment of the invention, the method of forming the source and drain layers described above comprises a selective epitaxial deposition process. / In an embodiment of the invention, the material of the source and the drain layer comprises a stone slab. However, in another embodiment of the present invention, the source of the above-mentioned source is and 200805507 005-0706 18973 twf.doc / (the material of the pole layer comprises Shi Xi carbon. ^ 曰 in the present invention, the gold-oxygen half field effect transistor or the complementary gold In the process of oxygen half-field γ--because gaps are formed on the sidewalls of the source and the electrodeless layer and the isolation structure to block the growth of the metal telluride layer at the parent of the isolation structure and the source and/or the pole layer The above-mentioned and other objects, features and advantages of the present invention will be more apparent and understood. [Embodiment] [First Embodiment] Fig. 2A to Fig. 2A are cross-sectional views showing a manufacturing process of a gold-oxygen half field effect transistor according to a first embodiment of the present invention. First, please refer to Fig. 2 First, a substrate 200 is provided. The substrate 2 is, for example, a sllic 〇n-based substrate. A plurality of isolation structures 202 have been formed on the substrate 2 (8). The material of the isolation structure 2G2 is, for example, oxidized stone. of A gate structure 2〇4 has been formed on the bottom 2〇〇. The gate structure 204 is composed of a gate dielectric layer 204a and a gate electrode 2〇4b. The material of the gate electrode layer 204a is, for example, hafnium oxide, gate electrode. The material of 204b is, for example, doped polysilicon. In addition, the substrate 2 below the gate structure 2〇4 is the channel region 206 of the gold oxide half field effect transistor. ^ Next, please refer to FIG. 2B, the gate structure A compensation spacer 208a is formed on both sides of the spacer 204, and a first spacer 208b is formed on the surface of the compensation spacer 2〇8a. The material of the compensation spacer 208a is, for example, tantalum nitride, 200805507 Q7 "d/uivi^-^005 -0706 18973 twf.doc/e and the material of the first spacer 208b is, for example, yttrium oxide or tantalum nitride. The method for forming the compensation spacer 208a and the first spacer 208b is, for example, prior to the surface of the second 204b and the substrate 200. Depositing a layer of nitriding layer (not shown), covering the gate structure 204 and the substrate 200 with an insulating layer (not shown), and then performing a non-specification process until the exposed gate 2〇4b and The substrate 200 is formed. Then, please refer to FIG. 2C, with the gate The structure 204, the spacer 2〇8a, the spacer 208b and the isolation structure 202 are masks, and a dry two-step process f 212 is performed to remove a portion of the substrate 200 between the two sides of the spacer 208b and the isolation structure 202 to form a depression. 214. The dry etching process 212 is, for example, a reactive ion etching (RIE) process, and the reactive gas of the dry etching process 212 is, for example, hexafluoride (2; 2176) and helium. When the dry etching process 212 is performed, the gate 204b of the gate structure 2〇4 is also removed. - Following, referring to FIG. 2D, a source and drain layer 216 is deposited in recess 214 wherein the top surface of source and drain layer 216 is, for example, higher than the top surface of isolation structure 1. In the case of good implementation, the process of the gold-oxygen half-field effect transistor further includes forming a shallow doped light source and a bungee extension between the channel region and the recess 214 (to be like him - eXtenS1) 〇n) to avoid the occurrence of a short channel effect. The source/, and the formation method of the extension region is, for example, a tilt angle ion implantation method. In the case of the f yoke, the gold-oxygen half-field effect transistor is PMOS, and the material of the source holy layer 216 is, for example, Shi Xi wrong. The composition of Shi Xi wrong is usually expressed as 1X~, or directly in SiGe. The range of X is 18973twf.doc/e 200805507— ______ —005-0706 The cofferdam is between 0 and 1. Further, the structure of the source and drain layers 216 is, for example, epitaxial. The method of forming the source and drain layers 216 is, for example, selective epitaxial deposition, so that the stone grows only on the crucible, and does not grow on the hafnium oxide or tantalum nitride. . In other words, the crucible will only grow on the recess 214 and will not grow on the isolation structure 2〇2, the compensation spacer 208a, the first spacer 2〇8b, and the dielectric layer 210. Therefore, in the selective epitaxial process, the semiconductor layer 217 of the same material as the source and drain layers 216 is formed on the gate 2?4b at the same time. The selective epitaxial deposition process is, for example, a vapor phase epitaxy process (vap〇rphaseepitaxy), which includes a decompression chemical vapor deposition epitaxial dep〇siti〇n, atmospheric pressure Atmosphere chemical vapor dep〇siti〇n epitaxy and ultra high vacuum chemical vapor deposition epitaxy (111 plus vacuum chemical vapor deposit i〇n epitaxy). Further, the source and drain layers 216 contain, for example, a P-type dopant. The p impurity is implanted, for example, by in-situ doping when the [anode and drain layers 216 are formed. Of course, the p-type dopant can also be implanted after the formation of the source and the drain layer 216 after the doping of the field. Further, the P-type dopant is, for example, a boron ion. ^ In addition, please continue to refer to Figure 2D. In another embodiment, the gold oxide half-effect transistor is NMOS, and the material of the source and drain layers 216 is, for example, germanium carbon. The composition of the ruthenium carbon is usually expressed in terms of SlxCix or directly in SiC. The range of X is between 〇 and 丨. Further, the structure of the source and drain layers 216 is, for example, epitaxial. The method of forming the source and drain layers 216 is, for example, a selective epitaxial deposition process so that the germanium carbon grows only on the surface of the sputum 11 200805507 -------005-0706 18973 twf.doc/e. In other words, the wall, the first: between: in the selective insect crystal process, will be the same length. Therefore, the semiconductor/21^ of the same material as the drain layer 2i6 is formed with the source_and the pole layer. The source is formed by: Π: poles and then - after the two-dimer f-type f-doping, for example, phosphorus Ion or cesium ion. Structure =::==216 Both sides and isolation ΐ: Figure, all structures are formed - layer insulation (not drawn; 202, U 仃 a non-isotropic etching process until the isolation junction 2 ^ Π and source The second spacer 218 is formed at the interface of the drain layer 216 with the drain layer 216. The semiconductor layer 217 and the source and the gate layer 216 are formed on the semiconductor layer 217. The layer 220' reduces the contact resistance of the subsequently formed contact window (c〇ntact), the tantalum and the pole layer 216. The metal telluride layer 22 is a metal factory such as yttrium-nickel compound or smectite The formation method of the lithium layer 22〇 is to self-align the salicide process. It is worth mentioning that the present invention can remove the isolation structure 2 before forming the second spacer 218. 2 a portion of the thickness to increase the height difference between the isolation structure, the top surface, and the top surface of the drain layer 216. 12! 2005-0706 18973 twf.doc/e by making the top of the isolation structure 202 The difference in height between the surface and the source and the top surface of the gate layer 2i6 becomes large, and the process of forming the second spacer 218 is performed. , to completely remove the insulating layer on the surface of the first spacer 208b, leaving the insulating layer on both sides of the source and the drain layer 216. Since the surface of the first spacer 2 is not formed with the second spacer 218, Therefore, the exposed area of the source and drain layers 216 is increased to facilitate a larger process margin when forming a contact window between the source and the drain layer 216, as shown in FIG. 2E. The gold oxide half field effect transistor of the present invention has a second spacer formed on both sides of the source and drain layers and on the isolation structure to block the metal halide layer in the isolation structure and the source and drain layers. The junction grows, so that the metal telluride layer can be prevented from being connected to the substrate, thereby avoiding junction leakage. [Second Embodiment] FIGS. 3A to 3D are manufacturing processes of a gold oxide half field effect transistor according to another embodiment of the present invention. First, referring to FIG. 3A, a substrate 300 is provided, and an isolation junction 302 and a gate structure 304 are formed, for example, on the substrate 300. The gate structure 304 is located on the substrate 300 between the isolation structures 302. The gate structure 304 is the gate dielectric layer 30 4a, a gate 304b and a compensation spacer 304c, wherein the gate dielectric layer 304a is located between the gate 304b and the substrate 300, and the compensation spacer 304c is located on both sides of the gate 304b. The material of the gate dielectric layer 304a is, for example, It is a oxidized stone, the material of the gate 304b is, for example, doped polysilicon, and the material of the compensation spacer 304c is, for example, tantalum nitride. Further, the substrate 300 under the gate structure 3〇4 is used as the gold oxide half. The channel region of the effect transistor is 3〇6. 13 1005-0706 18973twf.doc/e 200805507 Next, referring to FIG. 3β, the dry etching process 3〇8 is performed, and the substrate 305 is removed, so that the gate structure 304 is used. A recess 31 is formed in the substrate 300 between the both sides and the isolation structure 302. The dry etching process 3〇8 is, for example, a reverse ion plasma, and a dry silver engraving process of 3〇8 of a reaction gas such as a hexafluoride carbon coffee 6) and helium. It is worth noting that during the dry etching process 308, the gate 3 of the drain structure 3〇4 is also removed. For the mouth, please refer to Figure 3C to deposit the source and the electrodeless layer in the recess 31〇. In the preferred embodiment, the process of the MOS field-effect transistor further forms a shallow source between the cell 3〇6 and the recess 310 and avoids the short channel effect. The formation method of the source and the electrode extension region is, for example, a tilt angle ion implantation method. For example, the gold-oxygen half-field effect transistor is _s, and the source L-shi structure is such as 3 ί. In addition, the method of forming the source and drain layer 312 ° source layer 312 is, for example, 'the stone 锗 锗 will only form and form on the interpole and recess 31 〇 L L _ structure 302 or the compensation spacer 304c. In the case of the selective crystal crystal process, the semiconductor layer 314 of the same material of the source layer 2::: the pole layer 312 is simultaneously outside the gate 304b. This is in the case of a layer 312, for example, containing a p-type push substance. The p-type dopant is doped, for example, when implanted with ΐϊ == 312. The p-type dopant is, for example, boron ion 14 005-0706 18973 twf.d〇c/e 200805507 In addition, please continue to refer to FIG. 1 . In another embodiment, the field 妓 crystal is NM0S, then the source and drain layers 312 Material, stone is tired. Further, the structure of the source and drain layers 312 is, for example, = and the formation method of the drain layer 312 is, for example, selective (four) crystal deposition j: Cheng = so that the Shi Xi carbon is only cut and grown without growing on the oxygen cut. The carbon will only grow on the gate 304b and the recess 31〇 and grow on the second structure 302 and the compensation gap wall c. Therefore, the semiconductor layer 314 of the same material as the source is formed simultaneously on the gate electrode during the process. In addition, the type of dopant. N-type dopants are, for example, formed in the source and; and the polar layer = dry into the field. The N-type and the non-polar layer 312 are implanted on the = surface, and the N-type dopant is, for example, a phosphorus ion or an arsenic ion. u ‘Please refer to _ 3D ′ to form a spacer 316 on both sides of the closed-pole structure 304 and on both sides of the source-plate drain layer 312 and the isolation structure 302. The material of the gap 316 is, for example, oxygen cutting or nitrogen cutting, and the method of the spacer 316 is, for example, an insulating layer (not shown) on the structure of FIG. 3C, which is a kind of Nothing area 3 = 3 layers / Μ. A spacer 316 is formed at the source and drain layers 312 and the parent of the isolation structure 302. Further, a part of the spacer 3 = is formed on both sides of the gate structure 304. It is noted that before the spacer 316 is formed, the isolation junction f may be removed to remove a portion of the thickness so that the height difference between the top surface of the isolation structure 202 and the top surface of the source contact layer 216 Big. Thus, the refill room 15 W05-0706 18973 twf.doc/e gap 316 can be formed simultaneously on both sides of the gate structure 3〇4 and at the interface between the source and the pole layer 312 and the isolation structure 302. Subsequently, a layer of metal second layer is formed on the source and drain layers 312 and 314 to reduce the contact resistance of the subsequently formed contact window with the source and/or layer 312. The metal lithium layer 318 is, for example, a lithograph, and the method of manufacturing the metal slab 318 is, for example, a self-aligned metallization process. The gold-oxygen half-field effect transistor of the present invention has a spacer formed on the two H and isolated t structures of the source and the drain layer to block the growth of the metal telluride layer at the interface between the isolation structure and the impurity and the drain layer. Therefore, it is possible to prevent the metal-lithium layer from being connected to the substrate and leaking from the joint. The structure of the gold-oxygen half field effect electric body produced by the above two manufacturing methods will be described below. Please refer to FIG. 2E and FIG. 3D simultaneously, because the first embodiment is to form the first spacer 2_ on both sides of the gate structure 204, and then form the source and the pole layer 216'. The second embodiment is first in the gate structure. The source and drain layers 312 are formed sideways, and spacers 316 are formed, so that, in general, Figures 2E and 3D are similar structures having different fabrication procedures. Therefore, only the structure of Fig. 3D will be described. Further, the features of Figs. 2E and 3D are not limited to being produced by the above-described manufacturing method. The gold-oxygen half field effect transistor of the present invention comprises a substrate isolation structure 302, a gate structure 3〇4, a source and a gate layer 312, a semiconductor layer 314, a spacer 316, and a metal cleavage layer 318. Substrate · = as the base of the wire. The gate structure is arranged on the base, and the dielectric layer 304a, the inter-substrate and the compensation gap are interposed. The spacer 16 18973twf.doc/e 200805507!005, 706 316 is located on the sidewall of the gate structure 3G4 and on the sidewall of the source and the electrodeless layer and the isolation structure 302, and the material of the spacer 216 is, for example, oxidized money cut. The metal wafer layer 318 is located on the source and the gate layer 3曰12 and the semiconductor layer 314, and the material of the metallization layer 318 is a nickel halide and a germanium compound. The source and drain layers 312 are located in the substrate 3〇〇 on both sides of the gate structure 3〇4, and the top surface of the source and drain layers 312 is higher than the top surface of the isolation structure, and the semiconductor layer 314 is located on the gate 304b. . The structure of the source and drain layers 3J2 and the f-conductor layer 314 is, for example, epitaxial. In one embodiment: the right MOS field-effect transistor is a PMOS, and the source and drain layers 312 and the semiconductor layer 314 are made of, for example, germanium and may contain p-type dopants. In another consistent embodiment, if the MOS field-effect transistor is NM 〇 s, the source and the electrode layer 312 and the material of the semiconductor layer are, for example, stellite carbon, and can be doped. As can be seen from the above, in the present invention, since the sidewalls of the source and the drain layer and the isolation and the structure are not provided with spacers, the metal-lithium layer does not exist in the source and drain layers during the manufacturing process. The junction of the isolation structure grows, thereby preventing the metal telluride layer from being connected to the substrate, and avoiding the problem of junction leakage. [Third Embodiment] FIGS. 4A to 4F are complementary metal oxide half-field electric power days according to an embodiment of the present invention. Referring to FIG. 4A, a substrate 4 is provided, and an isolation structure 402 and a gate structure 404 are formed, for example, on the substrate 4. The substrate 400 can be divided into a first component & 400a and a - element region 400b. In the present embodiment, the subsequent process is to form an NMOS on the first device region 400a, and a PMOS is formed on the second device 17 200805507, the 18973 twf.doc/e region 400b. The gate structure 404 is The gate dielectric layer 404a and the gate 404b are formed. The gate dielectric layer 4〇4a is located between the gate 404b and the substrate 400, and the material of the gate dielectric layer 4〇4a is, for example, hafnium oxide, gate 404b. The material is, for example, doped polysilicon. In addition, The substrate 400 under the pole structure 404 is a channel region 406 for this complementary metal oxide half field effect transistor. Next, referring to FIG. 4B, a compensation spacer 408 is formed on the sidewall of the gate structure 4〇4, and then The substrate 4 is covered with a capping layer 410. The material for compensating the spacers 408 is, for example, nitride rock, and the material of the cap layer is, for example, an oxidative dream. Subsequently, a patterned photoresist is formed in the first component region. Layer 411. - Next, referring to FIG. 4C, after patterning the photoresist layer 41 as a mask, a wet etching process is performed, and after the cap layer 410 of the second element region 4b is removed, The cover layer 41 is a mask, and a dry silver engraving process 412' is performed to remove a portion of the substrate, so as to be in the base copper between the tearing sides of the gate structure of the second element region and the isolation structure 4? A depression 414 is formed. The dry side process 412 is, for example, a reactive ion, and the reaction gas is, for example, hexafluoride dicarbon and helium. The Λ 知 知 A A A 照 照 照 照 照 照 照 照 照 照 照 照 照 照 照 414 Extreme and bungee layer 416. In the difficult to implement financial, this process of mutual talent is included in the second The element region is completely b _ #^电曰曰体. The channel region 406 and the recess 416 of the several L4u0b are shallow-doped source and drain extension regions, =: the source and drain extension regions are formed, for example, In addition, the material of the source and source and drain layers 416 is, for example, 矽锗18 200805507 >005-0706 18973twf.doc/e ^ The structure of layer 416 is, for example, insect crystal. The source is selective (10) crystal deposition. The process, so that Wei only in ^^ and concave mnn financial < 'will be in _4 〇 4b and then grow in isolation structure 402 or compensation gap u. Therefore, when performing the selective crystallization process, the source and drain layers 416 are formed simultaneously on the gate of ί = 1.
的半導體層418。此外，源極触極層4i6 J =型摻質’此P型摻質例如是蝴離子。p型摻質例如 =在形成源極與沒極層416時進行臨場摻雜而注入。當 口:=咖成雜_ 416之後進“ 繼之，請參照圖4E，移除第-元件區4〇Oa的帽蓋層 柳，此處值得注意的是，在移除第—元件區微的帽蓋 層410的同時，將會同時移除第二元件區楊的隔離結二 備的部分厚度，以使得隔離結構402的頂表面及源極與 及極層4^6的頂表面的高度差變大，有利於後續間隙壁的 ^成〜接著’於第一元件區4術的補償間隙壁權的侧壁、 々一疋件區4〇〇b的補償間隙壁408的側壁以及源極與汲極 層416的側壁與隔離結構4〇2上形成間隙壁 420 〇 繼之，請參照圖4F，於第二元件區4〇〇b上覆蓋一層 ，案化光阻層（未緣示），並進行—離子植入製程 ，以於 弟一元件區40〇a的間隙壁42〇兩側的基底4〇〇中形成源極 ^汲極H 422。源極與汲極區422的摻質例如是鱗離子或 神離子。接著，移除這層圖案化光阻層。在-較佳實施例 19 >005-0706 18973twf.d〇c/e 200805507 中此互補式金氧半場效電晶體的製程更包括於第一 區400a的源極與汲極區似與通道區楊之間形成一淺換 雜的源極與沒極延伸區，以避免發生短通道效應。源極與 汲極蛑伸區的形成方法例如是傾斜角離子植入法。 "然後’於第-元件區的閘極4 〇4b、源極與沒極層4】6、 半導體層418以及源極與汲極區422上形成一層金屬石夕化 物層424。金屬魏物層424的材料例如是鎳魏物或銘 石夕化物’且金屬魏物層424的形成方法例如是自行對準 金屬石夕化物製程。由於在第二元件區娜的源極與沒極層 416兩側及隔離結構4〇2上形成有間隙壁42〇,因此金屬矽 化物層424不會在源極與没極層416與隔離結構4〇2的交 界處成長，從而避免接合漏電。 另一方面，在另一實施例的互補型金氧半場效電晶:體 中:NMOS是形成於第二元件區4〇%，而pM〇s是形成 於第一元件區400a。此互補型金氧半場效電晶體的源極與 没極層416的材質例如是石夕碳、其結構例如是遙晶，且源 極與汲極層416例如摻有磷離子或砷離子等N型摻質。再 者，源極與汲極區422例如摻有硼離子。除此之外，此互 補型金氧半場效電晶體的製造方法與上述的製程類似，因 此不再重複說明此另一實施例。 顯而易見，在又一實施例中，此互補型金氧半場效電 晶體的NMOS及PMOS的源極與汲極層的材質例如分別 是矽碳及矽鍺。源極與汲極層的結構例如均是磊晶，且例 如摻有N型摻質與P型摻質。換言之，NM〇s及pM〇s 20 200805507 2005-0706 18973twf.doc/e 可以均以第二元件區4〇〇b的製程來製作。 练上所述，由於在源極與沒極層的兩側及隔離結構上 形成有間隙壁，因此能夠防止金屬矽化物層在源極與汲極 層和隔離結構的交界處成長，避免金屬矽化物層與基底連 接，而可以防止接合漏電的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不_本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知一種金氧半場效電晶體的剖面示意圖。 圖2八至圖2E是本發明之第一實施例之金氧半場 晶體的製造流程剖面圖。 圖2E，是圖2E的金氧半場效電晶體在經過本發明 一實施例之製造流程所得到的結構。Semiconductor layer 418. Further, the source contact layer 4i6 J = type dopants 'this type P dopant is, for example, a butterfly ion. The p-type dopant is, for example, implanted by performing field doping when the source and the gate layer 416 are formed. When the mouth: = coffee into the _ 416 after the "continued, please refer to Figure 4E, remove the cap - layer of the fourth element area 4 〇 Oa, here it is worth noting that in the removal of the first element area At the same time as the cap layer 410, the partial thickness of the isolation junction of the second component region will be simultaneously removed, so that the height difference between the top surface and the source of the isolation structure 402 and the top surface of the electrode layer 4^6 The enlargement facilitates the sidewall of the subsequent spacer wall and then the sidewall of the compensation spacer wall of the first component region 4, the sidewall of the compensation spacer 408 of the first component region 4〇〇b, and the source and the drain A sidewall 420 is formed on the sidewall of the pole layer 416 and the isolation structure 4〇2, and then, referring to FIG. 4F, a layer is covered on the second component region 4〇〇b to form a photoresist layer (not shown). The ion implantation process is performed to form a source electrode H 422 in the substrate 4 〇 on both sides of the spacer 42 〇 of the device region 40 〇 a. The dopant of the source and the drain region 422 is, for example, Scale ions or god ions. Next, the patterned photoresist layer is removed. In Preferred Embodiment 19 >005-0706 18973twf.d〇c/e 200805507 The process of the complementary MOSFET is further included in the source and drain regions of the first region 400a to form a shallow alternating source and immersion extension region to avoid short occurrence. Channel effect. The method of forming the source and drain diffusion regions is, for example, tilt angle ion implantation. " Then 'gate 4 〇4b in the -e-element region, source and gate layer 4】6, semiconductor A metal lithium layer 424 is formed on the layer 418 and the source and drain regions 422. The material of the metal material layer 424 is, for example, nickel or stellite, and the method of forming the metal wafer layer 424 is, for example, Aligning the metallization process, since the spacer 42 is formed on both sides of the source and the gate layer 416 of the second element region and the isolation structure 4〇2, the metal telluride layer 424 is not at the source. Growing at the junction with the gate layer 416 and the isolation structure 4〇2, thereby avoiding junction leakage. On the other hand, in another embodiment of the complementary metal oxide half field effect transistor: NMOS is formed in the second component The region is 4〇%, and pM〇s is formed in the first element region 400a. This complementary type of gold oxide The source of the field effect transistor and the material of the gate layer 416 are, for example, a stellite carbon, the structure of which is, for example, a telecrystal, and the source and drain layer 416 are doped with, for example, N-type dopants such as phosphorus ions or arsenic ions. The source and drain regions 422 are, for example, doped with boron ions. In addition, the fabrication method of the complementary metal oxide half field effect transistor is similar to the above-described process, and thus another embodiment will not be repeatedly described. In another embodiment, the source and drain layers of the NMOS and PMOS layers of the complementary MOS field-effect transistor are, for example, germanium carbon and germanium, respectively. The structures of the source and drain layers are, for example, Epitaxial, and for example doped with N-type dopants and P-type dopants. In other words, NM〇s and pM〇s 20 200805507 2005-0706 18973twf.doc/e can all be fabricated in the process of the second component region 4〇〇b. As described above, since the spacers are formed on both sides of the source and the electrodeless layer and the isolation structure, it is possible to prevent the metal telluride layer from growing at the boundary between the source and the drain layer and the isolation structure, thereby avoiding metal deuteration. The layer is connected to the substrate to prevent the problem of joint leakage. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional gold oxide half field effect transistor. Fig. 2 through Fig. 2E are cross-sectional views showing the manufacturing process of the gold-oxygen half-field crystal of the first embodiment of the present invention. Fig. 2E is a view showing the structure of the gold-oxygen half field effect transistor of Fig. 2E obtained by the manufacturing process of an embodiment of the present invention.
圖3A至圖3D 是本發明的第二實施例之金氧半 電晶體的製造流程剖®圖。 乂 施例的互補式金氧半場 圖4A至圖4F是本發明第三實 效電晶體的製造流程剖面圖。 【主要元件符號說明】 100、200、300、400 :基底 102、204、304、404:閘極結構 104、204a、304a、404a :閘介電層 106、216、312、416:源極與汲極曰層 21 200805507.™ 18973twf.doc/e 108、220、318、424 :金屬矽化物層 110、202、302、402 ··隔離結構 112 :交界處 204b、304b、404b :閘極 206、306、406 :通道區 208a、304c、408 ··補償間隙壁 208b :第一間隙壁 408 :介電層 212、308、412 :乾式蝕刻製程 214、310、416 :凹陷 218 :第二間隙壁 217、314、418 :半導體層 216、420 :間隙壁 410 :帽蓋層 411 :圖案化光阻層 422 :源極與》及極區 22Fig. 3A to Fig. 3D are cross-sectional views showing the manufacturing process of the gold-oxygen semiconductor according to the second embodiment of the present invention.互补 Complementary gold oxide half field of the embodiment Fig. 4A to Fig. 4F are cross-sectional views showing the manufacturing process of the third practical transistor of the present invention. [Main component symbol description] 100, 200, 300, 400: substrate 102, 204, 304, 404: gate structure 104, 204a, 304a, 404a: gate dielectric layer 106, 216, 312, 416: source and 汲Electrode layer 21 200805507.TM 18973twf.doc/e 108, 220, 318, 424: metal telluride layer 110, 202, 302, 402 · isolation structure 112: junction 204b, 304b, 404b: gate 206, 306 406: channel region 208a, 304c, 408 · compensation spacer 208b: first spacer 408: dielectric layer 212, 308, 412: dry etching process 214, 310, 416: recess 218: second spacer 217, 314, 418: semiconductor layer 216, 420: spacer 410: cap layer 411: patterned photoresist layer 422: source and "and polar region 22