I2"5^d,005.0706 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種金氧半場效電晶體及其勢造方 法，且特別是有關於一種具有應變層的金氧半場致^晶體 及其製造方法。 ^日日^ 【先前技術】 金氧半場效電晶體由於具有高可靠度、低能量消耗及 低成本等優勢，已成為積體電路中的最重要元件。典型的 金氧半場效電晶體是建構在矽基底上，包括一閘極、源極 與汲極區以及位於閘極與基底之間的閘介電層。隨著通訊 等電子設備的進步’金氧半場效電晶_運作速】必^愈 來愈快。然而，因為受限於電子與電洞切中的移動速度二 金氧半場效電晶體的應用範圍也受到限制。 〜 習知技術已提出-種金氧半場效電晶體，利用石夕儲 晶等材料來做為源極與祕區，以提高電子與電洞的移動 速度。與梦相比，有較小的電子有效質4 Uec她 effects mass)及電洞有效質量（h〇le范沈細咖 口此以梦錄為材料可以提南源極與沒極區 電洞遷移率。再者，因為鍺的晶格常數大於石夕因; 石夕錯蟲晶具有應變層（rained layer)的功能，進一 步提尚了金氧半場效電晶體的效能。 I-為源極與汲極區的金氧半場效電晶 產生4的缺陷。請參照圖1，圖i是習知一種金 乳+場效電晶體的剖面示意圖。此金氧半場效電晶體包括 !2995^d -2005-0706 18973twf.doc/e 基底100、閘極102、閘介電層1〇4、源極與汲極區1〇6及 金屬矽化物層108。其中，金屬矽化物層1〇8是圖丨的結 構中最後製造的部分。金屬矽化物層1〇8的製造方法包括 自行對準金屬石夕化物製程（Self_aligned SiUdde Ργ〇_， SALICID Process)，此製程容易在源極與汲極1 1〇6及隔 離結構110的交界處112產生尖峰現象（Spiking)，使金 屬石夕化物層108與基底削接觸，因而造成接合漏電 (Junction Leakage )。 【發明内容】 於此，本發明之目的是提供—種金氧半場效電晶 體的衣每方法’以避免發生上叙鱗躲。 本^月之另一目的是提供-種金氧半場效電晶體，以 石f化物層與基底連接，換言之，能夠ΐ免-接合漏 =達上述或是其他目的，本 :=一供基底，基底上 侧盥隔離姓堪々^形成苐一間隙壁。移除第一間隙壁兩 浐二声湄：盥曰’的部分基底，以形成凹陷。於凹陷中沉 =二_。於源極與_兩;== 之後’於祕與汲極層上形成—層金屬石夕 在本發明之—實施例中，於形成第二間隙壁之前，更 6 I2995^d. 2005-0706 18973twf.doc/e 包括移除部分隔離結構’而降低隔離結構的頂表面言^ 在本發明之一實施例中’上述之源極與汲極層：ς成 方法例如是選擇性磊晶沉積製程。 ^成 本發明再提出-種金氧半場效電晶體的製造方法 基底，基底上已形成有閘極結構，並且於基底^ ，個隔離結構。移除閘極結構兩側與這些隔離結= 2部分基底’以形成凹陷。於凹陷中沉積源極與没極广 其中源極姐極層的頂表面高於隔離結構的頂表面。於γ 结構兩側及源極與錄層兩側與隔離結構上形成間= 。之後，於源極與汲極層上形成一層金屬矽化物層。，、 在本發明之一實施例中，於形成間隙壁之前，^包扛 移除部分隔離結構，而降低隔離結構的頂表面高度。 在本發明之一實施例中，上述之源極與汲極^之、 万法例如是選擇性磊晶沉積製程。 ， 例如=明之一實施例中，上述之源極與雖層之材料 例士 發明之一實施例中，上述之源極與汲極層之材料 本發明又提出一種金氧半場效電晶體，此金氧半場效 ，晶體是由基底、數個隔離結構、閘極結構、源極與汲^ 曰及間隙壁所構成。隔離結構配置於基底中。閘極結構配 置於隔離結構之間的基底上。源極與汲極層位於閘極結構 $側與隔離結構之間的基底中，且源極與汲極層的頂表面 向於隔離結構的頂表面。間隙壁位於閘極結構之侧壁，以 5齓·。7 06 18973twf.doc/e 及源極與汲極層之側壁與隔離結構上。 在本發明之一實施例中’上述之源極與汲極層之結構 例如是磊晶。 ^ 在本發明之一實施例中，上述之源極與汲極層之材料 例如是碎錯。 在本發明之一實施例中，上述之源極與汲極層之材料 例如是ί夕碳。 本發明另提出一種互補式金氧半場效電晶體的製造 方法’包括提供基底。基底可分為第一元件區及第二元件 區’且第一元件區及第二元件區的基底上分別形成有數甸 隔離結構及一閘極結構。此外，第一元件區及第二元件區 疋以隔離結構為界。然後，於第一元件區上形成一層帽= 層，並移除第二元件區紿閘極結構兩側與隔離結構之間的 部分基底，以形成凹陷。接著，於凹陷中沉積源極與及極 層，其中源極與汲極層的頂表面高於隔離結構的頂表面。 之後，移除帽蓋層及第二元件區的部分隔離結構，同時降 馨 低隔離結構的頂表面高度。繼之，於源極與汲極層兩侧與 隔離結構上形成間隙壁，並於第一元件區的閘極結構兩側 與隔離結構之間的基底中形成源極與汲極區。隨後，於源 極與汲極層上形成一層金屬矽化物層。 在本發明之一實施例中，上述之源極與汲極層之形成 方法包括選擇性磊晶沉積製程。 在本發明之一實施例中，上述之源極與汲極層之材料 包括矽鍺。然而在本發明另一實施例中，上述之源極與汲 〇MCD-2005.0706 18973twf.doc/e 極層之材料包括石夕碳。 曰在本發明的金氧半場效電晶體或互赋金氧半場效 電晶體的製針，由於在源極姐極層_ 上形成有間_，以_金射㈣層在_結構和^ 與汲極層的交界處成長，因此能夠防止金財 底連接，從而避免接合漏電。 基 ^為讓本發明之上述和其他目的、·和伽能更明顯 易懂’下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 【第一實施例】 圖2A至圖2E是本發明之第一實施例之金氧半場效 晶體的製造流程剖面圖。 =先，請參照圖2A，首先提供一基底200。基底2〇〇 例如是矽基的（silic〇nbased)基底。基底2〇〇上已形成數 個隔離結構202。隔離結構202之材料例如是氧化矽。隔 離結構202之間的基底2〇〇上已形成有閘極結構204。閘 極結構204是由閘介電層204a及閘極204b所構成。其中 閘^電層204a之材料例如是氧化矽，閘極204b之材$斗例 如是摻雜多晶矽。此外，閘極結構204下方的基底2〇〇是 做為此金氧半場效電晶體的通道區206。 ，接著’請參照圖2B，於閘極結構204兩側形成一層補 償間隙壁208a，並於補償間隙壁2〇8a的表面形成一^第 一間隙壁208b。補償間隙壁208a的材料例如是氮化二， ：D-2005-0706 18973twf.doc/e 且第一間隙壁208b的材料例如是氧化矽或氮化矽。補償間 隙壁208a與第一間隙壁208b的形成方法例如是先於閘極 204b表面以及基底200上沉積一層氮化矽層（未繪示）， 於閘極結構204及基底200上覆蓋一層絕緣層（未繪示）， 然後進行一非等向性蝕刻製程，直到暴露閘極204b及基底 200，而形成之。 然後，請參照圖2C ’以閘極結構2〇4、間隙壁208a、 間隙壁208b及隔離結構202為罩幕，進行乾式姓刻製程 212，以移除間隙壁208b兩侧與隔離結構2〇2之間的部分 基底200,而形成凹陷214。乾式蝕刻製程212例如是反應 性離子蝕刻（reactive ion etching，RIE)製程，且乾式姓 刻製程212的反應氣體例如是六氟化二碳(C2F6)及氦氣。 值得注意的是，在進行乾式蝕刻製程212時，閘極結構2〇4 的閘極204b也會被移除一部分。 繼之，請參照圖2D ’於凹陷2丨4中沉積源極與汲極層 216,其中源極與沒極^ 216的頂表面例如是高於隔離結構 202的頂表面。在一較佳實施例中，此金氧半場效電晶體 的製程更包括於通道區206與凹陷214之間形成一淺摻雜 (lightly doped)的源極與汲極延伸區（s〇urce/d=in extension)，以避免發生短通道效應（sh〇rt channd effect)。 源極與汲，延伸區的形成方法例如是傾斜角離子植入法。 在-實知例中’此金氧半場效電晶體為pM〇s，源極 與没極層216之材料例如切鍺。⑪鍺的組成結構通常以 SlxGei-X來表*，或直接以SiGe來表示。其巾X的範 12995說 -2005-0706 18973twf.doc/e 圍疋”於〇至1。此外，源極與汲極層216之結構例如 是磊晶。源極與汲極層216的形成方法例如是選擇性磊晶 "匕積裝程（selective epitaxial deposition)，以使石夕鍺僅在 矽上成長，而不會在氧化矽或氮化矽上成長。換言之，矽 鍺僅會在凹陷214上成長，而不會在隔離結構2〇2、補償 間隙壁208a、第一間隙壁208b及介電層210上成長。因 此’於進行選擇性磊晶製程時，會同時在閘極2〇4b上形成 與源極與汲極層216相同材料的半導體層217。選擇性磊 曰日/儿積製程例如是氣相遙晶製程（vap〇r phase epitaXy )， 其包括減壓化學氣相沉積遙晶沉癌法（re(juced pressufe chemical vapor deposition epitaxial deposition)、常壓化學 氣相沉積磊晶法（atmosphere chemicai vapor deposition epitaxy)以及超高真空化學氣相沉積磊晶法（仙以hi^， vacuum chemical vapor deposition epitaxy)。此外，源極與 汲極層216例如含有p型摻質。p型摻質例如是在形成源 極與沒極層216時進行臨場（in_situ)摻雜而注入。當然， P型摻質也可以在形-成源極與汲極層216之後進行非臨場 的摻雜而注入。另外，P型摻質例如是硼離子。 此外，請繼續參照圖2D。在另一實施例中，此金氧半 場效電晶體為NMOS ,則源極與汲極層216之材料例如是 矽碳。矽碳的組成結構通常以SixCi x來表示，或直接以 SiC來表示。其中X的範圍是介於〇至1。此外，源 極與汲極層216之結構例如是磊晶。源極與汲極層216的 形成方法例如是選擇性磊晶沉積製程，以使矽碳僅在矽上 ϋ-2005-0706 18973twf.doc/eI2"5^d, 005.0706 IX. Description of the Invention: [Technical Field] The present invention relates to a gold-oxygen half-field effect transistor and its potential manufacturing method, and in particular to a gold-oxygen half field having a strained layer The crystal and its manufacturing method. ^日日^ [Prior Art] Gold-oxygen half-field effect transistors have become the most important components in integrated circuits due to their high reliability, low energy consumption and low cost. A typical MOS field effect transistor is constructed on a ruthenium substrate and includes a gate, a source and a drain region, and a gate dielectric layer between the gate and the substrate. With the advancement of electronic equipment such as communication, the 'Gold Oxygen Half-Field Effect Electron Crystal _ Operating Speed】 will become faster and faster. However, because of the limited speed of movement in electron and hole cutting, the application range of the MOS field-effect transistor is also limited. ~ The conventional technology has proposed a kind of gold-oxygen half-field effect transistor, which uses materials such as Shixi storage crystal as the source and secret area to improve the moving speed of electrons and holes. Compared with the dream, there is a small electronic effective quality 4 Uec her effects mass) and the effective quality of the hole (h〇le Fan Shen fine coffee mouth this dream recorded as a material can be used to promote the South source and the immersed area hole migration Furthermore, because the lattice constant of yttrium is larger than that of Shi Xiyin; Shixi worm has the function of a rained layer, which further enhances the efficiency of the gold oxide half field effect transistor. I- is the source and The gold-oxide half-field effect crystal in the bungee region produces a defect of 4. Referring to Figure 1, Figure 1 is a schematic cross-sectional view of a conventional gold-emulsion + field-effect transistor. The gold-oxygen half-field effect transistor includes !2995^d - 2005-0706 18973twf.doc/e substrate 100, gate 102, gate dielectric layer 1〇4, source and drain regions 1〇6 and metal telluride layer 108. Among them, metal telluride layer 1〇8 is a figure The last fabricated part of the structure of germanium. The method of manufacturing the metal telluride layer 1〇8 includes a self-aligned metal-lithium process (Self_aligned SiUdde Ργ〇_, SALICID Process), which is easy to process at the source and the drain 1 1 The junction 112 of the crucible 6 and the isolation structure 110 generates a spike phenomenon, causing the metallization layer 108 The invention is in contact with the substrate, thereby causing junction leakage (Junction Leakage). [Invention] The purpose of the present invention is to provide a method for the coating of a gold-oxygen half-field effect transistor to avoid the occurrence of scaling. Another purpose of the month is to provide a gold-oxygen half-field effect transistor, which is connected to the substrate by a layer of stone, in other words, can be forgiven-joint leakage = for the above or other purposes, this: = a substrate, on the substrate The side 盥 isolation surname 々 々 苐 苐 苐 苐 。 。 。 。 。 。 。 。 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除 移除;== After the formation of the layer on the secret and the bismuth layer - in the embodiment of the invention, before the formation of the second spacer, 6 I2995^d. 2005-0706 18973twf.doc/e includes Removing a portion of the isolation structure to reduce the top surface of the isolation structure. In one embodiment of the invention, the source and drain layers described above are: for example, a selective epitaxial deposition process. - Method for producing gold oxide half field effect transistor A gate structure has been formed thereon, and an isolation structure is formed on the substrate. The two sides of the gate structure are removed from the isolation structure = 2 part of the substrate to form a depression. The source is deposited in the depression and the source is not extremely wide. The top surface of the sister layer is higher than the top surface of the isolation structure. The two sides of the γ structure and the source and the recording layer are formed on the isolation structure. Then, a metal halide is formed on the source and the drain layer. In one embodiment of the present invention, before forming the spacer, the portion of the isolation structure is removed to reduce the height of the top surface of the isolation structure. In an embodiment of the invention, the source and the drain are, for example, a selective epitaxial deposition process. For example, in one embodiment of the invention, in the embodiment of the source and the layer of the material, the material of the source and the drain layer, the present invention further provides a metal oxide half field effect transistor. The gold oxide half-field effect, the crystal is composed of a substrate, a plurality of isolation structures, a gate structure, a source and a 汲^ 曰 and a spacer. The isolation structure is disposed in the substrate. The gate structure is disposed on the substrate between the isolation structures. The source and drain layers are in the substrate between the gate structure $ side and the isolation structure, and the top surfaces of the source and drain layers face the top surface of the isolation structure. The spacer is located on the side wall of the gate structure, at 5 齓·. 7 06 18973twf.doc/e and the sidewall and isolation structure of the source and drain layers. In an embodiment of the invention, the structure of the source and drain layers described above is, for example, epitaxial. In one embodiment of the invention, the material of the source and drain layers described above is, for example, broken. In an embodiment of the invention, the material of the source and drain layers is, for example, ί夕碳. The present invention further provides a method of fabricating a complementary MOS field effect transistor comprising 'providing a substrate. The substrate may be divided into a first element region and a second device region, and a plurality of isolation structures and a gate structure are formed on the substrates of the first device region and the second device region, respectively. Further, the first element region and the second element region are bounded by an isolation structure. Then, a cap = layer is formed on the first element region, and a portion of the substrate between the two sides of the second element region and the isolation structure is removed to form a recess. Next, a source and a drain layer are deposited in the recess, wherein a top surface of the source and drain layers is higher than a top surface of the isolation structure. Thereafter, the cap layer and a portion of the isolation structure of the second component region are removed while reducing the height of the top surface of the low isolation structure. Then, a spacer is formed on both sides of the source and the drain layer and the isolation structure, and a source and a drain region are formed in the substrate between the two sides of the gate structure of the first element region and the isolation structure. Subsequently, a layer of metal telluride is formed on the source and drain layers. In one embodiment of the invention, the method of forming the source and drain layers described above comprises a selective epitaxial deposition process. In one embodiment of the invention, the material of the source and drain layers described above comprises germanium. However, in another embodiment of the invention, the material of the source and the 〇MCD-2005.0706 18973 twf.doc/e pole layer comprises a stone.制In the invention of the gold-oxygen half-field effect transistor or the mutual-enhanced gold-oxygen half-field effect transistor, since the source _ is formed on the source layer _, the _ gold (four) layer is in the _ structure and The junction of the bungee layer grows, so it can prevent the connection of the gold bottom, thus avoiding joint leakage. The above and other objects, and gamma energy of the present invention are more apparent and understood. The following detailed description of the preferred embodiments and the accompanying drawings are set forth below. [Embodiment] FIG. 2A to FIG. 2E are cross-sectional views showing a manufacturing process of a gold-oxygen half field effect crystal according to a first embodiment of the present invention. = First, referring to FIG. 2A, a substrate 200 is first provided. The substrate 2 is, for example, a silic〇nbased substrate. A plurality of isolation structures 202 have been formed on the substrate 2''. The material of the isolation structure 202 is, for example, ruthenium oxide. A gate structure 204 has been formed on the substrate 2 between the isolation structures 202. The gate structure 204 is composed of a gate dielectric layer 204a and a gate 204b. The material of the gate electrode layer 204a is, for example, yttrium oxide, and the material of the gate electrode 204b is doped polysilicon. In addition, the substrate 2 below the gate structure 204 is the channel region 206 that serves as the gold oxide half field effect transistor. Next, referring to FIG. 2B, a compensation spacer 208a is formed on both sides of the gate structure 204, and a first spacer 208b is formed on the surface of the compensation spacer 2〇8a. The material of the compensation spacer 208a is, for example, nitrided, :D-2005-0706 18973 twf.doc/e and the material of the first spacer 208b is, for example, tantalum oxide or tantalum nitride. The method for forming the compensation spacer 208a and the first spacer 208b is, for example, depositing a layer of tantalum nitride (not shown) on the surface of the gate 204b and the substrate 200, and covering the gate structure 204 and the substrate 200 with an insulating layer. (not shown), then an anisotropic etching process is performed until the gate 204b and the substrate 200 are exposed. Then, referring to FIG. 2C 'with the gate structure 2〇4, the spacer 208a, the spacer 208b and the isolation structure 202 as a mask, a dry-type process 212 is performed to remove both sides of the spacer 208b and the isolation structure 2〇 A portion of the substrate 200 between the two forms a recess 214. The dry etching process 212 is, for example, a reactive ion etching (RIE) process, and the reactive gas of the dry type process 212 is, for example, hexafluoride (C2F6) and helium. It should be noted that when the dry etching process 212 is performed, the gate 204b of the gate structure 2〇4 is also removed. Next, please refer to FIG. 2D' to deposit the source and drain layers 216 in the recesses 2丨4, wherein the top surfaces of the source and the gates 216 are, for example, higher than the top surface of the isolation structure 202. In a preferred embodiment, the process of the MOS field-effect transistor further includes forming a lightly doped source and drain extension between the channel region 206 and the recess 214 (s〇urce/ d=in extension) to avoid the short channel effect (sh〇rt channd effect). The source and the crucible, and the formation method of the extension region is, for example, a tilt angle ion implantation method. In the embodiment, the gold-oxygen half field effect transistor is pM〇s, and the source and the material of the electrode layer 216 are, for example, cut. The composition of 11锗 is usually expressed in terms of SlxGei-X or directly in SiGe. The vane 12995 of the towel X is described as -2005-0706 18973 twf.doc/e 疋 疋 〇 〇 。 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外 此外. For example, selective epitaxial deposition, so that the stone grows only on the raft, and does not grow on yttrium oxide or tantalum nitride. In other words, 矽锗 will only be in the depression The 214 grows up and does not grow on the isolation structure 2〇2, the compensation spacer 208a, the first spacer 208b, and the dielectric layer 210. Therefore, when performing the selective epitaxial process, the gate 2 is simultaneously A semiconductor layer 217 having the same material as the source and drain layers 216 is formed on 4b. The selective epitaxy process is, for example, a vapor phase recrystallization process (vap〇r phase epitaXy) including decompression chemical vapor deposition. Re-juced pressufe chemical vapor deposition epitaxial deposition, atmospheric chemicai vapor deposition epitaxy, and ultra-high vacuum chemical vapor deposition epitaxy Vacuum chemical vapor deposition ep In addition, the source and drain layers 216 contain, for example, a p-type dopant. The p-type dopant is implanted, for example, by in-situ doping when forming the source and the gate layer 216. Of course, P-type doping The quality may also be implanted by non-field doping after forming the source and drain layers 216. In addition, the P-type dopant is, for example, boron ions. Further, please continue to refer to FIG. 2D. In another embodiment, The metal oxide half field effect transistor is an NMOS, and the material of the source and drain layer 216 is, for example, germanium carbon. The composition of the germanium carbon is usually represented by SixCi x or directly represented by SiC, wherein the range of X is Further, the structure of the source and drain layers 216 is, for example, epitaxial. The method of forming the source and drain layers 216 is, for example, a selective epitaxial deposition process so that the tantalum carbon is only on the crucible - 2005-0706 18973twf.doc/e
I2995MI2995M
UMCI ^ ’而不會在氧切錢切上成長。換言之 2第 14 而不會在隔離結構 ί進\ 及介電層210上成長，此， =仃k擇性咖製程時，會同時在閘極細b上 極與沒極層2i6相同材料的半導體層217 =極 極與錄層216時進行臨場摻雜而注入。， 也可以在形成源極與祕層216 ^ 雜^ 注Μ^，Ν型穆質例如料二 -構=上;Πΐ ’於源極與沒極層216兩側與隔離 、-構202上$成-層紅間隙壁218 嫩切’而第二 ί :fTD的所有結構上形成-層絕緣層(未繪 /〇 “、、、後，進仃一非等向性蝕刻製程，直到義露隔離纱 ===72f源極與_216,而㈣“ 較界處形成第：間隙㈣。 層金屬魏物層勝以降低後細;層216上形成一 盥调炻盥、、》代麻傻,形成的接觸窗（contact) ==層216的接觸電阻。金屬石夕化 =如疋鎳魏物或卿化物，而金屬魏物^ 值侍一棱的疋，本發明可以在 的頂表面及源極與沒極層216的頂表面的高度差變大。而 12 I2995SSd.2005.0706 18973twf.d〇c/e 藉由，隔離結構202的頂表面及源極與汲極層216的頂表 面=高度差變大，在形成第二間隙壁218的製程中，將可 以完全去除第一間隙壁208b表面的絕緣層，而留下源極與 汲極層^16兩側的絕緣層。因為第一間隙壁208b的表面沒 有=成第二間隙壁218，所以會增加源極與汲極層216所 ^露=面積，以利於在源極與汲極層216上形成接觸窗 日守，月匕夠有車父大的製程裕度（process window)，如圖2E， 所示。 •本發明的金氧半場效電晶體由於在源極與汲極層的兩 側以及隔離結構上形成有第二_壁，以阻擔金屬石夕化物 層在隔離結構和源極與汲極層的交界處成長，因此能夠防 止金屬矽化物層與基底連接，從而避免接合漏電。 【第二實施例】 圖3A至圖3D是本發明的另一實施例之金氧半場效電 晶體的製造流程剖面圖。 首先，請參照圖3A，提供基底300，且基底300上例 > 如已形成有隔離結欉302與閘極結構304。閘極結構304 位於隔離結構302之間的基底300上。閘極結構304是由 閘介電層304a、閘極304b及補償間隙壁304c所構成。其 中閘介電層304a位於閘極304b及基底300之間，而補償 間隙壁304c位於閘極304b的兩侧。閘介電層304a的材料 例如是氧化矽，閘極304b的材料例如是摻雜多晶矽，補償 間隙壁304c的材料例如是氮化石夕。此外，閘極結構304 下方的基底300是做為此金氧半場效電晶體的通道區3〇6。 13 ：D-2005-0706 18973twf.doc/e 接著’請參照圖3B，進行乾式I虫刻製程3〇8，而移除 部分基底300，以於閘極結構3〇4兩側與隔離結構3〇2之 間的基底300中形成凹陷31〇。乾式餘刻餘3〇8例 反，性離佳刻’且乾式_餘通職麟體例 2化二碳(娜及氦氣。i得注意的是，在進行乾式钮 ^製程308時，閘極結構3〇4的閘極3〇牝也會被移除一部UMCI ^ ‘and will not grow in the oxygen cut. In other words, the 14th is not grown on the isolation structure and the dielectric layer 210. In this case, the semiconductor layer of the same material as the gate electrode 2i6 is simultaneously on the gate b of the gate. 217 = the pole and the recording layer 216 are implanted while being doped in the field. , can also be formed in the source and secret layer 216 ^ ^ ^ Μ ^, Ν 穆 穆 例如 例如 例如 例如 例如 例如 Πΐ Πΐ Πΐ Πΐ Πΐ Πΐ 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于The layer-by-layer red spacers 218 are tenderly cut and the second ί:fTD is formed on all the layers of the insulating layer (not drawn/〇,,,, and then an anisotropic etching process until the isolation Yarn ===72f source and _216, and (4) "The boundary is formed at the boundary: the gap (4). The layer of the metal layer wins to reduce the thickness; the layer 216 forms a 盥 炻盥," The formed contact == the contact resistance of the layer 216. The metal shi ding == 疋 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 金属 魏 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属The height difference between the pole and the top surface of the electrodeless layer 216 becomes larger. And 12 I2995SSd.2005.0706 18973twf.d〇c/e by the top surface of the isolation structure 202 and the top surface of the source and drain layer 216=height difference Increasingly, in the process of forming the second spacer 218, the insulating layer on the surface of the first spacer 208b can be completely removed, leaving the insulating layer on both sides of the source and drain layers. The surface of the first spacer 208b is not = the second spacer 218, so the source and the drain layer 216 are increased in area to facilitate the formation of contact windows on the source and drain layers 216. The moon has enough process window, as shown in Fig. 2E. • The MOS field effect transistor of the present invention is formed on both sides of the source and drain layers and on the isolation structure. The second wall serves to block the metal-lithium layer from growing at the interface between the isolation structure and the source and the drain layer, thereby preventing the metal telluride layer from being connected to the substrate, thereby avoiding junction leakage. [Second embodiment] 3A to 3D are cross-sectional views showing a manufacturing process of a gold-oxygen half field effect transistor according to another embodiment of the present invention. First, referring to FIG. 3A, a substrate 300 is provided, and the substrate 300 is as described above.欉302 and gate structure 304. The gate structure 304 is located on the substrate 300 between the isolation structures 302. The gate structure 304 is composed of a gate dielectric layer 304a, a gate 304b and a compensation spacer 304c. Layer 304a is located between gate 304b and substrate 300, and The spacers 304c are located on both sides of the gate 304b. The material of the gate dielectric layer 304a is, for example, tantalum oxide, the material of the gate 304b is, for example, doped polysilicon, and the material of the compensation spacer 304c is, for example, nitride nitride. The substrate 300 under the pole structure 304 is the channel region 3〇6 for this gold-oxygen half field effect transistor. 13 :D-2005-0706 18973twf.doc/e Next, please refer to FIG. 3B for the dry I insect engraving process 3 〇8, a portion of the substrate 300 is removed to form a recess 31〇 in the substrate 300 between the sides of the gate structure 3〇4 and the isolation structure 3〇2. The dry remnant of the remaining 3 〇 8 cases of anti-sexuality and the dry _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The gate 3〇牝 of the structure 3〇4 will also be removed.
繼之，請參照圖3C，於凹陷31〇巾沉積源極與沒極層 2 〇在-触實施射，此金氧半場效電晶體的製程更包 =於，道區306與凹陷31〇之間形成一淺推雜的源極與沒 2伸區，以贼發生輯道效應。源極歧極延伸區的 形成方法例如是傾斜角離子植入法。Then, referring to FIG. 3C, in the recess 31, the deposition source and the electrodeless layer 2 are in-contact, and the process of the gold-oxygen half-effect transistor is further included in the channel region 306 and the recess 31. A source of shallow dip and a region of no extension are formed, and the thief has a sweep effect. The method of forming the source-polarity extension region is, for example, a tilt angle ion implantation method.
貫婦彳巾’此金氧半場效電晶體為PMQS，源極 312之材料例如是㈣。此外，源極與汲極層祀 如是紹。源極與汲極層312的形成方法例如是 晶_製程，贿_僅抑上成長，而不會在 卜上成長。換言之，矽鍺僅會在閘極304b及凹陷310 具成J，而不會在隔離結構302或補償間隙壁304c上成 、、/進仃選擇性蟲晶製程時，會同時在閘極304b 外 '盾二、亟與沒極層312相同材料的半導體層314。此 是在形===4P型摻，，型摻質例如 注入。告麸，:/層312打進仃臨场（ln-situ)摻雜而 後進行::場的可以在形成源極與没極層312之 子。 ，雜而，主入。另外，P型摻質例如是硼離 14 12995¾ Ό-2005-0706 18973twf.doc/e 此外，睛繼續參照圖3C。在另一實施例中，此金&“ 場效電晶體為NMOS，則源極與汲極層312之材料例氧， 矽碳。此外，源極與汲極層312之結構例如是磊晶疋 與汲極層312的形&方法例如{選擇性遙曰曰曰沉積^ /「極 使石夕碳僅在％上成長，而不會在氧切上成長。、^之以 石夕碳僅會在閘極鳩及凹陷上成長，而不會在^级 ，302及補償間隙壁驗上成長。因此，於進行選擇= 晶製程時’會同時在閘極3〇4b上形成與源極與沒極 =材料的半導體層314。另外，源極触極層312曰 =有N型摻質。N型摻_如是在形成源極舰 =行臨場摻胸注人。當然，N型射也可以在形成 極與錄層312之後進行非臨場的摻雜而注人 = 面，N型摻質例如是磷離子或砷離子。 万The female oxygen half-field effect transistor is PMQS, and the source 312 material is, for example, (four). In addition, the source and drain layers are as follows. The method of forming the source and drain layers 312 is, for example, a crystal process, and the bribe is only growing up and not growing up. In other words, the crucible will only have J in the gate 304b and the recess 310, and will not be formed on the isolation structure 302 or the compensation spacer 304c, and will be simultaneously outside the gate 304b. A semiconductor layer 314 of the same material as the shield 2 and the gate electrode 312. This is in the form of ===4P type doping, type doping such as injection. The bran, :/ layer 312 is immersed in the on-site (ln-situ) doping and then:: the field can be formed in the source and the electrodeless layer 312. Miscellaneous, the main entry. Further, the P-type dopant is, for example, boron ion 14 129 953⁄4 Ό-2005-0706 18973 twf.doc/e Further, the eye continues with reference to FIG. 3C. In another embodiment, the gold & field effect transistor is NMOS, and the source and drain layer 312 are made of oxygen, germanium carbon. Further, the source and drain layer 312 is, for example, epitaxial. The shape & method of the 疋 and the bungee layer 312, for example, {selective remote deposition ^ / "extremely makes Shi Xi carbon grow only in %, and does not grow on the oxygen cut. It will only grow on the gates and depressions, and will not grow on the level, 302 and compensation gaps. Therefore, when selecting = crystal process, it will form and source on the gate 3〇4b at the same time. And the semiconductor layer 314 with the electrodeless material. In addition, the source contact layer 312 曰 = has N-type dopant. The N-type doping _ is in the formation of the source ship = line on-site with a chest implant. Of course, N-type shot also The non-field doping may be performed after the formation of the pole and recording layer 312, and the N-type dopant is, for example, a phosphorus ion or an arsenic ion.
鮮請參照目3D，於閉極結構304兩侧及源極與汲 =二兩侧無離結構302上形成間隙壁3 J 316的材料例如是氧切或氮切， ^ς :::如_是於圖3C的結構上覆蓋-層絕成 =刻餘，直縣錄極纽極區 搬的交界處形成間隙壁训。此外:層312及祕結構 形成於閘極結構綱的兩侧。心刀間隙壁316也會 值得—提的是，在間隙壁316 隔離結構302的-部分厚声，㈣-成之則可以先移除 及源極與沒極層216的頂^ ^離結構202的頂表面 貝表面的阿度差變大。從而確保間 I2995^d 2005-0706 18973twf.doc/e 隙壁316能夠同時形成於閘極結構3〇4的兩側以及源極與 没極層312與隔離結構3〇2的交界處上。 隨後，於源極與汲極層312及半導體層314上形成一 層金屬矽化物層318,以降低後續形成的接觸窗與源極與 汲極層312的接觸電阻。金屬矽化物層318例如是鎳矽^ 物或鈷矽化物，而金屬矽化物層318的製造方法例如是自 行對準金屬矽化物製程。 本發明的金氧半場效電晶體由於在源極與没極層的兩 側與隔離結構上形财_壁，錄擋金射化物層在隔 離結構和_歧則的交界處絲，·能_止金屬 矽化物層與基底連接，從而避免接合漏電。 _ 以下說明上述兩種製造方法所製作的金氧半場效電 曰曰體釔構。清同時參照圖2E及圖3D，因為第一實施例是 先於閘極結構204兩侧製作第一間隙壁2〇8b，再形成源極 與没極層216 ;第二實施例是先在閘極結構綱兩側形成 源極與汲極層312,再形成間隙壁316，所以，大體而言， 圖2E與圖3D為具有不同製造程序的相似結構。因此，以 下僅就圖3D的結構進行說明。此外，圖2E與圖3D的結 構並不限於以上述的製造方法來製作。 凊_參照圖3D’本發明的金氧半場效電晶體包括基底 3〇〇胃、隔離結構302、閘極結構3〇4、源極與汲極層312、 半層314、間隙壁316及金屬矽化物層318。基底300 例如=矽基的基底。閘極結構3〇4配置於基底3㈨上，包 括間"電層304a、閘極304b及補償間隙壁304c。間隙壁 16 1299¾¾ -2005-0706 18973twf.doc/e 316位於閘極結構304之側壁上，以及位於源極與汲極層 312之側壁與隔離結構302上，且間隙壁216的材料例如 是氧化矽或氮化矽。金屬矽化物層318位於源極與汲極層 312及半導體層314上，且金屬矽化物層318的材料例如 • 是鎳梦化物及姑矽化物。 源極與汲極層312位於閘極結構3〇4兩側的基底3〇〇 中，並且源極與汲極層312的頂表面高於隔離結構3〇2的 頂表面，半導體層314位於閘極304b上。源極與汲極層 312及半導體層314之結構例如是磊晶。在一實施例中， 若此金氧半場效電晶體為PMOS，源極與汲極層312及半 導體層314的材料例如是矽鍺，且可以含有p型摻質。在 另一實施例中，若此金氧半場效電晶體為1^皿〇3，源極與 汲極層312及半導體層的材料例如是矽碳，且可以含有^ 型摻質。 由上述可知，本發明由於在源極與汲極層側壁以及隔 離〜構上设置有間隙壁，因此在製造過程中，金屬石夕化物 • 層不會於源極與汲極— 層與隔離結構的交界處成長，從而防 止，屬矽化物層與基底連接，避免接合漏電的問題。 【弟二實施例】 圖4A至圖4F是本發明一實施例的互補式金氧半場效 電晶體的製造流程剖面圖。 、請參照圖4A，提供基底4〇〇，且基底400上例如已形 成有隔離結構402與閘極結構404。基底400可分為第一 =件區400a及第二元件區4〇〇b。在本實施例中，後續的 製程是在第一元件區4〇〇a上形成NMOS，並於第二元件 17 129951 2005-0706 18973twf.doc/e 區400b上形成PMOS。閘極結構404是由閘介電層4〇4a、 及閘極404b所構成。其中閘介電層4〇4a位於閘"極4〇扑 及基底400之間’且閘介電層404a的材料例如是氧化矽， 閘極404b的材料例如是摻雜多晶矽。此外，閘極結構4〇4 下方的基底彻是做為此互補式金氧半場效電晶體的通道 區 406 〇 椏考，諝餐照圖 .以…、叫nru ,⑺卿祐偁4ϋ4的側壁上形 補償間隙壁408，並接著於基底400上覆蓋一層帽罢層 41〇。其中補償間隙壁408的材料例如是氮化矽，而帽： ^1〇的材料例如是氧化梦。隨後，於第—元件區她上覆 蓋一層圖案化光阻層411。 接^，請參照圖4C，以圖案化光阻層41〇為 區伽^帽蓋層 4^2，而移除部分基底娜⑽第二^ ，與隔離結構402之間的基底中形 式蝕刻製€ 412例如是反應性離子 ^ 412的反應氣體例如是六氟化二碳及氦氣乾该刻Μ 繼之，請參照圖4D，於 層416。在一較佳實施例中:極與没極 的製程更包括於篦--# 式金氧半％效電晶體 道效應。源極與沒極延，以避免發生短通 植入法。 、伸£的形成方法例如是傾斜角離子 源極與汲極層416之她时销。此外，源極與 18 129951 2005-0706 18973twf.doc/e 汲極層416之結構例如是磊晶。源極與汲極層416的形成 方法例如是選擇性磊晶沉積製程，以使矽鍺僅在矽上成 長，而不會在氧化矽上成長。換言之，矽鍺僅會在閘極4〇牝 及凹陷414上成長，而不會在隔離結構4〇2或補償間隙壁 恥8上成長。因此，於進行選擇性磊晶製程時，會同時在 第二元件區400b的閘極404b上形成與源極與汲極層416 相同材料的半導體層418。此外，源極與汲極層416例如 f有P型摻質，此P型摻質例如是硼離子。p型摻質例如 是在形成源極與汲極層416時進行臨場摻雜而注入。當 然，p型摻質也可以在形成源極與汲極層416之後進行非 臨场*的換雜而注入。 _ 繼之，凊參照圖4E，移除第一元件區4〇〇a的帽蓋層 410，此處值得注意的是，在移除第一元件區4〇〇a的帽蓋 層410的同時，將會同時移除第二元件區4〇%的隔離結構 402的部分厚度’以使得隔離結構4〇2 &頂表面及源極與 汲極層416的頂表面的高度差變大，有利於後續間隙壁的 ，成。接著，於第一元件區400a的補償間隙壁4〇8的侧壁、 第二元件區400b的補償間隙壁4〇8的側壁以及源極與汲極 層416的侧壁與隔離結構4〇2上形成間隙壁42()。 繼之，請參照圖4F，於第二元件區4〇〇b上覆蓋一層 圖案化光阻層（未緣示），並進行一離子植入製程，以於 第一兀件區400a的間隙壁420兩侧的基底4〇〇中形成源極 與汲極區422。源極與汲極區422的摻質例如是磷離子或 砷離子。接著，移除這層圖案化光阻層。在一較佳實施例 12995¾¾ D-2005-0706 18973twf.doc/e 12995¾¾ D-2005-0706 18973twf.doc/e 中 此互補式金氧半場效電晶體的製程更包括於第一元件 區400a的源極與汲極區422與通道區4〇6之間形戌 雜的源極無觀輕，以魏發生賴奴應。源= 汲極延伸區的形成方法例如是傾斜角離子植入法。/、 然後，於第一元件區的閘極404b、源極與汲極層‘Μ 半導體層418以及源極與沒極區422上形成一層金曰屬石夕化 物層424。金屬梦化物| 424的材料例如是錄魏物或銘 矽化物，且金屬矽化物層424的形成方法例如是自行對準 金屬石夕化物製程。由於在第二元件區4_的源極與沒極層 416兩侧及隔離結構402上形成有間隙壁42〇，因此金屬ς 化物層424不會在源極與沒極層416與隔離結構的交 界處成長，從而避免接合漏電。 另一方面，在另一實施例的互補型金氧半場效電晶體 中，NMOS是形成於第二元件區400b，而pM〇s是^成 於第一元件區400a。此互補型金氧半場效電晶體的源極與 汲極層416的材質例如是矽碳、其結構例如是磊晶，且源 極與汲極層416例如#有鱗離子或砷離子等N型摻質。再 者，源極與汲極區422例如摻有硼離子。除此之外，此互 補型金氧半場效電晶體的製造方法與上述的製程類似，因 此不再重複說明此另一實施例。Please refer to item 3D. The material for forming the spacer 3 J 316 on both sides of the closed-pole structure 304 and the source and the 汲= two-side non-detachment structure 302 is, for example, oxygen cutting or nitrogen cutting, ^ς :::如_ It is on the structure of Figure 3C that the cover-layer is completed = engraved, and the gap is formed at the junction of the county. In addition, the layer 312 and the secret structure are formed on both sides of the gate structure. The core knife spacer 316 is also worth mentioning that the portion of the spacer 316 isolation structure 302 is thick, and the (four)-forming is removed first and the source and the bottom layer 216 are removed from the structure 202. The difference in the surface of the top surface of the shell surface becomes larger. Thereby, it is ensured that the interlayer 316 can be simultaneously formed on both sides of the gate structure 3〇4 and at the boundary between the source and the gate layer 312 and the isolation structure 3〇2. Subsequently, a metal germanide layer 318 is formed over the source and drain layers 312 and the semiconductor layer 314 to reduce the contact resistance of the subsequently formed contact window with the source and drain layers 312. The metal telluride layer 318 is, for example, a nickel ruthenium or a cobalt ruthenium, and the method of fabricating the metal telluride layer 318 is, for example, a self-aligned metal ruthenium process. The gold-oxygen half-field effect transistor of the present invention has a shape on the two sides of the source and the non-polar layer and the isolation structure, and the gold-recording layer is recorded at the boundary between the isolation structure and the _discrimination. The metal halide layer is connected to the substrate to avoid junction leakage. _ The following describes the gold-oxygen half-field electric 钇 structure fabricated by the above two manufacturing methods. Referring to FIG. 2E and FIG. 3D simultaneously, in the first embodiment, the first spacers 2〇8b are formed on both sides of the gate structure 204, and the source and the gate layer 216 are formed. The second embodiment is the gate first. The source and drain layers 312 are formed on both sides of the pole structure, and the spacers 316 are formed. Therefore, in general, FIGS. 2E and 3D are similar structures having different manufacturing procedures. Therefore, only the structure of Fig. 3D will be described below. Further, the structures of Figs. 2E and 3D are not limited to being fabricated by the above-described manufacturing method. Referring to FIG. 3D', the MOS field effect transistor of the present invention includes a substrate 3 gastro-intestinal, isolation structure 302, gate structure 3〇4, source and drain layer 312, half layer 314, spacer 316, and metal. Telluride layer 318. The substrate 300 is, for example, a base of a fluorene group. The gate structure 3〇4 is disposed on the substrate 3 (9), and includes an electrical layer 304a, a gate 304b, and a compensation spacer 304c. A spacer 16 12993⁄43⁄4 -2005-0706 18973twf.doc/e 316 is located on the sidewall of the gate structure 304 and on the sidewalls of the source and drain layers 312 and the isolation structure 302, and the material of the spacer 216 is, for example, hafnium oxide. Or tantalum nitride. The metal telluride layer 318 is on the source and drain layers 312 and the semiconductor layer 314, and the material of the metal telluride layer 318 is, for example, a nickel dream compound and a ruthenium compound. The source and drain layers 312 are located in the substrate 3〇〇 on both sides of the gate structure 3〇4, and the top surface of the source and drain layers 312 is higher than the top surface of the isolation structure 3〇2, and the semiconductor layer 314 is located at the gate. On pole 304b. The structure of the source and drain layers 312 and the semiconductor layer 314 is, for example, epitaxial. In one embodiment, if the MOS field-effect transistor is a PMOS, the material of the source and drain layers 312 and the semiconductor layer 314 is, for example, germanium and may contain a p-type dopant. In another embodiment, if the MOS field-effect transistor is 1 〇 3, the source and drain layers 312 and the material of the semiconductor layer are, for example, germanium carbon, and may contain a dopant. As can be seen from the above, in the present invention, since the spacers are provided on the sidewalls of the source and the drain layer and the isolation structure, the metallization layer does not exist in the source and the drain layer and the isolation structure during the manufacturing process. The junction grows to prevent the bismuth layer from being connected to the substrate to avoid the problem of joint leakage. [Second Embodiment] Figs. 4A to 4F are cross-sectional views showing a manufacturing process of a complementary MOS field effect transistor according to an embodiment of the present invention. Referring to FIG. 4A, a substrate 4 is provided, and an isolation structure 402 and a gate structure 404 are formed, for example, on the substrate 400. The substrate 400 can be divided into a first member region 400a and a second component region 4〇〇b. In the present embodiment, the subsequent process is to form an NMOS on the first element region 4a, and a PMOS on the second element 17 129951 2005-0706 18973 twf.doc/e region 400b. The gate structure 404 is composed of a gate dielectric layer 4A4a and a gate 404b. The gate dielectric layer 4〇4a is located between the gate electrode and the substrate 400, and the material of the gate dielectric layer 404a is, for example, hafnium oxide. The material of the gate electrode 404b is, for example, doped polysilicon. In addition, the base under the gate structure 4〇4 is completely made into the channel region 406 of this complementary MOS field-effect transistor, and the 谞 照 照 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以The spacers 408 are over-shaped and then covered with a layer of caps 41 on the substrate 400. The material in which the spacer 408 is compensated is, for example, tantalum nitride, and the material of the cap: ^1〇 is, for example, an oxidative dream. Subsequently, a patterned photoresist layer 411 is overlaid on the first component region. Referring to FIG. 4C, the patterned photoresist layer 41 is used as the region capping layer 4^2, and the portion of the substrate (10) is removed, and the substrate is etched in the substrate between the spacer structure 402. For example, the reactive gas of the reactive ion 412 is, for example, hexafluoride dicarbonate and helium gas, followed by Figure 4D at layer 416. In a preferred embodiment, the pole and immersion processes are further included in the 篦--type MOS half-effect transistor effect. The source is not extremely extended to avoid short-pass implantation. The forming method of the stretching is, for example, the tilting angle ion source and the draining layer 416. Further, the source and the structure of the gate layer 416 are, for example, epitaxial. The method of forming the source and drain layers 416 is, for example, a selective epitaxial deposition process so that the germanium grows only on the crucible without growing on the hafnium oxide. In other words, 矽锗 will only grow on the gate 4〇牝 and the recess 414 without growing on the isolation structure 4〇2 or the compensation gap 8 . Therefore, in the selective epitaxial process, the semiconductor layer 418 of the same material as the source and drain layers 416 is simultaneously formed on the gate 404b of the second element region 400b. Further, the source and drain layers 416, e.g., have a P-type dopant, such as a boron ion. The p-type dopant is implanted, for example, by field doping when the source and drain layers 416 are formed. Of course, the p-type dopant can also be implanted by non-field* after the source and drain layers 416 are formed. </ RTI> Next, referring to FIG. 4E, the cap layer 410 of the first element region 4A is removed, where it is noted that while the cap layer 410 of the first element region 4A is removed, At the same time, the partial thickness ' of the isolation structure 402 of the second element region 4% is removed to make the height difference between the top surface of the isolation structure 4 〇 2 & the source and the top surface of the drain layer 416 larger, which is advantageous In the subsequent gap wall, into. Next, the sidewall of the compensation spacer 4〇8 of the first element region 400a, the sidewall of the compensation spacer 4〇8 of the second element region 400b, and the sidewall of the source and drain layer 416 and the isolation structure 4〇2 A spacer 42 () is formed thereon. Then, referring to FIG. 4F, the second component region 4〇〇b is covered with a patterned photoresist layer (not shown), and an ion implantation process is performed to form a spacer of the first component region 400a. A source and a drain region 422 are formed in the substrate 4 on both sides of the 420. The dopant of the source and drain regions 422 is, for example, a phosphorus ion or an arsenic ion. Next, the patterned photoresist layer is removed. The process of the complementary MOS field effect transistor is further included in the source of the first element region 400a in a preferred embodiment 129953⁄43⁄4 D-2005-0706 18973 twf.doc/e 129953⁄43⁄4 D-2005-0706 18973 twf.doc/e The source of noisy between the pole and the bungee zone 422 and the channel zone 4〇6 is not light, and it takes place in Wei. The source = formation method of the drain extension region is, for example, a tilt angle ion implantation method. Then, a layer of a ruthenium-like layer 424 is formed on the gate 404b of the first element region, the source and drain layers Μ semiconductor layer 418, and the source and the gate region 422. The material of the metal dreaming material 424 is, for example, a recording material or a germanium compound, and the metal halide layer 424 is formed by, for example, a self-aligned metallization process. Since the spacer 42 is formed on both sides of the source and the gate layer 416 of the second element region 4_ and the isolation structure 402, the metal telluride layer 424 is not in the source and the gate layer 416 and the isolation structure. The junction grows to avoid joint leakage. On the other hand, in the complementary MOS field effect transistor of another embodiment, the NMOS is formed in the second element region 400b, and pM 〇 s is formed in the first element region 400a. The source of the complementary metal oxide half field effect transistor and the material of the drain layer 416 are, for example, germanium carbon, and the structure thereof is, for example, epitaxial, and the source and drain layers 416 are, for example, N-type such as scale ions or arsenic ions. Doping. Further, the source and drain regions 422 are doped with, for example, boron ions. In addition, the manufacturing method of this complementary type MOS field effect transistor is similar to that of the above-described process, and thus this other embodiment will not be repeatedly described.
顯而易見，在又一實施例中，此互補型金氧半場效電 晶體的NMOS及PMOS的源極與没極層的材質例如分別 是矽碳及矽鍺。源極與汲極層的結構例如均是磊晶，且例 如摻有N型摻質與P型摻質。換言之，NMOS及PMOS 1299m -2005-0706 18973twf.doc/e 可以均以第二元件區4〇〇b的製程來製作。 表τ、上所述，由於在源極與汲極層的兩側及隔離結構上 形成有間隙壁，因此能夠防止金屬石夕化物層在源極與汲極 層和隔離結構的交界處成長，避免金屬矽化物層與基底連 接，而可以防止接合漏電的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本發明、’，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知一種金氧半場效電晶體的剖面示意圖。 圖2A至圖2E是本發明之第一實施例之金氧半場效電 晶體的製造流程剖面圖。 圖2E’是圖2E的金氧半場效電晶體在經過本發明另 一實施例之製造流程所得到的結構。 圖3A至圖3D是本發明的第二實施例之金氧半場 電晶體的製造流程剖®圖。 > 圖4A至圖4F是本發明第三實施例的互補式金氧半p 效電晶體的製造流程剖面圖。 野 【主要元件符號說明】 100、200、300、400 :基底 102、204、304、404 :閘極結構 104、204a、304a、404a :閘介電層 106、216、312、416 :源極與汲極層 21 12995¾¾ D-2005-0706 18973twf.doc/e 108、220、318、424 :金屬矽化物層 110、202、302、402 :隔離結構 112 :交界處 • 204b、304b、404b :閘極 - 206、306、406 :通道區 208a、304c、408 :補償間隙壁 208b :第一間隙壁 408 :介電層 ❿ 212、308、412 :乾式蝕刻製程 214、310、416 :凹陷 218 :第二間隙壁 217、314、418 :半導體層 216、420 :間隙壁 410 :帽蓋層 411 :圖案化光阻層 422 :源極與汲極區 22It is apparent that in still another embodiment, the materials of the NMOS and PMOS sources and the electrodeless layer of the complementary MOS field-effect transistor are, for example, germanium carbon and germanium. The structures of the source and drain layers are, for example, epitaxial, and are, for example, doped with an N-type dopant and a P-type dopant. In other words, the NMOS and PMOS 1299m -2005-0706 18973twf.doc/e can all be fabricated in the process of the second component region 4〇〇b. In the above table, since the spacers are formed on both sides of the source and the drain layer and the isolation structure, it is possible to prevent the metallurgical layer from growing at the boundary between the source and the drain layer and the isolation structure. The metal halide layer is prevented from being connected to the substrate, and the problem of junction leakage can be prevented. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional gold oxide half field effect transistor. Fig. 2A to Fig. 2E are cross-sectional views showing the manufacturing process of the gold-oxygen half field effect transistor of the first embodiment of the present invention. Fig. 2E' is a structure of the gold-oxygen half field effect transistor of Fig. 2E obtained by the manufacturing process of another embodiment of the present invention. Fig. 3A to Fig. 3D are sectional views of the manufacturing process of the gold-oxygen half field transistor of the second embodiment of the present invention. > Fig. 4A to Fig. 4F are cross-sectional views showing the manufacturing process of a complementary MOS filter according to a third embodiment of the present invention. [Main component symbol description] 100, 200, 300, 400: substrate 102, 204, 304, 404: gate structure 104, 204a, 304a, 404a: gate dielectric layer 106, 216, 312, 416: source and Datum layer 21 129953⁄43⁄4 D-2005-0706 18973twf.doc/e 108, 220, 318, 424: metal telluride layer 110, 202, 302, 402: isolation structure 112: junction • 204b, 304b, 404b: gate - 206, 306, 406: channel regions 208a, 304c, 408: compensation spacers 208b: first spacers 408: dielectric layers 212, 308, 412: dry etching processes 214, 310, 416: recesses 218: second Clearance walls 217, 314, 418: semiconductor layers 216, 420: spacers 410: cap layer 411: patterned photoresist layer 422: source and drain regions 22