CN101410960A - 在外延生长源漏区上选择性淀积覆盖层的结构与制造方法 - Google Patents

在外延生长源漏区上选择性淀积覆盖层的结构与制造方法 Download PDF

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CN101410960A
CN101410960A CNA2007800107810A CN200780010781A CN101410960A CN 101410960 A CN101410960 A CN 101410960A CN A2007800107810 A CNA2007800107810 A CN A2007800107810A CN 200780010781 A CN200780010781 A CN 200780010781A CN 101410960 A CN101410960 A CN 101410960A
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layer
nickel
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sige alloy
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T·小库克
B·泽尔
A·穆尔蒂
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Abstract

公开了改进自对准多晶硅化物的接触形成并减小晶体管的外部电阻的方法和装置。在衬底表面形成栅电极。在衬底中各向同性地蚀刻源区和漏区。在源区和漏区中用硼在原位对硅锗合金进行掺杂。在该硅锗合金上淀积硅。在该硅上淀积镍。在该硅锗合金上形成镍硅锗硅化物层。在该镍硅锗硅化物层上形成镍硅硅化物层。

Description

在外延生长源漏区上选择性淀积覆盖层的结构与制造方法
技术领域
[0001]本发明涉及半导体集成电路领域，具体来说，涉及MOS晶体管的形成。
背景技术
[0002]集成电路通常在硅和其它半导体衬底上制造。集成电路可包括在数平方厘米的面积上形成的数百万个互连的晶体管。
[0003]这样一种晶体管通常包括硅衬底上的栅介质层、栅介质层上的栅电极以及硅衬底中的栅电极两侧的源区和漏区。通常，通过将掺杂剂杂质注入硅衬底来制作源区和漏区。
[0004]为了增加电子迁移率和成本效益，硅锗被用作源区和漏区的材料。锗具有比硅大4.2％的晶格常数(例如原子间距)。硅锗还具有更大的晶格常数，其程度取决于锗的百分比成分。当硅在硅锗上生长时，在适当条件下，硅晶格伸展以匹配硅/硅锗界面上的硅锗晶格。在硅上生长硅锗时，在适当条件下，硅锗晶格受到压缩。对于每种方法，存在生长层(无论是硅还是硅锗)的临界厚度，超过这个厚度时，生长层由于晶格缺陷传播而松弛。
[0005]硅锗为由它组成的晶体管提供改进的速度特征，因为与元素硅相比，锗具有更低的电子有效质量和更低的空穴有效质量(引起更高的电子迁移率和更高的空穴迁移率)。硅锗合金获益于其组成成分锗的增加迁移率。另外，硅锗可形成改变材料的导带和价带的各向异性结构。在与具有不同带隙的其它半导体层(例如异质层)组合时，导带和价带不连续性可被设计成形成量子阱区或者内置电场，以加速越过异质层的截流子。
[0006]外延SiGe层中的锗量根据晶体管性能要求来选择(通常在15％与30％之间)。该锗量对于自对准多晶硅化物(salicide)与源漏区之间的接触电阻以及对于均匀自对准多晶硅化物形成可能都不是最佳的，从而会引起产率与性能的降低。
附图说明
[0007]以下通过示例而不是限制来说明本发明，附图中：
[0008]图1是根据一个实施例的相邻晶体管的横截面侧视图。
[0009]图2是表示图1的衬底中的凹陷部形成的横截面侧视图。
[0010]图3是表示图2的衬底的凹陷部中的硅锗合金形成的横截面侧视图。
[0011]图4是表示根据一个实施例的图3的衬底的硅锗上的硅淀积的横截面侧视图。
[0012]图5是表示根据一个实施例的图4的衬底上的掩模之去除的横截面侧视图。
[0013]图6是表示根据一个实施例的图5的衬底上金属淀积的横截面侧视图。
[0014]图7是根据一个实施例的图6的金属反应后的晶体管的横截面侧视图。
[0015]图8是表示个根据另一实施例的图3的衬底上掩模去除的横截面侧视图。
[0016]图9是表示根据另一实施例的图8的衬底上硅淀积的横截面侧视图。
[0017]图10是表示根据另一实施例的图9的衬底上金属淀积的横截面侧视图。
[0018]图11是表示根据另一实施例的图10的金属反应后的晶体管的横截面侧视图。
[0019]图12是表示根据一个实施例的用于制造图7和图11所示的晶体管的方法的流程图。
具体实施方式
[0020]以下描述阐明例如具体系统、部件、方法的示例等许多具体细节，以提供对本发明的若干实施例的透彻了解。然而，本领域的技术人员清楚地知道，即使没有这些具体细节也可实施本发明的至少部分实施例。在其它情况下，没有详细描述公知的材料或方法，或者以简单框图来提供众所周知的部件或方法，以免不必要地影响对本发明的理解。因此，所阐明的具体细节只是示范。具体实现可不同于这些示范细节，但仍然预期是在本发明的主旨和范围之内。
[0021]通过将硅锗合金用于源区和漏区、金属硅锗硅化物(metal silicon germanium silicide)层和金属硅硅化物(metal siliconsilicide)层以形成源区和漏区的接触面，本发明的一个实施例减小晶体管的外部电阻。例如，该金属可以是镍。硅锗与镍硅锗硅化物之间的界面具有较低的接触电阻率，该接触电阻率基于硅锗与镍硅锗硅化物之间降低的金属半导体功函数和硅锗对硅增加的截流子迁移率。镍硅硅化物可提供更好的接触形成。可对硅锗进行掺杂以进一步调整其电气属性。晶体管外部电阻的减小相当于在交换速度和功耗两个方面改善的晶体管性能。
[0022]图1示出在硅衬底106上制造两个相邻晶体管102、104的实施例。晶体管102是在p型衬底或阱区上制作的金属氧化物半导体(MOS)晶体管。晶体管104是在n型衬底或阱区上制作的金属氧化物半导体(MOS)晶体管。
[0023]图1所示的部分制成的晶体管102、104按常规工艺制造。将P型掺杂剂注入硅衬底106的左部以形成P阱区108。将N型掺杂剂注入硅衬底106的右部以形成N阱区110。P阱区108通过隔离区(又称作隔离墙)例如二氧化硅浅沟槽隔离(STI)区112与N阱区110分隔。
[0024]随后分别在P阱区108和N阱区110上生长栅介质层114、116。可用公知的材料如二氧化硅或氮化二氧化硅来制作栅介质层114、116。在一个实施例中，栅介质层114和116的厚度可小于约40□。栅电极可在该栅介质层上形成。例如，多晶硅栅电极118、120分别在栅介质层114、116上形成。可采用N型掺杂剂如磷或砷来对多晶硅栅电极118掺杂。可采用P型掺杂剂如硼来对多晶硅栅电极120掺杂。
[0025]源漏延伸区128和130可分别在多晶硅栅电极118、120的两侧形成。也可分别在多晶硅栅电极118、120的两侧形成垂直侧壁隔层122和124。根据一个实施例，垂直侧壁隔层122和124可由SiO2或SiBN14形成。
[0026]掩模126可在晶体管104上形成。更具体来说，掩模126淀积在多晶硅栅电极120、垂直侧壁隔层124以及N阱区110的其余外露表面上。根据一个实施例，掩模126可充当后续处理步骤的阻挡层。
[0027]如图2所示，随后蚀刻成进入P阱区108的上表面的凹陷部202。可用各向同性蚀刻剂来有选择地去除S/D延伸区118、120以及沟槽隔离区112、栅介质层114和侧壁隔层122之间的外露硅。蚀刻继续进行，直到在栅介质层114之下形成凹陷部202的尖端部分204。因此，源和漏的凹陷部202在多晶硅栅电极118的两侧和下方形成。源和漏的凹陷部202在多晶硅栅电极118下有各自的尖端部分204。沟道区206规定在尖端部分204之间。晶体管104的掩模126暂时阻止对晶体管104的进一步加工。
[0028]图3示出源区和漏区形成之后的图2的结构。可通过在凹陷部202中外延生长硅锗而形成硅锗层302来形成源区和漏区。应当注意，硅锗有选择地在硅衬底106的材料上生长，与浅沟槽隔离区112、栅介质层114、侧壁隔层122和掩模126的材料相对。硅锗晶体不在SiO2或Si3N4介质层上生长。本领域的技术人员当知，有许多用于淀积硅锗的公知技术。例如，一种淀积技术可是减压化学汽相淀积(“CVD”)外延淀积。其它的淀积技术包括大气CVD外延和超高真空CVD外延。当淀积硅锗层302由单晶形成时，每种淀积技术是汽相外延的特定形式。在一个实施例中，硅锗合金可包括约5％至约50％之间的锗成分。
[0029]根据一个实施例，硅锗淀积方法包括CVD外延。外延可在10与760托之间的压力下、在600℃与800℃之间进行。H2、N2或He可用作载气。硅源前驱气体可以是SiH2Cl2、SiH4或Si2H6。在一个实施例中，GeH4是锗源前驱气体。可添加HCl或Cl2作为蚀刻剂，以增加淀积的材料选择性。在一个实施例中，所得硅锗层302可在凹陷部中淀积，以形成源区和漏区。硅锗层302的厚度在约500与约2000
Figure A20078001078100091
之间。图3示出其中淀积硅锗层302在衬底106的顶面上延伸的实施例。硅锗层302在衬底106的顶面之上和之下形成。通过在衬底106的顶面之上形成硅锗层302，形成升高的源漏区，从而提高电导率。提高的电导率又可改进器件性能。在另一实施例中，硅锗层302的厚度在约200与约1000
Figure A20078001078100092
之间。
[0030]可对硅锗层302进行掺杂以调整其电学和化学属性。掺杂可使用各种掺杂剂并采用各种掺杂技术来进行。例如，可采用p型杂质如硼，在原位将硅锗掺杂到1×1018/cm3与3×1021/cm3之间的掺杂剂浓度级，优选为约1×1020/cm3的浓度。在制造PMOS器件的实施例中，通过在硅锗外延淀积期间使用上述前驱物质和附加B2H6前驱气体作为硼掺杂剂的源，在外延期间采用硼在原位对硅锗进行掺杂。原位掺杂硅锗的有益效果在于，凹陷部202的形状使得难以在被侧壁隔层122遮蔽的区域中淀积了硅锗之后对硅锗进行掺杂。本领域的技术人员当知，也可用其它技术对硅锗层302进行掺杂。
[0031]在一实施例中，在硅锗淀积期间所添加的硼掺杂剂的一小部分这时没有被激活。也就是说，在淀积之后，硼原子处于硅锗层302中，但尚未被替换到晶格中可提供空穴(即缺少电子)的硅位置。在一实施例中，将掺杂剂的热激活推迟到后续处理步骤(例如硅化物退火)，从而减少热衡算并得到掺杂剂扩散，以能够形成很陡的源/漏结，从而改进器件性能。
[0032]如前所述，淀积的硅锗具有较大的晶格常数，其量级取决于硅锗合金中锗的原子百分比。在硅衬底106上淀积时，硅锗的晶格被压缩以适应晶体生长。形成源区和漏区的硅锗层302的压缩，进一步引起设置在硅锗源区和漏区之间以及栅介质层114之下(即晶体管102的沟道206)的硅衬底106的区域中的压缩。该压缩在沟道区中形成各向异性原子结构，从而改变沟道材料的导带和价带。该压缩的应力还减小硅衬底106的沟道区域中的空穴有效质量，从而又增加空穴迁移率。增加的空穴迁移率可提高所得到的MOS晶体管的饱和沟道电流，由此改进器件性能。
[0033]图4示出根据一个实施例的在淀积牺牲层后的图3的结构。在一个实施例中，牺牲层包括有选择地淀积在硅锗层302的外露表面上的薄硅层402。应当注意，有选择地在硅锗衬底302的材料上生长硅，与浅沟槽隔离区112、栅介质层114、侧壁隔层122和硬掩模126的材料相对。硅层402不在SiO2或Si3N4介质层上生长。硅层402的厚度范围可从200
Figure A20078001078100101
至400，这取决于待淀积在硅层402上的金属的类型和厚度。在一个实施例中，淀积技术可包括减压化学汽相淀积(“CVD”)外延淀积。在其它实施例中，淀积技术包括大气CVD外延和超高真空CVD外延。在淀积的硅层402由单晶形成时，各淀积技术是一种特定形式的汽相外延。在另一实施例中，牺牲层包括硅锗，其中锗的成分小于硅锗层中的锗。例如，牺牲层包括具有可达到约30％的锗成分的硅锗。
[0034]由于两个理由，淀积过程可包括将气体送往通风孔：(1)为了稳定预期的设置点处的DCS和HCL流；(2)为了让温度跳跃到预期温度(在777℃与825℃之间)。
[0035]图5示出根据一个实施例的从晶体管104去除掩模126后的图4的结构。去除掩模126，从而留下如图5所示外露的晶体管104的结构。具体来说，晶体管104的外露部分包括源漏区130、侧壁隔层124和栅电极120。晶体管102的外露部分包括硅层402、侧壁隔层122和栅电极118。
[0036]图6示出淀积金属后的图5的结构。在晶体管102以及104上均淀积金属602如镍。本领域的技术人员当知，有许多淀积金属602的方法。一例淀积技术是标准溅射技术(即物理汽相淀积即“PVD”)。金属602与晶体管102和104的某些成分发生反应。然后去除没有与晶体管102和104的成分发生反应的金属602。
[0037]图7示出根据一个实施例的在图6中金属与晶体管102、104发生反应后的晶体管的横截面侧视图。图7还示出自对准硅化物层702和704的形成。本领域的技术人员当知，硅化物层通过淀积薄层的难溶金属而形成。
[0038]难溶金属中还包括钴、钛和镍。在一实施例中，该难溶金属是镍。难溶金属的选择不仅需要考虑与占据相同衬底上的对应NMOS器件的源区和漏区以及外露源区和漏区的基础硅锗层302的电学兼容性，而且还要考虑机械和化学兼容性。例如，该硅化物层必须是连续且均匀的，以有助于减小该硅化物层与该基础硅锗层302之间的界面电阻。镍易于与硅和锗均匀反应，从而形成稳定的三元Ni(SiGe)相，而钴和钛优先与硅发生反应，并离析硅锗合金302中的锗成分。另外，与镍硅锗硅化物相比，基于钛和钴的硅锗硅化物具有降低的热稳定性。不适当的难溶金属选择会造成硅化物与半导体之间的不理想界面，这会增加界面电阻，与否则应电学兼容的材料无关。
[0039]图7示出其中难溶金属为PVD镍的一个实施例。根据环境，PVD镍淀积在20℃与200℃之间并且在小于50毫托的压力下进行。镍的厚度可在50与200
Figure A20078001078100111
之间。镍淀积后用例如快速退火(“RTA”)设备在325℃与450℃之间进行小于或等于60秒钟的快速形成退火。在形成退火期间，硅层402上的镍层602发生反应，形成第一镍硅锗硅化物层702和第二镍硅硅化物层704，如图7所示。在一个实施例中，淀积镍602的厚度在约200与400之间。在将镍602淀积到硅衬底106的整个外露表面时，通过例如热H2O2和热H2SO4的混合物的湿式蚀刻化学处理来去除未反应的镍(即没有与硅或硅锗发生反应而在被淀积到侧壁隔层122或隔离区112上面时与其基础层形成硅化物的镍)。硅锗层302上面的剩余未反应镍(源区和漏区)以及栅区118然后经过400℃与550℃之间的最后退火，以完成镍硅锗硅化物702和镍硅硅化物704的形成，如图7所示。硅化物层702和704还可例如由氮化钛盖(未示出)覆盖，以防止镍硅锗硅化物层702和镍硅硅化物层704在后续处理步骤中氧化，如本领域所周知。在一个实施例中，各硅化物层的厚度在200与400
Figure A20078001078100122
之间。
[0040]图8示出根据另一实施例的从晶体管104去除了掩模126后的图3的结构。掩模126去除后留下如图8所示外露的晶体管104的结构。具体来说，晶体管104的外露部分包括源漏区130、侧壁隔层124和栅电极120。
[0041]图9示出根据一个实施例的在淀积牺牲层后的图8的结构。牺牲层可包括例如硅。有选择地将薄硅层902淀积在晶体管106的硅锗层302的外露表面。将薄硅层902淀积在晶体管104的源漏区130的外露表面上。硅层902的厚度范围可从200至400
Figure A20078001078100124
，这取决于待淀积在硅层902上的金属的类型和厚度。前面参照图4描述了硅层902的淀积过程。
[0042]图10示出淀积金属1002如镍后的图9的结构。金属层1002的淀积过程在前面参照图6作了描述。
[0043]图11示出金属与晶体管102和104发生反应后的图10的结构。该反应过程在前面参照图7作了描述。
[0044]图12是表示用于制造图7和图11的晶体管的方法的流程图。在步骤1202，如图1所示形成栅电极。在步骤1204，如图2所示在衬底中蚀刻源区和漏区。在步骤1206，如图3所示在源区和漏区中淀积硅锗合金。在步骤1208，如图4和图9所示在硅锗合金上淀积材料的牺牲层。在一个实施例中，该牺牲层包括硅。在步骤1210，如图6和图10所示在牺牲层上淀积金属如镍。在该金属、牺牲层和硅锗合金之间的接触形成两个硅化物层。在步骤1212，该金属与硅锗发生反应，形成第一硅化物层。在一个实施例中，第一硅化物层包括通过镍与硅锗发生反应所形成的镍硅锗硅化物。在步骤1214，该金属与牺牲层发生反应，形成第二硅化物层。在一个实施例中，第二硅化物层包括通过镍与硅发生反应所形成的镍硅硅化物。
[0045]虽然以具体顺序示出和描述了本文中的方法的操作，但是，每个方法的操作顺序可以改变，某些操作可按相反顺序来执行，或者某些操作可至少部分地与其它操作同时执行。在另一实施例中，一些截然不同的操作的指令或子操作可采取间歇和/或交替方式。
[0046]在以上说明中，参照其中的具体示范实施例描述了本发明。但是很显然，可对其进行各种修改和变更，而不背离所附权利要求书规定的本发明的更宽的主旨和范围。本说明书和附图因此被视为是说明性而不是限制性的。

Claims (20)

1.一种方法，包括：
在衬底表面上形成栅电极；
在所述衬底中各向同性地蚀刻源区和漏区；
在所述源区和所述漏区中淀积硅锗合金；
在所述硅锗合金上淀积材料的牺牲层，该牺牲层的锗浓度低于所述硅锗合金的锗浓度；
在所述牺牲层上淀积金属；
在所述硅锗合金上形成第一硅化物层；以及
在所述第一硅化物层上形成第二硅化物层。
2.如权利要求1所述的方法，还包括：用硼在原位对所述硅锗合金进行掺杂。
3.如权利要求1所述的方法，其中，所述硅锗合金具有高于所述衬底表面所规定平面的顶面。
4.如权利要求1所述的方法，其中，所述硅锗合金具有约5％与约50％之间的锗成分。
5.如权利要求1所述的方法，其中，所述硅锗合金具有约
Figure A2007800107810002C1
与约
Figure A2007800107810002C2
之间的厚度。
6.如权利要求1所述的方法，其中，所述牺牲层包括硅。
7.如权利要求6所述的方法，其中，所述硅具有约与约
Figure A2007800107810002C4
之间的厚度。
8.如权利要求1所述的方法，其中，所述牺牲层包括具有最高可达30％的锗成分的硅锗。
9.如权利要求1所述的方法，其中，所述金属包括镍。
10.如权利要求9所述的方法，其中，所述镍具有约
Figure A2007800107810003C1
与约
Figure A2007800107810003C2
之间的厚度。
11.如权利要求9所述的方法，其中，所述第一硅化物层包括镍硅锗硅化物。
12.如权利要求11所述的方法，其中，所述镍硅锗硅化物具有约
Figure A2007800107810003C3
与约
Figure A2007800107810003C4
之间的厚度。
13.如权利要求9所述的方法，其中，所述第二硅化物层包括镍硅硅化物。
14.如权利要求13所述的方法，其中，所述镍硅硅化物具有约
Figure A2007800107810003C5
与约之间的厚度。
15.一种方法，包括：
在衬底表面形成栅电极；
在所述衬底中各向同性地蚀刻源区和漏区；
在所述源区和所述漏区中淀积硅锗合金；
用硼在原位对所述硅锗合金进行掺杂；
在所述硅锗合金上淀积硅；
在所述硅上淀积镍；
在所述硅锗合金上形成镍硅硅化物层；以及
在所述镍硅硅化物层上形成镍硅锗硅化物层。
16.如权利要求15所述的方法，其中，所述硅锗合金具有高于所述衬底表面所规定平面的顶面。
17.一种晶体管，包括：
具有沟道区的硅衬底，该沟道区包含第一掺杂剂杂质而具有第一电导型；
所述沟道区上的栅介质层；
所述栅介质层上的导电栅电极；
所述沟道区两侧的源区和漏区，所述源区和漏区由硅锗合金构成；
在所述硅锗合金上形成的镍硅硅化物层；以及
在所述镍硅硅化物层上形成的镍硅锗硅化物层。
18.如权利要求17所述的晶体管，其中，用硼在原位对所述硅锗合金进行掺杂。
19.如权利要求17所述的晶体管，其中，所述硅锗合金具有高于所述衬底表面所规定平面的顶面。
20.如权利要求17所述的晶体管，其中，所述硅锗合金具有5％与50％之间的锗成分。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103632977A (zh) * 2012-08-29 2014-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6949482B2 (en) 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
JP5114919B2 (ja) * 2006-10-26 2013-01-09 富士通セミコンダクター株式会社 半導体装置とその製造方法
US8124473B2 (en) 2007-04-12 2012-02-28 Advanced Micro Devices, Inc. Strain enhanced semiconductor devices and methods for their fabrication
US20100006961A1 (en) * 2008-07-09 2010-01-14 Analog Devices, Inc. Recessed Germanium (Ge) Diode
KR101561059B1 (ko) * 2008-11-20 2015-10-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US9484432B2 (en) 2010-12-21 2016-11-01 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
US8901537B2 (en) 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
FR2989517B1 (fr) * 2012-04-12 2015-01-16 Commissariat Energie Atomique Reprise de contact sur substrat semi-conducteur heterogene
FR3002688A1 (fr) * 2013-02-27 2014-08-29 Commissariat Energie Atomique Procede de fabrication d'un dispositif microelectronique

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
JP3876401B2 (ja) * 1999-08-09 2007-01-31 富士通株式会社 半導体装置の製造方法
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
JP3948290B2 (ja) * 2002-01-25 2007-07-25 ソニー株式会社 半導体装置の製造方法
US6812086B2 (en) * 2002-07-16 2004-11-02 Intel Corporation Method of making a semiconductor transistor
US6787864B2 (en) * 2002-09-30 2004-09-07 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
JP4509026B2 (ja) * 2003-02-07 2010-07-21 日本電気株式会社 ニッケルシリサイド膜の形成方法、半導体装置の製造方法およびニッケルシリサイド膜のエッチング方法
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7057216B2 (en) * 2003-10-31 2006-06-06 International Business Machines Corporation High mobility heterojunction complementary field effect transistors and methods thereof
US6872610B1 (en) * 2003-11-18 2005-03-29 Texas Instruments Incorporated Method for preventing polysilicon mushrooming during selective epitaxial processing
US6949482B2 (en) * 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
US20050253205A1 (en) * 2004-05-17 2005-11-17 Fujitsu Limited Semiconductor device and method for fabricating the same
JP4375619B2 (ja) * 2004-05-26 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2005353831A (ja) * 2004-06-10 2005-12-22 Toshiba Corp 半導体装置
US7072778B2 (en) * 2004-06-17 2006-07-04 Stmicroelectronics, Inc. Method and system for determining a rotor position in a wound field DC motor
JP4837902B2 (ja) * 2004-06-24 2011-12-14 富士通セミコンダクター株式会社 半導体装置
JP2006351581A (ja) * 2005-06-13 2006-12-28 Fujitsu Ltd 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103632977A (zh) * 2012-08-29 2014-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法
CN103632977B (zh) * 2012-08-29 2016-02-17 中芯国际集成电路制造(上海)有限公司 半导体结构及形成方法

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