CN103632977A - 半导体结构及形成方法 - Google Patents

半导体结构及形成方法 Download PDF

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CN103632977A
CN103632977A CN201210312974.4A CN201210312974A CN103632977A CN 103632977 A CN103632977 A CN 103632977A CN 201210312974 A CN201210312974 A CN 201210312974A CN 103632977 A CN103632977 A CN 103632977A
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silicon layer
germanium
germanium silicon
isolation structure
fleet plough
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CN103632977B (zh
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邓浩
张彬
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

一种半导体结构及形成方法,所述半导体结构包括:半导体衬底,位于半导体衬底内的浅沟槽隔离结构,位于浅沟槽隔离结构所包围的半导体衬底表面的栅极结构,位于所述若干栅极结构两侧的半导体衬底内的第一锗硅层和第二锗硅层,所述第一锗硅层靠近浅沟槽隔离结构,所述第二锗硅层远离浅沟槽隔离结构,第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。所述半导体结构中靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当,使得被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致。

Description

半导体结构及形成方法
技术领域
本发明涉及半导体制造技术,特别涉及一种具有浅沟槽隔离结构、MOS晶体管的半导体结构及形成方法。
背景技术
在半导体制造领域,随着半导体器件集成化和小型化发展,用于电学隔离相邻半导体器件的浅沟槽隔离结构(Shallow Trench Isolation,STI)的大小也随之减小。但是利用浅沟槽隔离结构进行隔离时,由于浅沟槽隔离结构的材料为二氧化硅,所述浅沟槽隔离结构的材料与半导体衬底的材料不同,所述浅沟槽隔离结构会不可避免地对浅沟槽隔离结构周围的半导体衬底产生应力作用,影响所述MOS晶体管的电学性能。
请参考图1,为现有的MOS晶体管和浅沟槽隔离结构的剖面结构示意图,具体包括:半导体衬底10,位于半导体衬底10内的有源区11;位于所述有源区11表面的栅极结构12,位于所述栅极结构12两侧的源区13和漏区14,所述源区13、漏区14、栅极结构12和位于所述栅极结构12下方有源区的沟道区15构成MOS晶体管,位于所述半导体衬底10内且围绕所述MOS晶体管设置的浅沟槽隔离结构18,所述浅沟槽隔离结构18将相邻的MOS晶体管电学隔离。由于形成所述浅沟槽隔离结构18的工艺为高温的化学气相沉积工艺,将二氧化硅材料形成于浅沟槽内时温度很高,当后续降为室温时,所述二氧化硅材料和半导体衬底的硅材料都会发生收缩。由于硅和二氧化硅的热膨胀系数不同,硅的热膨胀系数约为2.5×10-6/K,而二氧化硅的热膨胀系数约为0.5×10-6/K,降温时二氧化硅收缩的幅度小于硅收缩的幅度,使得材料为二氧化硅的浅沟槽隔离结构18会对周围的半导体衬底产生拉伸应力。且随着器件尺寸的进一步缩小,浅沟槽隔离结构的深宽比变大,为了使二氧化硅能完全填充满浅沟槽,利用高深宽比工艺形成浅沟槽隔离结构变得越来越普遍,但利用高深宽比工艺形成浅沟槽隔离结构会进一步地对周围的半导体衬底产生拉伸应力。
目前,减小浅沟槽隔离结构的拉伸应力可以采用改变浅沟槽隔离结构的位置或优化形成浅沟槽隔离结构的工艺,但是所述方法往往需要额外的步骤,使得器件生产过程变得复杂,同时增加了成本。
发明内容
本发明解决的问题是提供一种半导体结构及形成方法,使得被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致。
为解决上述问题,本发明技术方案提供了一种半导体结构的形成方法,包括:提供半导体衬底,在所述半导体衬底内形成浅沟槽隔离结构;在所述浅沟槽隔离结构包围的半导体衬底的表面形成若干平行排列的栅极结构;在靠近浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底内形成第一沟槽,在所述第一沟槽内形成第一锗硅层;在其余远离浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底内形成第二沟槽,在所述第二沟槽内形成第二锗硅层,使得每一个栅极结构两侧的半导体衬底内都形成有第一锗硅层或第二锗硅层,所述第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。
可选的,所述第一锗硅层中锗的摩尔百分比含量比第二锗硅层中锗的摩尔百分比含量大5%~10%。
可选的,所述第一锗硅层中锗的摩尔百分比含量范围为30%~45%,所述第二锗硅层中锗的摩尔百分比含量范围为20%~35%。
可选的,形成所述第一锗硅层的具体工艺包括:在所述半导体衬底表面、浅沟槽隔离结构表面、栅极结构侧壁和表面形成第一硬掩膜层,在所述第一硬掩膜层内形成第一开口,所述第一开口暴露出靠近浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底;以所述具有第一开口的第一硬掩膜层为掩膜,对暴露出的半导体衬底进行刻蚀,形成第一沟槽;利用选择性外延工艺在所述第一沟槽内填充满锗硅材料,形成第一锗硅层,所述第一锗硅层内掺杂有P型杂质离子,构成MOS晶体管的源区或漏区。
可选的,形成所述第二锗硅层的具体工艺包括:在所述半导体衬底表面、浅沟槽隔离结构表面、栅极结构侧壁和表面形成第二硬掩膜层,在所述第二硬掩膜层内形成第二开口,所述第二开口暴露出远离浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底;以所述具有第二开口的第二硬掩膜层为掩膜,对暴露出的半导体衬底进行刻蚀,形成第二沟槽;利用选择性外延工艺在所述第二沟槽内填充满锗硅材料,形成第二锗硅层,所述第二锗硅层内掺杂有P型杂质离子,构成MOS晶体管的源区或漏区。
可选的,刻蚀形成所述第一沟槽和第二沟槽的工艺为干法刻蚀、湿法刻蚀的混合工艺,或者为干法刻蚀工艺。
可选的,刻蚀形成所述第一沟槽或第二沟槽的工艺具体为:先采用干法刻蚀工艺在半导体衬底内形成剖面形状为矩形的沟槽,再利用湿法刻蚀工艺对所述剖面形状为矩形的沟槽进行刻蚀,形成侧壁形状为“Σ”形状的第一沟槽或第二沟槽。
可选的,所述第一硬掩膜层、第二硬掩膜层的材料为氧化硅、氮化硅、氮氧化硅其中的一种或几种。
可选的,当所述第一硬掩膜层、第二硬掩膜层的材料为氧化硅,利用稀释的氢氟酸去除所述第一硬掩膜层、第二硬掩膜层。
可选的,形成所述浅沟槽隔离结构的具体工艺为:利用干法刻蚀工艺对所述半导体衬底进行刻蚀形成浅沟槽,利用高深宽比工艺在所述浅沟槽内填充满介质材料,形成浅沟槽隔离结构。
可选的,当靠近浅沟槽隔离结构一边的第一锗硅层的数量大于等于二时,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量越高。
可选的,分别形成所述具有不同锗的摩尔百分比含量的第一锗硅层。
可选的,先形成所述第一锗硅层,再形成所述第二锗硅层。
可选的,先形成所述第二锗硅层,再形成所述第一锗硅层。
本发明技术方案还提供了一种半导体结构,包括:半导体衬底,位于半导体衬底内的浅沟槽隔离结构,位于所述浅沟槽隔离结构所包围的半导体衬底表面的若干平行排列的栅极结构,位于所述若干栅极结构两侧的半导体衬底内的第一沟槽和第二沟槽,其中,所述第一沟槽靠近浅沟槽隔离结构,所述第二沟槽远离浅沟槽隔离结构,所述第一沟槽内具有第一锗硅层,所述第二沟槽内具有第二锗硅层,第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。
可选的,所述第一锗硅层中锗的摩尔百分比含量比第二锗硅层中锗的摩尔百分比含量大5%~10%。
可选的,所述第一锗硅层中锗的摩尔百分比含量范围为30%~45%,所述第二锗硅层中锗的摩尔百分比含量范围为20%~35%。
可选的,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量越高。
可选的,所述浅沟槽隔离结构对半导体衬底和PMOS晶体管的沟道区产生拉伸应力。
与现有技术相比,本发明具有以下优点:
所述半导体结构包括浅沟槽隔离结构和所述浅沟槽隔离结构包围的半导体衬底表面的栅极结构,所述栅极结构的两侧形成有第一锗硅层或第二锗硅层,所述第一锗硅层靠近所述浅沟槽隔离结构,所述第二锗硅层远离所述浅沟槽隔离结构,且所述第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量。由于靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量大于远离浅沟槽隔离结构的第二锗硅层中锗的摩尔百分比含量,使得靠近浅沟槽隔离结构的所述锗硅层产生的压缩应力大于远离浅沟槽隔离结构的所述锗硅层产生的压缩应力,而所述浅沟槽隔离结构产生的拉伸应力从靠近浅沟槽隔离结构到远离浅沟槽隔离结构逐渐变小,使得整体上靠近浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用与远离浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用相当,被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致。
进一步的,当靠近浅沟槽隔离结构一侧的第一锗硅层的数量大于等于二时,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较高,越远离浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较低,但仍大于第二锗硅层中锗的摩尔百分比含量,从而可以在不同的沟道区中产生渐变的压缩应力,所述渐变的压缩应力与浅沟槽隔离结构产生的渐变的拉伸应力相抵消,从而可以更精确的进行控制,使得整体上靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当。
附图说明
图1、图2是现有技术被浅沟槽隔离结构包围的MOS晶体管的结构示意图;
图3是图2中被浅沟槽隔离结构所包围的MOS晶体管沟道区和源/漏区的水平应力分布图;
图4~图10为本发明实施例的半导体结构形成过程的结构示意图。
具体实施方式
在背景技术可知,现有技术形成的浅沟槽隔离结构会对周围的半导体衬底产生拉伸应力。当一个浅沟槽隔离结构包围若干MOS晶体管时,靠近浅沟槽隔离结构的半导体衬底所受到的应力作用大于远离浅沟槽隔离结构的半导体衬底,对应使得靠近浅沟槽隔离结构的MOS晶体管的沟道区所受到的应力作用大于远离浅沟槽隔离结构的MOS晶体管的沟道区所受到的应力作用,即使所述MOS晶体管的形状、大小、形成工艺相同,不同位置的MOS晶体管的载流子迁移率也不相同,使得不同位置的MOS晶体管的电学性能不一致,可能会影响最终形成的集成电路的性能。特别是当所述浅沟槽隔离结构所包围的MOS晶体管都为PMOS晶体管时,由于PMOS晶体管的沟道区的载流子为空穴,当所述沟道区中具有压缩应力时,所述PMOS晶体管的载流子迁移率越大,当所述沟道区中具有拉伸应力时,所述PMOS晶体管的载流子迁移率越小。所述浅沟槽隔离结构对周围的半导体衬底产生的拉伸应力,会使得靠近浅沟槽隔离结构的PMOS晶体管的载流子迁移率小于远离浅沟槽隔离结构的PMOS晶体管的载流子迁移率,使得靠近浅沟槽隔离结构的PMOS晶体管的电学性能变差。请参考图2和图3,图2表示浅沟槽隔离结构28包围着7个PMOS晶体管,所述PMOS晶体管的源区/漏区24的材料为锗硅,使得位于栅极结构22下方的沟道区25具有压缩应力,图3为图2中被浅沟槽隔离结构所包围的PMOS晶体管沟道区和源/漏区的水平应力分布图。图3中可以清晰的看出,在靠近浅沟槽隔离结构的PMOS晶体管沟道区的压缩应力比远离浅沟槽隔离结构的PMOS晶体管沟道区的压缩应力小24%~35%。
为此,本发明提出了一种半导体结构及形成方法,所述半导体结构包括浅沟槽隔离结构和所述浅沟槽隔离结构包围的半导体衬底表面的栅极结构,所述栅极结构的两侧形成有第一锗硅层或第二锗硅层,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。所述第一锗硅层靠近所述浅沟槽隔离结构,所述第二锗硅层远离所述浅沟槽隔离结构,且所述第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量。由于靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量大于远离浅沟槽隔离结构的第二锗硅层中锗的摩尔百分比含量,使得靠近浅沟槽隔离结构的所述锗硅层产生的压缩应力大于远离浅沟槽隔离结构的所述锗硅层产生的压缩应力,而所述浅沟槽隔离结构产生的拉伸应力从靠近浅沟槽隔离结构到远离浅沟槽隔离结构逐渐变小,使得整体上靠近浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用与远离浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用相当,被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致,靠近浅沟槽隔离结构的PMOS晶体管的电学性能没有变差。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以多种不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广。因此本发明不受下面公开的具体实施的限制。
请参考图4至图10,为本发明实施例的半导体结构的形成过程的结构示意图。
请参考图4,提供半导体衬底100,在所述半导体衬底100内形成浅沟槽隔离结构110。
所述半导体衬底100为硅衬底、锗衬底、硅锗衬底、绝缘体上硅衬底(SOI)、绝缘体上锗衬底其中的一种。在本实施例中,所述半导体衬底100为掺杂有N型杂质离子的硅衬底。
形成所述浅沟槽隔离结构110的工艺包括:在所述半导体衬底100表面形成垫氧化层(未图示),在所述垫氧化层表面形成氮化硅层(未图示),在所述氮化硅层表面形成第一光刻胶层(未图示),对所述第一光刻胶层进行曝光显影,形成第一光刻胶图形;对所述第一光刻胶图形暴露出的氮化硅层、垫氧化层和半导体衬底进行刻蚀,形成浅沟槽;去除所述第一光刻胶图形后,利用高深宽比(HARP)工艺在所述浅沟槽内和氮化硅层表面形成氧化硅材料,且所述氧化硅材料填充满所述浅沟槽,并以所述氮化硅层为抛光阻挡层,对所述氧化硅材料进行化学机械抛光,直至暴露出所述氮化硅层,在浅沟槽内形成浅沟槽隔离结构。形成所述浅沟槽隔离结构后,去除所述氮化硅层,还可以对所述浅沟槽隔离结构进行退火处理。
由于随着器件尺寸的进一步缩小,浅沟槽隔离结构的宽度也在进一步缩小,但为了维持浅沟槽隔离结构的隔离效果,所述浅沟槽隔离结构必须具有一定深度,使得浅沟槽的深宽比越来越大,甚至达到10:1,为此,采用传统的化学气相沉积工艺无法有效地填充满浅沟槽。本发明实施例采用高深宽比(HARP)工艺填充浅沟槽,所述高深宽比(HARP)工艺具体为在540℃温度下,采用亚常压化学气相沉积(SACVD)工艺,利用O3/TEOS作为反应前驱物在浅沟槽内和氮化硅层表面形成氧化硅材料,利用所述高深宽比(HARP)工艺可以填充深宽比大于8:1的沟槽。但是利用所述高深宽比工艺形成的浅沟槽隔离结构会对周围的半导体衬底产生拉伸应力,会进一步增加靠近浅沟槽隔离结构的半导体衬底受到的拉伸应力。
在其他实施例中,还可以在所述浅沟槽隔离结构包围的半导体衬底内形成有源区,所述有源区的掺杂类型与对应待形成的MOS晶体管的类型相关。在本实施例中,当待形成的MOS晶体管为PMOS晶体管时,所述有源区的掺杂离子为N型掺杂离子,且所述浅沟槽隔离结构电学隔离相邻的有源区。
请参考图5和图6,在所述浅沟槽隔离结构110包围的半导体衬底100的表面形成若干平行排列的栅极结构120。其中,图5为本发明实施例的俯视视角的结构示意图,图6为图5中沿AA′方向的剖面结构示意图。
所述栅极结构120包括位于所述半导体衬底100表面的栅介质层121、位于所述栅介质层121表面的栅电极122、位于所述栅氧化层121和栅电极122侧壁表面的侧墙(未图示)。所述栅介质层121的材料为氧化硅、氮氧化硅或高K介质材料,所述栅电极122的材料为多晶硅或金属,所述侧墙的材料可以是氧化硅、氮化硅或是二者的叠层结构。当所述栅极结构120为高K栅介质层和金属栅电极的堆叠结构时,形成所述栅极结构120的工艺包括前栅工艺或后栅工艺。由于所述栅极结构的形成方法为本领域技术人员的公知技术,在此不再赘述。
在本实施例中,所述浅沟槽隔离结构110围成一个长方形,且所述长方形的两个边111、113在X方向上、两个边112、114在Y方向上,所述若干平行排列的栅极结构120也沿X方向排列。由于所述浅沟槽隔离结构产生的应力方向垂直于所述浅沟槽隔离结构,所述浅沟槽隔离结构的两个边111、113产生的拉伸应力方向与栅极结构120垂直,会影响栅极结构下方的沟道区中载流子的迁移速率。而所述浅沟槽隔离结构的两个边112、114产生的拉伸应力方向与栅极结构120平行,不会影响栅极结构下方的沟道区中载流子的迁移速率。因此,在本发明中,所记载的靠近浅沟槽隔离结构110的栅极结构、锗硅层、半导体衬底即为靠近所述浅沟槽隔离结构的两个边111、113的栅极结构、锗硅层、半导体衬底。
请参考图7,在最靠近浅沟槽隔离结构110的栅极结构的一侧的半导体衬底100内形成第一沟槽130,即在所述最靠近浅沟槽隔离结构两个边111和113的栅极结构的一侧的半导体衬底100内形成两个第一沟槽130。
形成所述第一沟槽130的具体工艺包括:在所述半导体衬底100表面、浅沟槽隔离结构110表面、栅极结构120侧壁和表面形成第一硬掩膜层(未图示),所述第一硬掩膜层的材料为氧化硅、氮化硅、氮氧化硅其中的一种或几种;在所述第一硬掩膜层表面形成图形化的第二光刻胶层(未图示),利用所述图形化的第二光刻胶层在所述第一硬掩膜层内形成第一开口,所述第一开口暴露出最靠近浅沟槽隔离结构110的栅极结构120的一侧的半导体衬底100;以所述具有第一开口的第一硬掩膜层为掩膜,对暴露出的半导体衬底100进行刻蚀,形成第一沟槽130。所述第一沟槽130用于填充锗硅材料形成第一锗硅层,所述第一锗硅层作为后续形成的MOS晶体管的源区或漏区。
在本发明实施例中,形成第一沟槽130的刻蚀工艺为干法刻蚀、湿法刻蚀的混合工艺,先采用干法刻蚀工艺在半导体衬底100内形成剖面形状为矩形的沟槽,再利用四甲基氢氧化铵(TMAH)溶液工艺对所述剖面形状为矩形的沟槽进行湿法刻蚀,形成侧壁形状为“Σ”形状的第一沟槽130。利用所述侧壁形状为“Σ”形状的第一沟槽130形成的第一锗硅层对沟道区具有较大的拉伸应力。在其他实施例中,形成第一沟槽的刻蚀工艺也可以只包括干法刻蚀工艺。
请参考图8,在所述第一沟槽130(请参考图7)内形成第一锗硅层135。
形成所述第一锗硅层135的工艺为选择性外延工艺。在本实施例中,形成所述第一锗硅层135的具体工艺包括:将硅源(例如硅烷、乙硅烷、丙硅烷、有机硅烷等)、锗源(例如锗烷、乙锗烷、丙锗烷、有机锗烷等)、刻蚀气体(例如氯化氢、氟化氢、氯气、四氯化硅等)、载气(氢气、氮气、氦气、氩气等)通入到反应腔中,在压强范围为0.1托~200托,温度范围为700摄氏度~900摄氏度的反应腔内,所述混合气体在所述第一沟槽130内形成锗硅材料,且所述刻蚀气体会刻蚀去除第一硬掩膜层表面的锗硅材料,使得最终形成的锗硅材料只能选择性外延形成于第一沟槽130内,在所述第一沟槽130内形成第一锗硅层135。
通过调整所述硅源和锗源的比例,可以调节最终形成第一锗硅层135中锗的摩尔百分比含量。在本实施例中,所述第一锗硅层135中锗的摩尔百分比含量范围为30%~45%。在其他实施例中,所述第一锗硅层中锗的摩尔百分比含量还可以为其他值。
形成所述第一锗硅层135后,去除所述第一硬掩膜层。去除所述第一硬掩膜层的工艺为湿法刻蚀工艺。在本实施例中,所述第一硬掩膜层的材料为氧化硅,利用稀释的氢氟酸去除所述第一硬掩膜层,所述稀释的氢氟酸中水和氢氟酸的体积比为100:1~300:1。
在其他实施例中,也可以不去除所述第一硬掩膜层,后续在所述第一硬掩膜层、第一锗硅层表面形成第二硬掩膜层,利用所述第二硬掩膜层形成第二沟槽。
请参考图9,在其余远离浅沟槽隔离结构110的栅极结构120的两侧的半导体衬底100内形成第二沟槽140。
形成所述第二沟槽140的具体工艺包括:在所述半导体衬底100表面、浅沟槽隔离结构110表面、栅极结构120侧壁和表面、第一锗硅层135表面形成第二硬掩膜层(未图示),所述第二硬掩膜层的材料为氧化硅、氮化硅、氮氧化硅其中的一种或几种;在所述第二硬掩膜层表面形成图形化的第三光刻胶层(未图示),利用所述图形化的第三光刻胶层在所述第二硬掩膜层内形成第二开口,所述第二开口暴露出其余远离浅沟槽隔离结构110的栅极结构120的两侧的半导体衬底100;以所述具有第二开口的第二硬掩膜层为掩膜,对暴露出的半导体衬底100进行刻蚀,形成第二沟槽140。所述第二沟槽140用于填充锗硅材料形成第二锗硅层,所述第二锗硅层作为后续形成的MOS晶体管的源区或漏区。
在本发明实施例中,形成第二沟槽140的刻蚀工艺为干法刻蚀、湿法刻蚀的混合工艺,先采用干法刻蚀工艺在半导体衬底100内形成剖面形状为矩形的沟槽,再利用四甲基氢氧化铵(TMAH)溶液工艺对所述剖面形状为矩形的沟槽进行湿法刻蚀,形成侧壁形状为“Σ”形状的第二沟槽140。利用所述侧壁形状为“Σ”形状的第二沟槽140形成的第二锗硅层对沟道区具有较大的拉伸应力。在其他实施例中,形成第二沟槽的刻蚀工艺为也可以只包括干法刻蚀工艺。
请参考图10,在所述第二沟槽140(请参考图9)内形成第二锗硅层145,每一个栅极结构120两侧的半导体衬底100内都形成有第一锗硅层135或第二锗硅层145。
形成所述第二锗硅层145的工艺为选择性外延工艺。在本实施例中,形成所述第二锗硅层145的具体工艺与形成所述第一锗硅层135的具体工艺相似,包括:将硅源(例如硅烷、乙硅烷、丙硅烷、有机硅烷等)、锗源(例如锗烷、乙锗烷、丙锗烷、有机锗烷等)、刻蚀气体(例如氯化氢、氟化氢、氯气、四氯化硅等)、载气(氢气、氮气、氦气、氩气等)通入到反应腔中,在压强范围为0.1托~200托,温度范围为700摄氏度~900摄氏度的反应腔内,所述混合气体在所述第二沟槽140内形成锗硅材料,且所述刻蚀气体会刻蚀去除第二硬掩膜层表面的锗硅材料,使得最终形成的锗硅材料只能选择性地外延形成于第二沟槽140内,在所述第二沟槽140内形成第二锗硅层145,且所述第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量。
在本实施例中,所述第二锗硅层145中锗的摩尔百分比含量范围为20%~35%,所述第一锗硅层135中锗的摩尔百分比含量比第二锗硅层145中锗的摩尔百分比含量大5%~10%。在其他实施例中,所述第一锗硅层中锗的摩尔百分比含量与第二锗硅层中锗的摩尔百分比含量之间的差值也可以为其他值。由于靠近浅沟槽隔离结构110的第一锗硅层135中锗的摩尔百分比含量大于远离浅沟槽隔离结构110的第二锗硅层145中锗的摩尔百分比含量,使得靠近浅沟槽隔离结构的第一锗硅层135产生的压缩应力大于远离浅沟槽隔离结构的第二锗硅层145产生的压缩应力,而所述浅沟槽隔离结构110产生的拉伸应力从靠近浅沟槽隔离结构110到远离浅沟槽隔离结构110逐渐变小,使得整体上靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当,最终形成的被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致,靠近浅沟槽隔离结构的PMOS晶体管的电学性能没有变差。
在本发明实施例中,仅在最靠近浅沟槽隔离结构110的一个栅极结构120的一侧的半导体衬底100内形成一个第一锗硅层135,在其余远离浅沟槽隔离结构110的栅极结构120的两侧的半导体衬底100内形成第二锗硅层145。
在其他实施例中,还可以在最靠近浅沟槽隔离结构的一个或两个栅极结构的一侧或两侧的半导体衬底内形成第一锗硅层。即在最靠近浅沟槽隔离结构的一个栅极结构的两侧的半导体衬底内形成两个第一锗硅层;或在最靠近浅沟槽隔离结构的栅极结构的两侧和次靠近的浅沟槽隔离结构的栅极结构的一侧的半导体衬底内形成三个第一锗硅层;或在最靠近浅沟槽隔离结构的栅极结构的两侧和次靠近的浅沟槽隔离结构的栅极结构的两侧的半导体衬底内形成四个第一锗硅层,在其余远离浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底内形成第二锗硅层。其中,所述第一锗硅层的数量为靠近浅沟槽隔离结构一边的第一锗硅层的数量。由于浅沟槽隔离结构会产生拉伸应力,且所述拉伸应力从靠近浅沟槽隔离结构到远离浅沟槽隔离结构逐渐变小,因此只需要将靠近浅沟槽隔离结构的一个或几个锗硅层中锗的摩尔百分比含量大于其余远离浅沟槽隔离结构的锗硅层中锗的摩尔百分比含量,就能使得整体上靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当。
当靠近浅沟槽隔离结构一边的第一锗硅层的数量大于等于二时,所述第一锗硅层中锗的摩尔百分比含量可以相同,也可以不同。当所述第一锗硅层中锗的摩尔百分比含量不同时,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较高,越远离浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较低,但仍大于第二锗硅层中锗的摩尔百分比含量,从而可以在不同的沟道区中产生渐变的压缩应力,所述渐变的压缩应力与浅沟槽隔离结构产生的渐变的拉伸应力相抵消,从而可以更精确的进行控制,使得整体上靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当。
当所述第一锗硅层中锗的摩尔百分比含量不同时,所述锗的摩尔百分比含量不同的第一锗硅层分别形成,每次形成一种锗的摩尔百分比含量的第一锗硅层,具体的形成工艺参考上述第一锗硅层和第二锗硅层的形成工艺,在此不作详述。
在其他实施例中,还可以先形成所述第二锗硅层,再形成所述第一锗硅层。
形成所述第二锗硅层145后,去除所述第二硬掩膜层。去除所述第一硬掩膜层1的工艺为湿法刻蚀工艺。在本实施例中,所述第二硬掩膜层的材料为氧化硅,利用稀释的氢氟酸去除所述第二硬掩膜层。
在形成所述第一锗硅层和第二锗硅层后,利用离子注入工艺在所述第一锗硅层和第二锗硅层内形成P型杂质离子,例如:硼、镓、铟等,所述第一锗硅层和第二锗硅层形成源区或漏区,相邻的PMOS晶体管共享源区或漏区,使得所述栅极结构120和位于所述栅极结构120两侧的第一锗硅层135或第二锗硅层145构成PMOS晶体管,
在其他实施例中,还可以在选择性外延形成所述第一锗硅层和第二锗硅层中原位掺杂所述P型杂质离子,使得所述利用外延工艺形成的第一锗硅层和第二锗硅层成为PMOS晶体管的源区或漏区。
本发明实施例还提供了一种半导体结构,请参考图10,包括:半导体衬底100,位于半导体衬底100内的浅沟槽隔离结构110,位于所述浅沟槽隔离结构110所包围的半导体衬底100表面的若干平行排列的栅极结构120,位于所述若干栅极结构120两侧的半导体衬底内的第一沟槽130(请参考图7)和第二沟槽140(请参考图9),其中,所述第一沟槽130靠近浅沟槽隔离结构110,所述第二沟槽140远离浅沟槽隔离结构110。所述第一沟槽130内具有第一锗硅层135,所述第二沟槽140内具有第二锗硅层145,第一锗硅层135中锗的摩尔百分比含量大于第二锗硅层145中锗的摩尔百分比含量,所述栅极结构120和位于所述栅极结构120两侧的第一锗硅层135或第二锗硅层145构成PMOS晶体管。
在本实施例中,所述第一锗硅层135中锗的摩尔百分比含量范围为30%~45%,所述第二锗硅层145中锗的摩尔百分比含量范围为20%~35%,所述第一锗硅层135中锗的摩尔百分比含量比第二锗硅层145中锗的摩尔百分比含量大5%~10%。在其他实施例中,所述第一锗硅层中锗的摩尔百分比含量与第二锗硅层中锗的摩尔百分比含量之间的差值也可以为其他值。
由于所述靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量大于远离浅沟槽隔离结构的第二锗硅层中锗的摩尔百分比含量,使得靠近浅沟槽隔离结构的所述锗硅层产生的压缩应力大于远离浅沟槽隔离结构的所述锗硅层产生的压缩应力,而所述浅沟槽隔离结构产生的拉伸应力从靠近浅沟槽隔离结构到远离浅沟槽隔离结构逐渐变小,使得整体上靠近浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用与远离浅沟槽隔离结构的PMOS晶体管沟道区受到的应力作用相当,被浅沟槽隔离结构包围的PMOS晶体管的载流子迁移速率一致,靠近浅沟槽隔离结构的PMOS晶体管的电学性能没有变差。
进一步的,当靠近浅沟槽隔离结构一侧的第一锗硅层的数量大于等于二时,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较高,越远离浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量较低,但仍大于第二锗硅层中锗的摩尔百分比含量,从而可以在不同的沟道区中产生渐变的压缩应力,所述渐变的压缩应力与浅沟槽隔离结构产生的渐变的拉伸应力相抵消,从而可以更精确的进行控制,使得整体上靠近浅沟槽隔离结构的沟道区受到的应力作用与远离浅沟槽隔离结构的沟道区受到的应力作用相当。
本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。

Claims (21)

1.一种半导体结构的形成方法,其特征在于,包括:
提供半导体衬底,在所述半导体衬底内形成浅沟槽隔离结构;
在所述浅沟槽隔离结构包围的半导体衬底的表面形成若干平行排列的栅极结构;
在靠近浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底内形成第一沟槽,在所述第一沟槽内形成第一锗硅层;
在其余远离浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底内形成第二沟槽,在所述第二沟槽内形成第二锗硅层,使得每一个栅极结构两侧的半导体衬底内都形成有第一锗硅层或第二锗硅层,所述第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一锗硅层中锗的摩尔百分比含量比第二锗硅层中锗的摩尔百分比含量大5%~10%。
3.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第一锗硅层中锗的摩尔百分比含量范围为30%~45%,所述第二锗硅层中锗的摩尔百分比含量范围为20%~35%。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第一锗硅层的具体工艺包括:
在所述半导体衬底表面、浅沟槽隔离结构表面、栅极结构侧壁和表面形成第一硬掩膜层,在所述第一硬掩膜层内形成第一开口,所述第一开口暴露出靠近浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底;
以所述具有第一开口的第一硬掩膜层为掩膜,对暴露出的半导体衬底进行刻蚀,形成第一沟槽;
利用选择性外延工艺在所述第一沟槽内填充满锗硅材料,形成第一锗硅层,所述第一锗硅层内掺杂有P型杂质离子,构成MOS晶体管的源区或漏区。
5.如权利要求4所述的半导体结构的形成方法,其特征在于,形成所述第一锗硅层后,去除所述第一硬掩膜层。
6.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述第二锗硅层的具体工艺包括:
在所述半导体衬底表面、浅沟槽隔离结构表面、栅极结构侧壁和表面形成第二硬掩膜层,在所述第二硬掩膜层内形成第二开口,所述第二开口暴露出远离浅沟槽隔离结构的栅极结构的一侧或两侧的半导体衬底;
以所述具有第二开口的第二硬掩膜层为掩膜,对暴露出的半导体衬底进行刻蚀,形成第二沟槽;
利用选择性外延工艺在所述第二沟槽内填充满锗硅材料,形成第二锗硅层,所述第二锗硅层内掺杂有P型杂质离子,构成MOS晶体管的源区或漏区。
7.如权利要求6所述的半导体结构的形成方法,其特征在于,形成所述第二锗硅层后,去除所述第二硬掩膜层。
8.如权利要求4或6所述的半导体结构的形成方法,其特征在于,刻蚀形成所述第一沟槽和第二沟槽的工艺为干法刻蚀、湿法刻蚀的混合工艺,或者为干法刻蚀工艺。
9.如权利要求4或6所述的半导体结构的形成方法,其特征在于,刻蚀形成所述第一沟槽或第二沟槽的工艺具体为:先采用干法刻蚀工艺在半导体衬底内形成剖面形状为矩形的沟槽,再利用湿法刻蚀工艺对所述剖面形状为矩形的沟槽进行刻蚀,形成侧壁形状为“Σ”形状的第一沟槽或第二沟槽。
10.如权利要求4或6所述的半导体结构的形成方法,其特征在于,所述第一硬掩膜层、第二硬掩膜层的材料为氧化硅、氮化硅、氮氧化硅其中的一种或几种。
11.如权利要求10所述的半导体结构的形成方法,其特征在于,当所述第一硬掩膜层、第二硬掩膜层的材料为氧化硅,利用稀释的氢氟酸去除所述第一硬掩膜层、第二硬掩膜层。
12.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述浅沟槽隔离结构的具体工艺为:利用干法刻蚀工艺对所述半导体衬底进行刻蚀形成浅沟槽,利用高深宽比工艺在所述浅沟槽内填充满介质材料,形成浅沟槽隔离结构。
13.如权利要求1所述的半导体结构的形成方法,其特征在于,当靠近浅沟槽隔离结构一边的第一锗硅层的数量大于等于二时,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量越高。
14.如权利要求13所述的半导体结构的形成方法,其特征在于,分别形成所述具有不同锗的摩尔百分比含量的第一锗硅层。
15.如权利要求1所述的半导体结构的形成方法,其特征在于,先形成所述第一锗硅层,再形成所述第二锗硅层。
16.如权利要求1所述的半导体结构的形成方法,其特征在于,先形成所述第二锗硅层,再形成所述第一锗硅层。
17.一种半导体结构,其特征在于,包括:半导体衬底,位于半导体衬底内的浅沟槽隔离结构,位于所述浅沟槽隔离结构所包围的半导体衬底表面的若干平行排列的栅极结构,位于所述若干栅极结构两侧的半导体衬底内的第一沟槽和第二沟槽,其中,所述第一沟槽靠近浅沟槽隔离结构,所述第二沟槽远离浅沟槽隔离结构,所述第一沟槽内具有第一锗硅层,所述第二沟槽内具有第二锗硅层,第一锗硅层中锗的摩尔百分比含量大于第二锗硅层中锗的摩尔百分比含量,所述栅极结构和位于所述栅极结构两侧的第一锗硅层或第二锗硅层构成PMOS晶体管。
18.如权利要求17所述的半导体结构,其特征在于,所述第一锗硅层中锗的摩尔百分比含量比第二锗硅层中锗的摩尔百分比含量大5%~10%。
19.如权利要求17所述的半导体结构,其特征在于,所述第一锗硅层中锗的摩尔百分比含量范围为30%~45%,所述第二锗硅层中锗的摩尔百分比含量范围为20%~35%。
20.如权利要求17所述的半导体结构,其特征在于,所述第一锗硅层中锗的摩尔百分比含量不同,越靠近浅沟槽隔离结构的第一锗硅层中锗的摩尔百分比含量越高。
21.如权利要求17所述的半导体结构,其特征在于,所述浅沟槽隔离结构对半导体衬底以及PMOS晶体管的沟道区产生拉伸应力。
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