WO2023102951A1 - 一种垂直mosfet器件及其制造方法、应用 - Google Patents

一种垂直mosfet器件及其制造方法、应用 Download PDF

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WO2023102951A1
WO2023102951A1 PCT/CN2021/137385 CN2021137385W WO2023102951A1 WO 2023102951 A1 WO2023102951 A1 WO 2023102951A1 CN 2021137385 W CN2021137385 W CN 2021137385W WO 2023102951 A1 WO2023102951 A1 WO 2023102951A1
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layer
silicon
gate
silicon germanium
groove
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French (fr)
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陈卓
朱慧珑
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北京超弦存储器研究院
中国科学院微电子研究所
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Priority to US17/770,871 priority Critical patent/US20240145591A1/en
Publication of WO2023102951A1 publication Critical patent/WO2023102951A1/zh

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Definitions

  • the invention relates to the field of transistors, in particular to a vertical MOSFET device and its manufacturing method and application.
  • the performance of vertical transistor devices still has a large gap. This is because vertical transistors have many challenges in key process modules and process integration.
  • the key process modules of vertical transistors include etching and selective etching to form nanowire and nanosheet channels and inner walls. For this reason, the present invention is proposed.
  • the main purpose of the present invention is to provide a method for manufacturing a vertical MOSFET device, which can well control the size of the channel, the size of the inner wall of the extension region, the size of the gate, etc., and is applicable to nanosheet or nanowire structures.
  • Another object of the present invention is to provide a vertical MOSFET device, which adds a size-controllable inner wall of the expansion region, and has better electrical performance than the existing vertical transistor device, such as low leakage, small parasitic capacitance, etc. .
  • the present invention provides the following technical solutions.
  • a first aspect of the present invention provides a method of manufacturing a vertical MOSFET device, comprising the following steps:
  • a first silicon layer, a first silicon germanium layer, a second silicon germanium layer, a third silicon germanium layer, and a second silicon layer are formed vertically stacked from bottom to top on the substrate; wherein, the first silicon germanium layer and the molar content of germanium in the third silicon germanium layer are greater than the content of germanium in the second silicon germanium layer;
  • a second aspect of the present invention provides a vertical MOSFET device, which includes a substrate, and a source/drain, a first extension region, a channel, a second extension region, and a source stacked from bottom to top on the substrate.
  • a vertical MOSFET device which includes a substrate, and a source/drain, a first extension region, a channel, a second extension region, and a source stacked from bottom to top on the substrate.
  • both sides of the channel are gates, and the gate is isolated from the channel by a gate dielectric
  • both sides of the first extension region are first inner wall
  • the second extension Both sides of the region are second inner walls, and the gate is located between the first inner wall and the second inner wall;
  • first extension region, the channel and the second extension region are all made of silicon germanium material, and the molar content of germanium in the first extension region and the second extension region is greater than the content of germanium in the channel;
  • the source/drain is doped silicon.
  • the third aspect of the present invention provides the above-mentioned vertical MOSFET device, or the application of the vertical MOSFET device prepared by the above-mentioned manufacturing method in electronic devices.
  • an inner wall is added between the gate and the source-drain, and by designing a specific process sequence (for example, the design has different germanium components and different etching selectivities)
  • the silicon germanium epitaxial stack, replacement mask, and inner wall protection layer structure realize the integrated development of the vertical transistor inner wall process) realize the controllable size of the inner wall, and simultaneously realize the gate size and channel size Controllable, thereby reducing the leakage problem of the device, reducing the parasitic capacitance, and reducing the bad phenomenon in the processing of the device;
  • the vertical MOSFET device manufactured by the method of the invention can be used in various memory devices such as SRAM, DRAM, and Flash.
  • Figures 1 to 25 are structural diagrams obtained in each step of the manufacturing method of the vertical MOSFET device provided by the present invention.
  • Fig. 26 is a schematic cross-sectional structure diagram of a vertical MOSFET device provided by the present invention.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • the present invention studies the above problems, and proposes a method for manufacturing a vertical MOSFET device. In this method, an inner wall is added between the gate and the source and drain, and the size of the inner wall is controlled by designing a specific process sequence.
  • the manufacturing method provided by the invention includes the following steps.
  • First step S1 forming the first silicon layer 2, the first silicon germanium layer 3, the second silicon germanium layer 4, the third silicon germanium layer 5, and the second silicon layer 6 stacked vertically from bottom to top on the substrate 1, to obtain The structure shown in Figure 1.
  • the molar content of germanium in the first silicon germanium layer 3 and the third silicon germanium layer 5 is greater than the content of germanium in the second silicon germanium layer 4, and the three silicon germanium layers can be realized by differentiating the germanium content. selective etching.
  • the first silicon germanium layer 3 and the third silicon germanium layer 5 need to be etched simultaneously in the subsequent process, it is preferable that the first silicon germanium layer 3 and the third silicon germanium layer 5 use the same germanium content. Material.
  • the molar content of germanium in the first silicon germanium layer 3 and the third silicon germanium layer 5 is preferably more than 15% (15%, 20%, 25%, 30%, 35%, 40%, 45%, 50% %, 55%, etc., wherein more preferably 15% to 30%), matched with it, the molar content of germanium in the second silicon germanium layer 4 is preferably below 15% (such as 1%, 3%, 5%, 7% %, 10%, 13%, 15%, etc., among which, 5% to 15% is more preferable).
  • the above-mentioned substrate 1 may be any substrate known to those skilled in the art for carrying components of semiconductor integrated circuits, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, Germanium, silicon germanium, gallium arsenide, or germanium on insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide, etc.
  • SOI silicon-on-insulator
  • bulk silicon silicon carbide
  • the corresponding top semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide, etc.
  • the semiconductor layer on the substrate determines the doping type according to the device type to form a P well (for nMOSFET) or an n well (for pMOSFET), as shown in Figure 1 with a dotted line frame doping region ( Figure 1 to The boundary line between the doped region 1a and the non-doped region is marked in the substrate of the cross-sectional view of 25).
  • the first silicon layer 2 and the second silicon layer 6 can be used as the source/drain of the transistor through subsequent etching and doping, and can also be in-situ doped when the first silicon layer 2 and the second silicon layer 6 are grown epitaxially.
  • impurity to form a highly doped n-type or p-type conductive layer (the doping concentration is 1 ⁇ 10 19 to 1 ⁇ 10 21 cm -3 ). Therefore, its thickness, doping concentration and doping type and other parameters are determined according to product design.
  • the first silicon germanium layer 3 and the second silicon germanium layer 5 are formed by epitaxial growth, the first silicon germanium layer 3 and the second silicon germanium layer 5 can be undoped, or can be doped in situ during epitaxial growth, doped
  • the impurity concentration is 1 ⁇ 10 18 ⁇ 1 ⁇ 10 20 cm -3 , the doping concentration of the first silicon germanium layer 3 and the second silicon germanium layer 5 should be lower than that of the first silicon layer 2 and the second silicon layer 6 concentration to suppress the hot carrier injection effect.
  • the second silicon germanium layer 4 will serve as a channel after subsequent etching, so its thickness is preferably greater than that of the first silicon germanium layer 3 and the third silicon germanium layer 5 .
  • the thicknesses of the first silicon germanium layer 3 and the third silicon germanium layer 5 are each independently 5-15 nm in thickness, and the thickness of the second silicon germanium layer 4 is 15-100 nm.
  • an appropriate formation process usually including but not limited to epitaxial growth methods such as reduced pressure chemical vapor deposition (RPCVD), metal organic compound chemical vapor deposition (MOCVD), etc. .
  • epitaxial growth methods such as reduced pressure chemical vapor deposition (RPCVD), metal organic compound chemical vapor deposition (MOCVD), etc. .
  • step S2 etch the first silicon layer 2, the first silicon germanium layer 3, the second silicon germanium layer 4, the third silicon germanium layer 5, and the second silicon layer 6 to form a nano-stack structure.
  • the second silicon layer 6 Since the second silicon layer 6 is to be used as the source/drain of the transistor, it needs to be fully protected during etching, and at the same time, the regularization of the pattern must be guaranteed, so it is necessary to etch with the help of a mask, that is, the second silicon layer 6 must be etched in advance. 6, deposit a mask, and then etch. For example, the following method is adopted.
  • Step S201 depositing a mask stack 7 on the second silicon layer 6, the mask stack 7 is preferably a hard mask (HM), such as TiN, SiN, SiO2, amorphous silicon, polysilicon, etc., preferably a multi-layer stack , so that it can adapt to the different selectivity of etching in different processes, and at the same time include an etch stop layer, etc., to play a better protective role, such as the common silicon nitride-silicon-silicon nitride or silicon oxide-silicon-silicon oxide stack Layer, the present invention preferably silicon oxide layer 701, amorphous silicon layer 702 (or replaced by other false mask layer, hereinafter take amorphous silicon as an example), silicon oxide layer 703 stacked from bottom to top mask Membrane (as shown in Figure 2 for example).
  • HM hard mask
  • Step S202 patterning the mask stack 7: first etching the top silicon oxide layer 703 and the amorphous silicon layer 702 in the mask stack by combining photolithography and etching processes to form a pattern mandrel, as shown in Figure 3 structure; then remove the photoresist 8.
  • Step S203 etching the silicon oxide layer 701 .
  • Step S204 etching the second silicon layer 6, the third silicon germanium layer 5, the second silicon germanium layer 4, the first silicon germanium layer 3, and the first silicon layer 2 to form a nano-stack structure as shown in FIG. 4, according to Nanowires or nanosheets determine the shape of the nanostack structure, for example, Figures 5 and 6 represent the top view structures of nanowires and nanosheets (the arrows in Figures 5 and 6 represent the cross-sectional direction of Figure 4), and all steps below are expressed in nanometers. Line is introduced as an example (but this does not limit the scope of application of the present invention).
  • the etching in the above-mentioned step S2 can be selected from dry method (reactive ion etching RIE, plasma etching, high-pressure plasma etching, high-density plasma etching), wet method (selecting an appropriate solvent or solution), or the like.
  • dry method reactive ion etching RIE, plasma etching, high-pressure plasma etching, high-density plasma etching
  • wet method selecting an appropriate solvent or solution
  • the preferred etching method is generally selected according to the type of material, which is not particularly limited in the present invention.
  • step S3 is performed to selectively etch the first silicon germanium layer 3 and the third silicon germanium layer 5 in the nano-stack structure, thereby forming
  • the first groove 3a and the third groove 5a have a structure as shown in FIG. 7 .
  • the methods for etching the first silicon germanium layer 3 and the third silicon germanium layer 5 in step S3 include but are not limited to dry continuous etching, dry atomic layer etching (ALE), wet continuous etching, wet ALE wait.
  • the amount of etching can be controlled by adjusting a variety of etching parameters, including the difference in germanium in the three germanium and silicon layers, etching dose, etching power, etching gas flow, etching chamber pressure and duration, etc.
  • the preferred means is ALE.
  • the selectivity of the etching means and conditions to the first silicon layer and the second silicon layer should also be considered.
  • the size of the first groove and the third groove can be better controlled, thereby controlling the size of the inner wall to be subsequently filled.
  • the etching amount in this step is preferably controlled at 5nm-25nm, that is, the depth of the first groove and the third groove reaches 5nm-25nm.
  • step S4 forming an inner wall of the expansion area in the first groove and the third groove.
  • the inner wall of the expansion area is preferably made of a material with good dielectric properties and a simple deposition process, such as typical silicon oxide.
  • step S3 Since the structure morphology obtained after step S3 has an irregular shape, the process of over-deposition and etching-back is required when forming the inner wall of the gate extension region in step S4. Specifically, the following steps can be adopted.
  • Step S401 depositing the inner wall material 9 of the expansion region (hereinafter, silicon oxide is used as an example) until covering all the outer surfaces.
  • the deposition means include but not limited to PECVD, LPCVD, ALD and other methods to obtain the structure shown in FIG. 8 .
  • step S402 the pseudo-mask amorphous silicon layer 702 in the mask stack is exposed by performing chemical mechanical polishing or selective etching on the silicon oxide. In this step, if the material of the inner wall of the expansion area is not silicon oxide, it needs to be carried out step by step.
  • step S403 anisotropic etching is performed until the wall material inside the expansion region only fills the first groove and the third groove.
  • step S403 in order to prevent the etching in step S403 from causing damage to the second silicon layer, it is preferable to replace the silicon layer in the mask with a material with a large etching selectivity difference from the inner wall material of the extension region. Etch selectivity compared to silicon in the inner wall material of the extension region. Taking silicon oxide as an example for the inner wall material of the extension region, it is preferable to replace the silicon in the mask with silicon nitride. To achieve the above purpose, the following steps can be added between step S402 and step S403 (for the convenience of description, the inner wall of the silicon oxide expansion area is taken as an example here):
  • Step S402a on the basis of FIG. 8 , filling a large area with the inner wall material of the expansion area such as silicon oxide.
  • Step S402b removing the silicon layer in the mask to form mask grooves 704 .
  • Step S402c filling the mask groove 704 with a material having a large etch selectivity difference from the inner wall material of the extension region, such as silicon nitride, to obtain a structure as shown in FIG. 11 .
  • a material having a large etch selectivity difference from the inner wall material of the extension region such as silicon nitride
  • it also needs to be deposited in a large area, and then remove the silicon nitride outside the mask groove by CMP, so that only the mask groove is filled with silicon nitride, which is a replacement mask 705.
  • step S403 forming the topography as shown in FIG. 12 by anisotropic etching to obtain the inner wall 9a of the expansion region.
  • the replacement mask 705 may also be removed after the step S403 is completed to obtain the structure shown in FIG. 13 , and the silicon oxide etch stop layer 701 of the top layer remains.
  • the replacement mask 705 may be removed in a subsequent process, which is not particularly limited in the present invention.
  • step S5 the second SiGe layer 4 is selectively etched to form a gate groove 4a on the sidewall of the second SiGe layer 4, as shown in FIG. 14 .
  • This step of etching preferably uses atomic layer etching (ALE). Since the silicon germanium material is used in this layer of the present invention, it has a large difference in etching selectivity from silicon, so the size of the channel and the size of the subsequent gates on both sides can be better controlled, and the device yield can be improved. The amount of etching in this step depends on the channel size.
  • ALE atomic layer etching
  • step S6 forming a dummy gate in the gate groove.
  • the purpose of pre-forming the dummy gate is to form the source and drain by doping on the one hand, and to form the shallow trench isolation on the other hand. Since the protection and conformation of the inner wall of the expansion area should be taken into consideration, comprehensive consideration should be taken when selecting the dummy material.
  • nitride is preferably used, such as common silicon nitride. Also, this step needs to be completed step by step due to the shape restriction on the dummy gate, such as the following method.
  • Step S601 deposit dummy gate material 10 until covering all the outer surfaces, preferably using an isotropic deposition method, such as the structure shown in FIG. 15 .
  • Step S602 then etch until only the dummy gate material 10 is filled in the gate groove to form a dummy gate 10a, preferably using anisotropic etching to obtain a structure as shown in FIG. 16 .
  • Step S603 removing the mask. If the substitute mask has been removed before, only the silicon oxide layer 701 (etching stop layer) needs to be taken out in this step to obtain the structure shown in FIG. 17 .
  • the first silicon layer 2 and the second silicon layer 6 are respectively doped to form source/drain electrodes 2a, 6a.
  • implanting elements such as boron, phosphorus or arsenic
  • the type depends on the device type.
  • the doping method and implantation angle are controlled according to device requirements.
  • step S8 after forming the dummy gate, the substrate is etched and a dielectric material is deposited to form an active region with a shallow trench isolation layer.
  • the active region When forming the active region, it is necessary to conform to the inner wall of the expansion region, so that the etching selectivity of the isolation material and each layer in the nano-stack structure is guaranteed at the same time. Therefore, it is necessary to form a protective layer on the side wall of the nano-stack structure, and then proceed. Specifically, the following steps can be adopted.
  • Step S801 forming a sidewall protective layer 11 on the sidewall of the nano-stacked structure to obtain the structure shown in FIG. 19 .
  • the protective layer can be made of silicon nitride and other dielectric materials. On the one hand, it protects the stack structure (especially the inner wall), and on the other hand, its bottom can be reserved as a source-drain isolation layer to reduce leakage current and parasitic capacitance.
  • the thickness of the protective layer 11 can be selected from 5 to 10 nm.
  • the protective layer is also formed in two steps: large-area deposition first, and then anisotropic etching.
  • step S802 the substrate is etched to form an active region.
  • Step S803 depositing silicon oxide and other dielectric materials until covering all the outer surfaces.
  • Step S804 and then etch back until the surface height of the dielectric material is equal to the upper surface height of the first SiGe layer to form the shallow trench isolation layer 12 , as shown in FIG. 20 .
  • step S9 the dummy gate 10a in the active region is removed to obtain the structure shown in FIG. 21 .
  • the protective layer in step S801 needs to be removed first.
  • the protective layer is preferably made of the same material as the dummy gate, such as silicon nitride, so that the protective layer and the dummy gate 10a can be removed simultaneously by isotropic etching using hot H3PO4 solution or RIE.
  • the removal process it is necessary to control the amount of etching and etching conditions to ensure that the remaining part of the sidewall protection between the shallow trench isolation layer (STI) and the first silicon layer (the source/drain has been formed by the previous process) layer material 11a (the structure shown in FIG. 21 ), the remaining part can separate the STI from the source/drain to reduce the leakage problem and reduce the parasitic capacitance at the same time.
  • step S10 forming a replacement gate stack layer, including gate dielectric layer 13 and gate 14 , to obtain the structure shown in FIG. 22 .
  • a high-k dielectric material can be used for the gate dielectric layer, including but not limited to HfO 2 , HfSiO x , HfAlO x , HfZrO x and the like.
  • a thinner oxide layer (0.3-1.5nm) can also be deposited as a barrier layer before depositing the gate dielectric.
  • a gate material is deposited outside the gate layer, and the gate material includes but not limited to titanium, tungsten, titanium nitride, etc., and may be a single layer or a stack of multiple layers. When depositing the gate dielectric and the gate, both are deposited in a large area, so it is necessary to etch back and/or polish the preset thickness and height.
  • the height of the gate is preferably lower than the height of the upper source/drain, more preferably lower than the height of the upper inner wall, so as to reduce parasitic capacitance.
  • step S11 pattern the gate 14 with the help of photoresist, form the patterned gate 14a and gate dielectric 13a, leave the landing pad 14b for leading out the contact hole, remove the photoresist, and obtain structure shown.
  • Fig. 25 is the top view of Fig. 24.
  • the vertical MOSFET device that utilizes above-mentioned method of the present invention to manufacture has roughly following structure:
  • FIG. 26 it includes a substrate 21, and a source/drain 22, a first extension region 23, a channel 28, a second extension region 25, and a source/drain stacked from bottom to top on the substrate 21. 26; both sides of the channel 28 are gates, and the gate is isolated from the channel 28 by a gate dielectric; both sides of the first extension region 23 are first inner wall 20, and the first Two sides of the second expansion area 25 are second inner walls 27 , and the gate 29 is located between the first inner walls 10 and the second inner walls 27 .
  • first extension region 23, the channel and the second extension region 25 are all silicon germanium materials, and the molar content of germanium in the first extension region 23 and the second extension region 25 is greater than that of germanium in the channel. content; the source/drain 22, 26 is doped silicon.
  • the first extension region 23 and the second extension region 25 are the remaining parts after the first silicon germanium layer and the third silicon germanium layer are etched by the above method, and are sandwiched by inner side walls. These two extension regions can be used as the extension of the channel .
  • the sidewalls of the source/drain, the sidewalls of the first inner wall 20 and the sidewalls of the second inner wall 27 are connected to form a groove profile, and the gate The pole 29 is located in said groove.
  • the width of the first inner wall of the first extension region 23 parallel to the direction of the nanowire channel is preferably 5-15 nm, and the depth of the groove perpendicular to the direction of the nanowire channel is preferably 5-25 nm.
  • the material of each layer in the MOSFET device is as described in the above process, and various types can be selected to suit it.
  • the present invention provides a MOSFET device with the above structure, it does not mean that the vertical MOSFET device provided by the present invention can only be manufactured by the above process, and it can also be obtained by other feasible methods.

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Abstract

本发明涉及一种垂直MOSFET器件及其制造方法、应用。方法包括：衬底上形成由下至上垂直堆叠的第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层；其中，第一锗硅层和第三锗硅层中锗的摩尔含量都大于第二锗硅层中锗的含量；刻蚀形成纳米堆叠结构；选择性刻蚀第一锗硅层和第三锗硅层，从而形成第一凹槽、第三凹槽；在第一凹槽、第三凹槽内形成扩展区内侧墙；选择性刻蚀第二锗硅层，形成栅极凹槽；在栅极凹槽内形成假栅；形成源漏极；形成具有浅沟槽隔离层的有源区；去除假栅，形成栅介质层、栅极。本发明能够很好的控制沟道尺寸、扩展区内侧墙尺寸、栅极尺寸等，并且在纳米片或纳米线结构中都适用。

Description

一种垂直MOSFET器件及其制造方法、应用 技术领域
本发明涉及晶体管领域，特别涉及一种垂直MOSFET器件及其制造方法、应用。
背景技术
对于MOSFET，由于它的集成度会是决定产品价格的重要因素，因此会特别期望提高集成度。对于二维或平面半导体器件，由于它们的集成度主要由单位存储单元在硅片表面占据的投影的面积，因此集成度受精细图案形成技术的水平的影响很大。然而，用于提高图案精细度的极其昂贵的工艺设备会对提高二维或平面半导体器件的集成度设定实际的限制。为了克服这种限制，已经提出了包括三维布置的存储单元的三维半导体存储装置。3D集成是对逻辑器件、DRAM等存储器件缩放的突破。然而由于光刻和反应离子刻蚀等工艺在刻蚀过程工艺的波动性以及工艺集成的复杂性，因此导致垂直纳米片或纳米线MOSFET中存在内侧墙的厚度等尺寸难以控制等问题。
目前垂直晶体管器件的性能相较于成熟的平面晶体管以及FinFET仍然有较大差距。这由于垂直晶体管在关键工艺模块和工艺集成上存在许多挑战。在垂直晶体管的关键工艺模块中包括刻蚀和选择性刻蚀，形成纳米线和纳米片沟道、内侧墙。为此，提出本发明。
发明内容
本发明的主要目的在于提供一种垂直MOSFET器件的制造方法，该方法能够很好的控制沟道尺寸、扩展区内侧墙尺寸、栅极尺寸等，并且在纳米片或纳米线结构中都适用。
本发明的另一目的在于提供一种垂直MOSFET器件，该器件增加了尺寸可控的扩展区内侧墙，相比现有的垂直晶体管器件具有更好的电学性能，例如低漏电、寄生电容小等。
为了实现以上目的，本发明提供了以下技术方案。
本发明的第一方面提供了一种垂直MOSFET器件的制造方法，包括下列步骤：
提供衬底；
在所述衬底上形成由下至上垂直堆叠的第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层；其中，所述第一锗硅层和第三锗硅层中锗的摩尔含量都大于所述第二锗硅层中锗的含量；
刻蚀所述第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层，形成纳米堆叠结构；
选择性刻蚀纳米堆叠结构中的第一锗硅层和第三锗硅层，从而在第一锗硅层和第三锗硅层的侧壁处分别形成第一凹槽、第三凹槽；
在所述第一凹槽、第三凹槽内形成扩展区内侧墙；
选择性刻蚀第二锗硅层，使第二锗硅层的侧壁处形成栅极凹槽；
在所述栅极凹槽内形成假栅；
对所述第一硅层和第二硅层分别进行掺杂，形成源/漏极；
形成源/漏极之后，刻蚀衬底、沉积介质材料，以形成具有浅沟槽隔离层的 有源区；
去除有源区内的假栅，然后在所述栅极凹槽内依次形成栅介质层、栅极；
进行后续工艺。
本发明的第二方面提供了一种垂直MOSFET器件，其包括衬底，以及在所述衬底上由下至上堆叠的源/漏极、第一扩展区、沟道、第二扩展区和源/漏极；所述沟道的两侧为栅极，并且栅极与所述沟道之间通过栅介质隔离；所述第一扩展区的两侧为第一内侧墙，所述第二扩展区的两侧为第二内侧墙，所述栅极位于所述第一内侧墙和所述第二内侧墙之间；
其中，所述第一扩展区、沟道和第二扩展区都为锗硅材料，并且所述第一扩展区和第二扩展区中锗的摩尔含量都大于所述沟道中锗的含量；所述源/漏极为掺杂硅。
本发明的第三方面提供了上述垂直MOSFET器件，或者利用上述制造方法制备的垂直MOSFET器件在电子器件中的应用。
与现有技术相比，本发明达到了以下技术效果：在栅极与源漏极之间增加内侧墙，并且通过设计特定的工艺顺序(例如，设计具有不同锗组分和不同刻蚀选择性的锗硅外延叠层、替代掩膜、内侧墙保护层结构，实现了垂直晶体管内侧墙工艺的集成开发)实现该内侧墙的尺寸可控化，还同步实现了栅极尺寸和沟道尺寸的可控化，从而减少了器件的漏电问题、降低寄生电容、减少器件加工中的不良现象；利用本发明方法制作的垂直MOSFET器件可用于SRAM、DRAM、Flash等各类存储器器件中。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。
图1至25为本发明提供的垂直MOSFET器件的制造方法各步得到结构图；
图26为本发明提供的垂直MOSFET器件的剖视结构示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时， 该层/元件可以位于该另一层/元件“下”。
正如背景技术所介绍的，现有技术中垂直堆叠纳米线/片晶体管由于扩展区内侧墙尺寸、栅极尺寸等结构尺寸不可控，导致晶体管中各结构尺寸存在差异，进而限制了垂直堆叠纳米线/片晶体管的实际应用。本发明针对以上问题进行研究，提出了一种垂直MOSFET器件的制造方法，该方法在栅极与源漏极之间增加内侧墙，并且通过设计特定的工艺顺序实现该内侧墙的尺寸可控化，还同步实现了栅极尺寸和沟道尺寸的可控化，从而减少了器件的漏电问题、降低寄生电容、减少器件加工中的不良现象。本发明提供的制作方法包括下列步骤。
首先步骤S1，在衬底1上形成由下至上垂直堆叠的第一硅层2、第一锗硅层3、第二锗硅层4、第三锗硅层5、第二硅层6，得到如图1所示的结构。
其中，所述第一锗硅层3和第三锗硅层5中锗的摩尔含量都大于所述第二锗硅层4中锗的含量，通过锗含量的差异化可以实现三个锗硅层的选择性刻蚀。另外，由于所述第一锗硅层3和第三锗硅层5在后续工艺中要实现同步刻蚀，因此优选所述第一锗硅层3和第三锗硅层5采用锗含量相同的材料。例如，所述第一锗硅层3和第三锗硅层5中锗的摩尔含量优选为15％以上(15％、20％、25％、30％、35％、40％、45％、50％、55％等，其中更优选15％～30％)，与之相匹配的，第二锗硅层4中锗的摩尔含量优选为15％以下(例如1％、3％、5％、7％、10％、13％、15％等，其中，更优选5％～15％)。
上述的衬底1可以是本领域技术人员熟知的任何用以承载半导体集成电路组成元件的底材，例如绝缘体上硅(silicon-on-insulator，SOI)、体硅(bulk silicon)、碳化硅、锗、锗硅、砷化镓或者绝缘体上锗等，相应的顶层半导体材料为硅、锗、锗硅或砷化镓等。同时该基底上的半导体层根据器件类型确定掺杂类型，以形成P阱(用于nMOSFET)或者n阱(用于pMOSFET)，如图1中用虚线框示出了掺杂区域(图1至25的剖视图的衬底中都标识了掺杂区1a和非掺杂区的分界线)。
第一硅层2和第二硅层6可通过经过后续刻蚀、掺杂将作为晶体管的源/漏极，也可以通过外延生长第一硅层2和第二硅层6时进行原位掺杂，以形成高浓度掺杂的n型或者p型导电层(掺杂浓度为1×10 19～1×10 21cm -3)。因此其厚度、掺杂浓度和掺杂种类等参数根据产品设计而定。
第一锗硅层3和第二锗硅层5通过外延生长形成，第一锗硅层3和第二锗硅层5可以是不掺杂的，也可以通过外延生长时原位掺杂，掺杂浓度为1×10 18～1×10 20cm -3，第一锗硅层3和第二锗硅层5的掺杂浓度应低于第一硅层2和第二硅层6的掺杂浓度，以抑制热载流子注入效应。
第二锗硅层4经过后续刻蚀后将作为沟道，因此其厚度优选大于所述第一锗硅层3和第三锗硅层5中的厚度。例如，在一些典型电子器件中，第一锗硅层3和第三锗硅层5的厚度各自独立地为5～15nm，所述第二锗硅层4的厚度为15～100nm。
根据以上三个锗硅层和两个硅层的材料类型，选择适当的形成工艺，通常包括但不限于减压化学气相沉积(RPCVD)、金属有机化合物化学气相沉积(MOCVD)等外延生长方法等。
继续步骤S2，刻蚀所述第一硅层2、第一锗硅层3、第二锗硅层4、第三锗硅层5、第二硅层6，形成纳米堆叠结构。
由于第二硅层6要作为晶体管的源/漏极，因此刻蚀时需要对其进行充分保护，同时要保证图形的规则化，因此需要借助掩膜进行刻蚀，即预先在第二硅层6上沉积掩膜，然后刻蚀。例如采用如下的方式。
步骤S201，在第二硅层6上沉积掩膜叠层7，该掩膜叠层7优选采用硬掩模(HM)，例如TiN、SiN、SiO2、无定形硅、多晶硅等，优选多层堆叠，这样可以适应不同工序中刻蚀的不同选择性，同时包含蚀刻停止层等，起到更好的保护作用，例如常见的氮化硅-硅-氮化硅或者氧化硅-硅-氧化硅叠层的，本发明优选氧化硅层701、无定形硅层702(或者替换为其他的假掩膜层，下文以无定形硅为例介绍)、氧化硅层703自下而上堆叠而成的掩膜(如图2示例)。
步骤S202，图案化掩膜叠层7：先结合光刻和刻蚀工艺刻蚀掩膜叠层中的顶部氧化硅层703和无定形硅层702，形成图案心轴，得到如图3所示的结构；然后去除光刻胶8。
步骤S203，刻蚀氧化硅层701。
步骤S204，刻蚀第二硅层6、第三锗硅层5、第二锗硅层4、第一锗硅层3、第一硅层2，形成如图4所示的纳米堆叠结构，根据纳米线或纳米片确定纳米堆叠结构的形状，例如如图5和6分别表示纳米线和纳米片的俯视结构(图5和6的箭头表示图4的剖视方向)，下文所有步骤都以纳米线为例介绍(但这并不能限制本发明的应用范围)。
上述步骤S2中的刻蚀可以选择干法(反应离子刻蚀RIE、等离子刻蚀、高压等离子刻蚀、高密度等离子体刻蚀)、湿法(选择适当的溶剂或溶液)等方式，也可以在刻蚀之前结合抛光(CMP)步骤，通常根据材料类型选择其优选的刻蚀手段，本发明对此不作特别限制。
接下来进行步骤S3，选择性刻蚀纳米堆叠结构中的第一锗硅层3和第三锗硅层5，从而在第一锗硅层3和第三锗硅层5的侧壁处分别形成第一凹槽3a、第三凹槽5a，得到如图7所示的结构。
步骤S3刻蚀第一锗硅层3和第三锗硅层5的方法包括但不限于干法连续性刻蚀、干法原子层刻蚀(ALE)、湿法连续性刻蚀、湿法ALE等。可以通过调控多种刻蚀参数控制刻蚀量，包括三个锗硅层中锗的差异大小、刻蚀剂量、刻蚀功率、刻蚀气体流量、刻蚀腔体气压及时长等手段，刻蚀手段优选ALE。同时除了考虑对第二锗硅层的选择性外，还要考虑刻蚀手段及条件对第一硅层、第二硅层的选择性。由于本发明所选择的锗硅层与硅层具有差异大的刻蚀选择性，因此能更好地控制第一凹槽、第三凹槽的尺寸，进而控制后续填充的内侧墙的尺寸。对于典型的MOSFET器件，这一步的刻蚀量优选控制在5nm-25nm，即第一凹槽、第三凹槽的深度达到5nm-25nm。
继续步骤S4，在所述第一凹槽、第三凹槽内形成扩展区内侧墙。扩展区内侧墙优选选用介电性能好、沉积工艺简单的材料，例如典型的氧化硅。
由于在步骤S3之后得到的结构形貌具有不规则形，因此，在步骤S4形成栅扩展区内侧墙时要经过过沉积、回刻的过程，具体可以采用如下步骤。
步骤S401，沉积扩展区内侧墙材料9(下文以氧化硅为例)直至覆盖所有外表面，沉积手段包括但不限于PECVD、LPCVD、ALD等方法，得到如图8所示的结构。
步骤S402，然后通过对氧化硅进行化学机械研磨或选择性刻蚀至掩膜叠层 中的假掩膜无定形硅层702裸露。这一步中，若扩展区内侧墙材料不是氧化硅，则需要分步进行。
步骤S403，再各向异性刻蚀至扩展区内侧墙材料仅充满所述第一凹槽和第三凹槽。
其中，为了避免步骤S403的刻蚀不对第二硅层造成损伤，优选将掩膜中硅层替换为与扩展区内侧墙材料刻蚀选择性差异大的材料，此次的“差异大”是相比扩展区内侧墙材料与硅的刻蚀选择性。以氧化硅作为扩展区内侧墙材料为例，优选将掩膜中的硅替换为氮化硅。为实现以上目的，可以在步骤S402和步骤S403之间增设以下步骤(为方便描述，此处以氧化硅扩展区内侧墙为例)：
步骤S402a，在图8基础上大面积填充氧化硅等扩展区内侧墙材料。
步骤S402b，去除掩膜中的硅层，形成掩膜凹槽704。这一步可以先对氧化硅等扩展区内侧墙材料CMP至掩膜中的假掩膜无定形硅层裸露，得到图9所示的结构；然后利用TMAH等湿法刻蚀手段刻蚀去除假掩膜无定形硅层，形成掩膜凹槽704，得到如图10所示的结构。
步骤S402c，在所述掩膜凹槽704内填充与扩展区内侧墙材料刻蚀选择性差异大的材料，例如氮化硅，得到如图11所示的结构。同样地，这一步在沉积氮化硅时，也需要大面积沉积后，然后通过CMP去除掩膜凹槽外的氮化硅，使得仅掩膜凹槽内充满氮化硅，即为替代掩模705。
然后进行步骤S403，通过各向异性刻蚀形成如图12所示的形貌，得到扩展区内侧墙9a。另外，也可以在步骤S403完成后去除替代掩模705，得到如图13所示的结构，还剩余顶层的氧化硅蚀刻停止层701。在实际工艺中，替代掩模705可以在后续工艺中去除，本发明对此并不做特别限制。
继续步骤S5，选择性刻蚀第二锗硅层4，使第二锗硅层4的侧壁处形成栅极凹槽4a，如图14所示的结构。
这一步刻蚀优选采用原子层刻蚀(ALE)。由于本发明这一层采用锗硅材料，其与硅具有差异大的刻蚀选择性，因此，也能更好地控制沟道尺寸以及后续两侧栅极的尺寸等，提高器件良率。这一步刻蚀量根据沟道尺寸而定。
继续步骤S6，在所述栅极凹槽内形成假栅。预先形成假栅的目的一方面是为了掺杂形成源漏极，另一方面是为了形成浅沟槽隔离。由于要考虑到对扩展区内侧墙的保护和保形，因此在选择假材料时应当考虑全面，本发明优选采用氮化物，例如常见的氮化硅。同样这一步由于对假栅有形状限制，因此需要分步完成，例如下述的方法。
步骤S601，沉积假栅材料10直至覆盖所有外表面，优选采用各向同性沉积法，如图15所示的结构。
步骤S602，然后刻蚀至仅所述栅极凹槽内填充假栅材料10，形成假栅10a，优选采用各向异性法刻蚀，得到如图16所示的结构。
步骤S603，去除掩膜，若替代掩模已在之前去除，则这一步只需要取出氧化硅层701(蚀刻停止层)，得到如图17所示的结构。
继续步骤S7，对所述第一硅层2和第二硅层6分别进行掺杂，形成源/漏极2a、6a。例如注入硼、磷或砷等元素，类型根据器件类型而定。其中，在掺杂第一硅层2时会对衬底浅表层进行掺杂，并且有可能第一硅层只有两侧边缘区域1b被掺杂，如图18所示。在实际应用时根据器件需求控制掺杂方式以及注 入角度等。
继续步骤S8，形成假栅之后，刻蚀衬底、沉积介质材料，以形成具有浅沟槽隔离层的有源区。
形成有源区时需要对扩展区内侧墙保形，因此同时保证隔离材料与纳米堆叠结构中各层的刻蚀选择性，因此，需要在纳米堆叠结构的侧壁形成保护层，之后再进行，具体可采用如下的步骤。
步骤S801，在所述纳米堆叠结构的侧壁形成侧墙保护层11，得到如图19所示的结构。该保护层可采用氮化硅等介质材料，一方面保护堆叠结构(尤其是内侧墙)，另一方面其底端可以留用，作为源漏极的隔离层，以减少漏电流和寄生电容。保护层11的厚度可以选择5～10nm。利用常见的沉积工艺，保护层也是分两步形成：先大面积沉积，然后各向异性刻蚀。
步骤S802，然后刻蚀衬底，形成有源区。
步骤S803，再沉积氧化硅等介质材料直至覆盖所有外表面。
步骤S804，再回刻至介质材料的表面高度与第一锗硅层的上表面高度齐平，形成浅沟槽隔离层12，如图20所示的结构。
继续步骤S9，去除有源区内的假栅10a，得到如图21所示的结构。
如果存在步骤S801的保护层，则需要先去除保护层。为了简化工艺，保护层优选采用与假栅相同的材料，例如氮化硅，这样可以利用热H3PO4溶液或者RIE等手段各向同性刻蚀同步去除保护层和假栅10a。在去除的过程中，需要控制刻蚀量及刻蚀条件等，以保证浅沟槽隔离层(STI)与第一硅层(已通过先前工艺形成源/漏极)之间残留部分侧墙保护层材料11a(如图21所示的结构)，残留的这一部分可以间隔开STI与源/漏极，以减少漏电问题，同时减小寄生电容。
继续步骤S10，形成替代栅堆叠层，包括栅介质层13、栅极14，得到如图22所示的结构。
在这一步，栅介质层可采用高k介质材料，包括但不限于HfO 2、HfSiO x、HfAlO x、HfZrO x等。在沉积栅介质之前还可以沉积较薄的氧化层(0.3～1.5nm)作为阻挡层。栅极层之外再沉积栅极材料，栅极材料包括但不限于钛、钨、氮化钛等，可以是单层或多层的堆叠。在沉积栅介质和栅极时，都为大面积沉积，因此需要回刻和/或抛光预设的厚度、高度。其中，栅极的高度优选低于上部源/漏极的高度，更优选低于上部内侧墙的高度，以减小寄生电容。
继续步骤S11，借助光刻胶对栅极14图形化，形成图形化的栅极14a和栅介质13a，留出用于引出接触孔的着陆垫14b，移除光刻胶，得到如图23所示的结构。
最后再大面积沉积氧化硅，分别引入源/漏极接触孔和栅极接触孔(包括源/漏极接触孔16、17，以及栅极接触孔15)，实现金属互连等，得到如图24所示的结构，图25为图24的俯视形貌。
利用本发明上述的方法制造出的垂直MOSFET器件具有大致如下的结构：
如图26所示，包括衬底21，以及在所述衬底21上由下至上堆叠的源/漏极22、第一扩展区23、沟道28、第二扩展区25和源/漏极26；所述沟道28的两侧为栅极，并且栅极与所述沟道28之间通过栅介质隔离；所述第一扩展区23的两侧为第一内侧墙20，所述第二扩展区25的两侧为第二内侧墙27，所述栅 极29位于所述第一内侧墙10和所述第二内侧墙27之间。
其中，所述第一扩展区23、沟道和第二扩展区25都为锗硅材料，并且所述第一扩展区23和第二扩展区25中锗的摩尔含量都大于所述沟道中锗的含量；所述源/漏极22、26为掺杂硅。
第一扩展区23和第二扩展区25即为上文方法刻蚀第一锗硅层和第三锗硅层之后剩余的部分，被内侧墙夹心，这两个扩展区可以作为沟道的延伸。
由上述工艺制备出的MOSFET器件中，所述源/漏极的侧壁、所述第一内侧墙20的侧壁和所述第二内侧墙27的侧壁相连形成凹槽轮廓，所述栅极29位于所述凹槽内。所述第一扩展区23的第一内侧墙的平行于纳米线沟道方向的宽度优选为5～15nm，所述凹槽的垂直于纳米线沟道方向的深度为优选5～25nm。
同时该MOSFET器件中各层的材料如上文工艺所述，可以选择与之适应的多种类型。
虽然本发明提供了一种具有上述结构的MOSFET器件，但这并不代表本发明提供的垂直MOSFET器件仅能通过上述工艺制成，其还可以通过其他可行的方法获得。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (27)

  1. 一种垂直MOSFET器件的制造方法，其特征在于，包括下列步骤：
    提供衬底；
    在所述衬底上形成由下至上垂直堆叠的第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层；其中，所述第一锗硅层和第三锗硅层中锗的摩尔含量都大于所述第二锗硅层中锗的含量；
    刻蚀所述第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层，形成纳米堆叠结构；
    选择性刻蚀纳米堆叠结构中的第一锗硅层和第三锗硅层，从而在第一锗硅层和第三锗硅层的侧壁处分别形成第一凹槽、第三凹槽；
    在所述第一凹槽、第三凹槽内形成扩展区内侧墙；
    选择性刻蚀第二锗硅层，使第二锗硅层的侧壁处形成栅极凹槽；
    在所述栅极凹槽内形成假栅；
    对所述第一硅层和第二硅层分别进行掺杂，形成源/漏极；
    刻蚀衬底、沉积介质材料，以形成具有浅沟槽隔离层的有源区；
    去除有源区内的假栅，然后在所述栅极凹槽内形成栅堆叠层的替代栅，其中，所述替代栅按照堆叠顺序包括栅介质层、栅极；
    进行后续工艺。
  2. 根据权利要求1所述的制造方法，其特征在于，所述第一锗硅层和第三锗硅层中锗的摩尔含量相同，为15％以上。
  3. 根据权利要求1所述的制造方法，其特征在于，所述第一锗硅层和第三锗硅层中锗的摩尔含量为15％～30％，和/或，所述第二锗硅层中锗的摩尔含量为5％～15％。
  4. 根据权利要求1所述的制造方法，其特征在于，所述第一锗硅层和第三锗硅层的厚度小于所述第二锗硅层的厚度。
  5. 根据权利要求4所述的制造方法，其特征在于，所述第一锗硅层和第三锗硅层的厚度各自独立地为5～15nm，所述第二锗硅层的厚度为15～100nm。
  6. 根据权利要求1所述的制造方法，其特征在于，所述形成纳米堆叠结构的方法为：
    在所述第二硅层的表面形成掩膜叠层；
    图案化掩膜叠层；
    在掩膜叠层的保护下刻蚀所述第一硅层、第一锗硅层、第二锗硅层、第三锗硅层、第二硅层，形成纳米堆叠结构。
  7. 根据权利要求6所述的制造方法，其特征在于，所述掩膜叠层包括从下至上依次堆叠的蚀刻停止层、假掩膜层、氧化硅层。
  8. 根据权利要求6所述的制造方法，其特征在于，所述蚀刻停止层为氧化硅；
    和/或，
    所述假掩膜层与氧化硅有高刻蚀选择比。
  9. 根据权利要求1所述的制造方法，其特征在于，所述第一凹槽和所述第三凹槽的深度为5nm～25nm。
  10. 根据权利要求7所述的制造方法，其特征在于，在所述第一凹槽、第三凹槽内形成扩展区内侧墙的方法包括：
    沉积扩展区内侧墙材料直至覆盖所有外表面；
    然后对扩展区内侧墙材料和掩膜叠层中的氧化硅层进行化学机械研磨或选择性刻蚀，直至所述掩膜叠层中的假掩膜层裸露；
    再各向异性刻蚀至扩展区内侧墙材料仅充满所述第一凹槽和第三凹槽，从而形成扩展区内侧墙。
  11. 根据权利要求10所述的制造方法，其特征在于，所述扩展区内侧墙材料为氧化硅。
  12. 根据权利要求10所述的制造方法，其特征在于，在所述掩膜叠层中的硅层裸露之后和所述各向异性刻蚀之前还包括：
    大面积填充扩展区内侧墙材料；
    通过选择性刻蚀去除掩膜叠层中的假掩膜层，形成掩膜凹槽；
    在所述掩膜凹槽内填充与氧化硅有较大刻蚀选择比的材料，形成替代掩膜。
  13. 根据权利要求12所述的制造方法，其特征在于，在所述掩膜凹槽内填充的材料与所述假栅相同。
  14. 根据权利要求7-、10或12任一项所述的制造方法，其特征在于，在所述栅极凹槽内形成假栅的方法包括：
    沉积假栅材料直至覆盖所有外表面；
    然后各向异性刻蚀至仅所述栅极凹槽内填充假栅材料，形成假栅；
    进行掺杂形成源/漏极注之前，去除掩膜叠层。
  15. 根据权利要求1所述的制造方法，其特征在于，形成具有浅沟槽隔离层的有源区的方法包括：
    在所述纳米堆叠结构的侧壁形成扩展区内侧墙的侧墙保护层；
    然后刻蚀衬底，形成有源区；
    再沉积介质材料直至覆盖所有外表面；
    再回刻至介质材料的表面高度与第一锗硅层的上表面高度齐平，形成浅沟槽隔离层。
  16. 根据权利要求1所述的制造方法，其特征在于，所述介质材料包括氧化硅、PSG、BSG、BPSG中的至少一种。
  17. 根据权利要求15所述的制造方法，其特征在于，去除假栅的方法包括：
    刻蚀侧墙保护层至所述浅沟槽隔离层与所述第一硅层之间残留部分侧墙保护层材料，其余侧墙保护层及假栅通过选择性刻蚀被去除。
  18. 根据权利要求1所述的制造方法，其特征在于，形成栅极之后还对栅极进行图案化、形成接触孔。
  19. 根据权利要求15所述的制造方法，其特征在于，所述侧墙保护层和所述假栅为相同的材料。
  20. 根据权利要求19所述的制造方法，其特征在于，所述侧墙保护层和所述假栅为氮化硅或氮氧化硅。
  21. 一种垂直MOSFET器件，其特征在于，包括衬底，以及在所述衬底上由下至上堆叠的源/漏极、第一扩展区、沟道、第二扩展区和源/漏极；所述沟道的两侧为栅极，并且栅极与所述沟道之间通过栅介质隔离；所述第一扩展区的两侧为第一内侧墙，所述第二扩展区的两侧为第二内侧墙，所述栅极位于所述第一内侧墙和所述第二内侧墙之间；
    其中，所述第一扩展区、沟道和第二扩展区都为锗硅材料，并且所述第一扩展区和第二扩展区中锗的摩尔含量都大于所述沟道中锗的含量；所述源/漏极为掺杂硅。
  22. 根据权利要求21所述的垂直MOSFET器件，其特征在于，所述第一内侧墙和所述第二内侧墙为氧化硅。
  23. 根据权利要求21所述的垂直MOSFET器件，其特征在于，所述第一扩展区和第二扩展区中锗的摩尔含量相同，为15％以上。
  24. 根据权利要求21所述的垂直MOSFET器件，其特征在于，所述第一扩展区和第二扩展区中锗的摩尔含量为15％～30％，和/或，所述沟道中锗的摩尔含量为5％～15％。
  25. 根据权利要求21所述的垂直MOSFET器件，其特征在于，所述源/漏极的侧壁、所述第一内侧墙的侧壁和所述第二内侧墙的侧壁相连形成凹槽轮廓，所述栅极位于所述凹槽内。
  26. 根据权利要求25所述的垂直MOSFET器件，其特征在于，所述第一扩展区的第一内侧墙的平行于纳米线沟道方向的宽度为5～15nm，和/或，所述凹槽的垂直于纳米线沟道方向的深度为5～25nm。
  27. 权利要求21-26任一项所述的垂直MOSFET器件或者根据权利要求1-20任一项所述的制造方法制造出的垂直MOSFET器件在电子器件中的应用。
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