CN106252391A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
CN106252391A
CN106252391A CN201510311627.3A CN201510311627A CN106252391A CN 106252391 A CN106252391 A CN 106252391A CN 201510311627 A CN201510311627 A CN 201510311627A CN 106252391 A CN106252391 A CN 106252391A
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fin structure
fin
insulation layer
substrate
epitaxial layer
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CN201510311627.3A
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CN106252391B (zh
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冯立伟
蔡世鸿
刘鸿辉
林昭宏
黄南元
郑志祥
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201510311627.3A priority Critical patent/CN106252391B/zh
Priority to US14/792,591 priority patent/US9502410B1/en
Priority to US15/293,292 priority patent/US9583394B2/en
Publication of CN106252391A publication Critical patent/CN106252391A/zh
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构包含一基底，一第一鳍状结构与一第二鳍状结构位于该基底上，一第一绝缘区，位于该第一鳍状结构与该第二鳍状结构之间，一第二绝缘区，位于该第一鳍状结构相对于该第一绝缘区另外一侧的基底中，以及至少一外延层，位于该第一鳍状结构与该第二鳍状结构侧边，其中该外延层具有一底面，该底面至少从该第一鳍状结构延伸至该第二鳍状结构，且该底面低于该第一绝缘区的一底面以及该第二绝缘区的一顶面。

Description

半导体结构及其制作方法
技术领域
本发明涉及半导体领域，尤其是涉及一种具有优选品质的外延层的半导体结构。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，除了影响通道区载流子的迁移率之外，又影响元件的整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
为解决上述问题，本发明提供一种半导体结构，包含一基底，一第一鳍状结构与一第二鳍状结构位于该基底上，一第一绝缘区，位于该第一鳍状结构与该第二鳍状结构之间，一第二绝缘区，位于该第一鳍状结构相对于该第一绝缘区另外一侧的基底中，以及至少一外延层，位于该第一鳍状结构与该第二鳍状结构侧边，其中该外延层具有一底面，该底面至少从该第一鳍状结构延伸至该第二鳍状结构，且该底面低于该第一绝缘区的一底面以及该第二绝缘区的一顶面。
本发明另提供一种半导体结构的形成方法，包含：首先，提供一基底，一第一鳍状结构与一第二鳍状结构位于该基底上，接着形成一第一绝缘区，位于该第一鳍状结构与该第二鳍状结构之间，并形成一第二绝缘区，位于该第一鳍状结构相对于该第一绝缘层另外一侧的基底中，然后，形成至少一外延层，位于该第一鳍状结构与该第二鳍状结构侧边，其中该外延层具有一底面，该底面至少从该第一鳍状结构延伸至该第二鳍状结构，且该底面低于该第一绝缘区的一底面以及该第二绝缘区的一顶面。
本发明特征在于，在制作鳍状结构过程中，就已经先移除部分的鳍状结构，以预留后续制作外延层的生长区域。如此一来，可提升后续外延层制作的品质，进一步提高半导体结构的效能。此外，本发明的外延层同时接触多个鳍状结构，换句话说，同时形成多个晶体管的源/漏极区域，也进一步提高制作工艺的便利性。
附图说明
图1至图8为本发明的第一优选实施例的半导体结构的制作方法示意图；
图9为本发明另外一实施例的剖视图；
图10为本发明另外一实施例的剖视图。
主要元件符号说明
110 基底
112 鳍状结构
112a 虚置鳍状结构
114 鳍状结构
116 凹槽
120 绝缘层
120a 顶面
122 第一绝缘区
124 第二绝缘区
130 栅极结构
132 栅极介电层
134 栅极导电层
136 帽盖层
140 凹槽
142 底面
144 侧壁
150 外延层
150a 外延层
152 底面
152a 底面
154 侧壁
210 基底
214 鳍状结构
230 栅极结构
236 帽盖层
238 间隙壁
250 外延层
t1 夹角
t2 夹角
t3 夹角
D1 深度
D2 深度
A1 主动区
S 源极区
D 漏极区
A-A’ 剖面线
B-B’ 剖面线
a、b 长度
M 中线
P1 蚀刻步骤
P2 蚀刻步骤
P3 鳍状切割步骤
P4 蚀刻步骤
P5 外延成长步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
图1至图8绘示了本发明的第一优选实施例的半导体结构的制作方法示意图。请参照图1，图1绘示了半导体结构于初始阶段的立体图。如图1所示，首先，提供一基底100，基底100上设置有多个鳍状结构112。基底100除了块硅基底之外，上述基底100也可例如是一含硅基底、一三五族半导体覆硅基底(例如GaAs-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或硅覆绝缘(silicon-on-insulator,SOI)基底、氧化硅基底(silicon dioxide)、铝化硅基底(aluminum oxide),蓝宝石基底(sapphire)、含锗(germanium)基底或是硅锗合金基底(alloy of silicon and germanium)等半导体基底。
详细来说，鳍状结构112的制备方法可包括下列步骤，但不以此为限。举例来说，首先提供一块状基底(未绘示)，并在其上形成硬掩模层(未绘示)，接着利用光刻以及蚀刻制作工艺，将硬掩模层图案化，以定义出后续欲对应形成的鳍状结构112的位置。接着，进行一蚀刻步骤P1，将定义于硬掩模层内的图案转移至块状基底中，而形成所需的鳍状结构112。最后选择性地去除硬掩模层，便可获得如图1所示的结构。在此情况下，鳍状结构112可视为延伸出自基底10的一表面，且彼此间具有相同的成分组成，例如单晶硅。另一方面，当基底并非选自上述块状基底，而是选自于三五族半导体覆硅基底时，则鳍状结构的主要组成会与此基底的三五族半导体组成相同。
接着如图2所示，再次进行一光刻以及蚀刻步骤P2，将上述的鳍状结构112部分移除，而形成多个彼此分离的鳍状结构114。更详细说明，可在基底上形成另一硬掩模层(图未示)，硬掩模层优选为多个彼此平行排列的长条形光致抗蚀剂图案，其中各长条形硬掩模层的延伸方向优选与鳍状结构112的延伸方向垂直。因此在经过蚀刻步骤之后，各鳍状结构112将会被分割成多个彼此相互分开的鳍状结构114。值得注意的是，此步骤中，鳍状结构112被移除的区域，将会是后续步骤中生长外延层的区域，将会在后续段落中描述。另外，在此步骤中可能有部分的鳍状结构作为虚置鳍状结构(例如图2中的虚置鳍状结构112a)，而不会被蚀刻形成鳍状结构114。
此外，上述步骤中，先形成鳍状结构112之后，再利用另外一次的蚀刻步骤P2以移除部分鳍状结构112，而形成鳍状结构114。然而本发明的另外一实施例中，也可以在形成长条状硬掩模层后，进行一蚀刻步骤，直接移除部分的硬掩模层，因而形成多个彼此分开的硬掩模层，再进行一次蚀刻步骤，将上述硬掩模层的图案转移至基底100中，形成如图2所示的鳍状结构114，也属于本发明的涵盖范围。除此之外，上述的硬掩模层可通过一侧壁图案转移(sidewalls image transfer,SIT)步骤形成于基底上，该方法属于本领域的熟知技术而不在此赘述。
接下来，再利用一光致抗蚀剂图案(未绘示)当作掩模来进行一鳍状结构切割(fin-cut)步骤。如图3所示，经过鳍状切割步骤P3之后，部分鳍状结构112与部分的基底被移除而形成凹槽116。一般来说，凹槽116所在的区域将再后续步骤会被填入绝缘层，而形成例如浅沟隔离(shallow trenchisolation,STI)的绝缘区。而被凹槽116所包围的区域A1可定义为半导体元件的主动区，也就是后续步骤中形成的晶体管等元件的所在区域。
如图4所示，全面性形成一平坦的绝缘层120于基底110上，覆盖各鳍状结构114并且填入凹槽116中，绝缘层120例如为氧化硅或是氮化硅等绝缘材质。其中主动区A1内的绝缘层的厚度较各鳍状结构114的厚度小。更详细说明，本发明中，在各鳍状结构114之间的绝缘层120可定义为一第一绝缘区122，而各凹槽116被填入绝缘层120后，形成第二绝缘区124，且第二绝缘区124的深度D2应大于第一绝缘区122的深度D1。此外，在形成绝缘层120之前，可先选择性形成一衬垫层于基底与绝缘层120之间，在此不另外赘述。
如图5所示，形成多个栅极结构130，位于绝缘层120上并且横跨于各鳍状结构114上。其中各栅极结构130可包含一栅极介电层132、一栅极导电层134以及一帽盖层136。其中栅极介电层132的材料可以包括氧化硅(SiO)、氮化硅(SiN)、氮氧化硅(SiON)，或包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium siliconoxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconiumsilicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconatetitanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。栅极导电层134的材料可以包括未掺杂的多晶硅、重掺杂的多晶硅、金属硅化物、或是单层或多层金属层，金属层例如功函数金属层，阻挡层和低电阻金属层等。帽盖层136可包括单层结构或多层的介电材料，例如氧化硅(SiO)、氮化硅(SiN)、碳化硅(SiC)、碳氮化硅(SiCN)，氮氧化硅(SiON)或者其组合。此外，栅极结构130侧壁应含有间隙壁，但为了附图简洁，间隙壁未被绘于图5中，而绘示于以下叙述的图6中。
图6分别绘示图5中沿着剖面线A-A’以及剖面线B-B’所得的剖面结构图。配合图5所绘的立体结构说明，沿着剖面线A-A’的剖视图即为沿着X方向的剖视图；着剖面线B-B’的剖视图即为沿着Y方向的剖视图。为明确说明本发明的结构特征，接下来的图示将以剖面结构表示，各元件之间的相对位置可以参考图5与图6而得到正确的位置关系。另外，上述间隙壁138标示于图6中的Y方向剖视图。
图7绘示图6的剖面结构中经过一外延凹槽蚀刻步骤后所得的剖视图。如图7所示，先形成一图案化光致抗蚀剂(图未示)于绝缘层120上，该图案化光致抗蚀剂具有多条开口图案，且各开口图案分别位于相邻的栅极结构130之间，接着进行一蚀刻步骤P4，在各栅极结构的两侧各形成一凹槽140，其中在蚀刻凹槽140的过程中，除了移除部分的绝缘层120之外，鳍状结构114与基底110也可能一并/或是在后续另外的蚀刻步骤被部分移除，因此凹槽140的底面142可能会比原先主动区A1内的基底110的顶面更低，或是从Y方向的剖视图来看(剖面线B-B’的方向)，凹槽140的底部142较鳍状结构114的底部更低。此外，从沿着X方向的剖视图(剖面线A-A’的方向)来看，凹槽140还具有两侧壁144，且底面142与侧壁144之间的夹角t1角度优选大于90度，但不限于此。实际上凹槽的形状还可以依照需求而调整。
最后，图8绘示图7的剖面结构中经过一选择性外延成长步骤后所得的剖视图。如图8所示，在移除图案化光致抗蚀剂之后，进行一选择性外延成长(SEG)步骤，以于凹槽140内形成一外延层150，且外延层150是填满凹槽140。熟悉该项技术的人士应知，在进行外延成长步骤P5时，外延层150是沿着凹槽140的各表面成长。因此，外延层150具有一底面152，且底面152较绝缘层120的顶面120a(也就是第二绝缘区124的顶面)更低，此外底面152也应比第一绝缘层122的底面更低(其中第一绝缘层122的底面可参考图6所示)。除此之外，外延层150的平坦底面152与其侧壁154之间的夹角优选大于90度。值得注意的是，外延层150位于各鳍状结构114的侧边，且底面152至少延伸经过两个以上的鳍状结构114。换句话说，外延层150的底面152位于基底110中，且外延层150直接接触两个以上的鳍状结构114。
在上述实施例中，外延层150具有平坦底面152。然而在本发明另外一实施例中，可参考图9所示，其绘示本发明另外一实施例的半导体结构的局部剖视图。外延层150a的底面152a具有一夹角t2，并非具有一平坦的底面。该实施例也属于本发明的涵盖范围内。
根据不同实施例，外延层150(或150a)可包含一硅锗外延层，而适用于一PMOS晶体管，或者外延层150(或150a)可包含一硅碳外延层，而适用于一NMOS晶体管。接着再进行一离子注入制作工艺以注入适当的掺质，或者于进行外延成长步骤P5时，同时掺杂适当的掺质，如此，外延层150便可用以作为一源/漏极区(S/D)。在形成外延层150之后，可再进行一金属硅化物制作工艺(未绘示)，以在源/漏极中形成金属硅化物，其中金属硅化物制作工艺可包含前清洗制作工艺、金属沉积制作工艺、退火制作工艺、选择性蚀刻制作工艺及测试制作工艺等。当然，在进行金属硅化物制作工艺之后，可再进行其他后续制作工艺。
图10绘示本发明另外一实施例的剖视图。本实施例中，基底210上有多个鳍状结构214以及多个栅极结构230，每一个栅极结构230包含顶端的帽盖层236，间隙壁238位于栅极结构230两侧，另外在每一个栅极结构230的两侧都包含有各一外延层250。与图8Y方向的剖视图差异在于，本实施例中，因为制作工艺中可能产生的对准误差影响，因此栅极结构230与鳍状结构214的位置之间产生一错位，可能导致栅极结构230往某一特定方向偏移。因此，以任一鳍状结构214的中线M为对称轴，每一个鳍状结构214被栅极结构230以非对称的方式覆盖，换句话说，任一栅极结构230的中心到鳍状结构214左右两侧壁的水平距离分别为a、b，而本实施例中a、b的大小并不相同。在此情况下，特定的栅极结构230(尤其是位于边缘部分的栅极结构)其左右两边生长出的外延层250体积大小可能会不同。
除此之外，在完成栅极结构230之后，在利用蚀刻步骤蚀刻出外延层的凹槽过程中，将会先形成一光致抗蚀剂层(图未示)，而此光致抗蚀剂层可能有多个开口，各开口图案的宽度可略大于相邻的栅极结构230的间距，以利用栅极结构230的间隙壁238及/或帽盖层236进行自对准蚀刻。因此在上述过程中也可能一并移除部分的鳍状结构214侧壁，而使得鳍状结构214呈现一阶梯状的侧壁，进而从剖视图上看来，外延层250的也具有至少一阶梯状侧壁(如图10中的夹角t3)。另外，上述第一实施例也可能具有本实施例所述的外延层具有阶梯状侧壁的特征，在此不另外赘述。
本发明特征在于，在制作鳍状结构过程中，就已经先移除部分的鳍状结构，以预留后续制作外延层的生长区域。如此一来，可提升后续外延层制作的品质，进一步提高半导体结构的效能。此外，本发明的外延层同时接触多个鳍状结构，换句话说，同时形成多个晶体管的源/漏极区域，也进一步提高制作工艺的便利性。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体结构，包含:
基底，包含第一鳍状结构与第二鳍状结构，位于该基底上；
第一绝缘区，位于该第一鳍状结构与该第二鳍状结构之间；
第二绝缘区，位于该第一鳍状结构相对于该第一绝缘区另外一侧的基底中；以及
至少一外延层，位于该第一鳍状结构与该第二鳍状结构侧边，其中该外延层具有一底面，该底面至少从该第一鳍状结构延伸至该第二鳍状结构，且该底面低于该第一绝缘区的一底面以及该第二绝缘区的一顶面。
2.如权利要求1所述的半导体结构，还包含至少一栅极结构横跨该第一鳍状结构以及该第二鳍状结构。
3.如权利要求2所述的半导体结构，其中该栅极结构非对称覆盖部分该第一鳍状结构。
4.如权利要求2所述的半导体结构，其中至少一栅极结构其两侧都包含有该外延层，且该两外延层的体积大小不同。
5.如权利要求1所述的半导体结构，其中该第二绝缘区的深度大于该第一绝缘区的深度。
6.如权利要求1所述的半导体结构，其中该外延层的该底面为一平坦底面，且该外延层还包含两侧壁。
7.如权利要求6所述的半导体结构，其中该平坦底面以及该两侧壁的夹角大于90度。
8.如权利要求1所述的半导体结构，其中该外延层的底面具有一夹角。
9.如权利要求1所述的半导体结构，其中该外延层具有一阶梯状剖面侧壁。
10.一种半导体结构的形成方法，包含:
提供一基底，包含第一鳍状结构与第二鳍状结构位于该基底上；
形成一第一绝缘区，位于该第一鳍状结构与该第二鳍状结构之间；
形成一第二绝缘区，位于该第一鳍状结构相对于该第一绝缘层另外一侧的基底中；以及
形成至少一外延层，位于该第一鳍状结构与该第二鳍状结构侧边，其中该外延层具有一底面，该底面至少从该第一鳍状结构延伸至该第二鳍状结构，且该底面低于该第一绝缘区的一底面以及该第二绝缘区的一顶面。
11.如权利要求10所述的形成方法，其中形成该第一鳍状结构与该第二鳍状结构于该基底上的方法包含:
形成多个第三鳍状结构于该基底上；
形成一图案化硬掩模层于该基底上，并覆盖部分该第三鳍状结构；以及
进行一蚀刻步骤，将该移除部分该第三鳍状结构，部分剩余该第三鳍状结构定义为该第一鳍状结构与该第二鳍状结构。
12.如权利要求11所述的形成方法，还包含形成至少一栅极结构横跨该第一鳍状结构以及该第二鳍状结构。
13.如权利要求12所述的形成方法，其中上述形成该第一鳍状结构与该第二鳍状结构的步骤在该栅极结构形成之前。
14.如权利要求10所述的形成方法，其中该第一鳍状结构与该第二鳍状结构形成于该基底上之后，该第一绝缘区与该第二绝缘区才形成于该基底中。
15.如权利要求10所述的形成方法，其中该第二绝缘区的深度大于该第一绝缘区的深度。
16.如权利要求10所述的形成方法，其中该外延层的该底面为一平坦底面，并且该外延层还包含两侧壁。
17.如权利要求16所述的形成方法，其中该平坦底面以及该两侧壁的夹角大于90度。
18.如权利要求10所述的形成方法，其中该外延层的底面具有一夹角。
19.如权利要求10所述的形成方法，其中该栅极结构非对称覆盖部分该第一鳍状结构。
20.如权利要求10所述的形成方法，其中该外延层具有一阶梯状剖面侧壁。
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