TW559965B - Method of forming a bond pad and structure thereof - Google Patents
Method of forming a bond pad and structure thereof Download PDFInfo
- Publication number
- TW559965B TW559965B TW091120027A TW91120027A TW559965B TW 559965 B TW559965 B TW 559965B TW 091120027 A TW091120027 A TW 091120027A TW 91120027 A TW91120027 A TW 91120027A TW 559965 B TW559965 B TW 559965B
- Authority
- TW
- Taiwan
- Prior art keywords
- copper
- layer
- features
- dielectric layer
- height
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052802 copper Inorganic materials 0.000 claims abstract description 48
- 239000010949 copper Substances 0.000 claims abstract description 48
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 239000000523 sample Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910000831 Steel Inorganic materials 0.000 claims 2
- 239000010959 steel Substances 0.000 claims 2
- 230000007797 corrosion Effects 0.000 abstract description 16
- 238000005260 corrosion Methods 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000007788 liquid Substances 0.000 description 10
- 239000003112 inhibitor Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 230000004907 flux Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000013043 chemical agent Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 238000001467 acupuncture Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011819 refractory material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05546—Dual damascene structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
- H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/48847—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01007—Nitrogen [N]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01031—Gallium [Ga]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
559965 A7 ___ B7 五、發明説明(1 ) — 參考先前的申請 本申請書已經於2001年9月14日在美國提出,專利申請號 碼為 09/952,527 〇 ~ 發明的籤疇 本發明大體而言是有關半導體的範疇,而更特別的是有 關半導體的打線墊的範脅。 發明背景 在工業的半導體製程中,以銅取代移開的鋁,使一銅線 黏著附著在銅打線墊上是需要的。銅打線墊的問題為使用 化學機械拋光(CMP)時,會發生中間凹下。解決的方法是在 該銅打線墊中形成氧化物溝槽,以改善平坦化。然而,氧 化物溝槽難以確實地接觸具有探針縫合或線黏著的金屬。 若/又有溝槽’不只該CMP處理更困難,而且該探針縫合會 損宝又該打線塾’以至於危及線黏著的能力。因而,為了打 線塾的存在,需考慮溝槽的存在與銅線的線黏著,對銅打 線墊與探針縫合接觸的可靠程度。 圖示的簡述 以範例且不受限於附圖的方式說明本發明,其中相同的 參考符號表示類似的元件,而其中: 圖1說明根據本發明的實施例,陳列溝槽的部分半導體基 板的剖面圖; 圖2說明一部分具有形成一金屬層的圖丨的半導體基板; 圖3說明平坦化後,圖2的半導體基板; 圖4說明形成鈍化層後,圖3的半導體基板; -4-
559965 A7 _________B7 五、發明説明(2 ) 圖5說明圖樣化及姓刻該鈍化層後,圖4的半導體基板; 圖6說明形成一腐蝕障壁後,圖5的半導體基板; 圖7說明絲焊後的部分半導體基板;以及 圖8是根據本發明的實施例的打線墊的上視圖。 熟悉此技藝之人士會瞭解於圖中所說明的此些元件是為 了簡單清楚,因此不需要按比例繪製。例如,於圖中,相 對於其他的元件,加大若干元件的尺寸,以幫助促進對本 發明的實施例的瞭解。 詳述 於一實施例中,形成包括介電區與銅填充的溝槽打線墊 ,以改善銅線絲焊對銅打線墊與針探縫合的可靠程度。藉 由申請專利範圍,以及透過對參考附圖的較佳了解來闡述 本發明。 如圖1所顯示’在半導體基板1〇的表面上形成及圖樣化介 電層,以形成溝槽14與絕緣區12。於此所使用的名詞"基板 表面係用於指示基板10上的此些特徵頂的大部分曝露表 面。基板10為一直被製造的半導體基板,但不包括在最後 金屬層的後續處理期間所發生的形成打線墊。因此,基板 1 〇具有形成於其中的電晶體、位元線、字線等等。基板1 〇 具有一半導體層,例如石夕、鎵神化物、石夕鍺化物等等,而 且也包括一絕緣體,例如,矽絕緣體(S0I)。該介電層為最 後金屬層的介電層,而且能夠由化學氣相沉積(CVD)形成, 旋轉成類似的或上述的組合。該介電層為曝露在空氣中, 也幾乎完全不會起反應的介電材料,例如可以是四乙基氧 -5- 559965
石夕烧(TEOS)氣體。於實施例中,該介電層大約為〇」到工微 米的厚度。於實施例中,溝槽14與介於溝槽14間的通道9具 有相同的厚度’而另-實施例中,溝槽14的最大寬度不會 大於約4微米。於貫施例中,溝槽丨4為絕緣材料。溝槽的材 料與絕緣區12-樣是有好處的,因為只需要一沉積與一圖 樣化的處理步驟。如果溝槽14與絕緣區12為不同的材料, 沉積與圖樣化超過丨介電材料,對製造處理而言,會增加整 個製程的時間。 立形成溝槽14與絕緣區12之後,在該基板表面上形成第一 障壁層(未顯示),於實施例中,該第一障壁層為钽,由 形成大約400埃。其他耐火材料與其氮化物,例如TiN、Ti 與TaN,能夠被使用作為該第一障壁層。此外,也能夠使用 原子層沈積(ALD)或另外的方法。在該第一障壁層上形成一 種子層(未顯示)。於實施例中,該種子層為銅,由pvD形成 約800到1,500埃的厚度。 如圖2所顯不,在絕緣區12上及溝槽14之間與上面形成的 金屬層16,最好為銅。如果選擇使用該第一障壁層與該種 層’金屬層16也會覆蓋在其上。於實施例中,金屬層以為 一銅層與一銅填充,沉積在此些特徵或溝槽14之間及其上 。也可以使用其他有傳導性的材料,例如鎢與銅合金。以 電鍍或另一適合的處理形成金屬層16。所形成的金屬層16 的總量應該至少與通道9的高度一樣厚。於實施例中,沉積 8,000埃的銅。 形成金屬層16之後,例如以平坦化移除部分金屬層16 , -6- 本紙張尺度適财S 8家搮_(CNS) A4規格(2ι〇x 297公董) ------ 559965 A7 -_______Β7 五、發明説明(4 ) 以形成如圖3所顯示的鑲嵌結構18或金屬區18。通常,化學 機械拋光金屬層16 ,以產生金屬區18與溝槽14,一起形成 打線層1〇〇。此外,回蝕金屬層16以產生金屬區18。於該實 施例中,金屬層16為一銅層與一銅填充,平坦化該銅層與 銅填充,以形成幾乎完全平坦的表面,包括該銅填充的上 表面及所有溝槽14的上表面。金屬區18與溝槽14為打線墊 100或打線墊區100的一部分。 如圖4所顯示,形成打線墊1〇〇之後,在打線墊1〇〇與絕緣 區12上开> 成鈍化層2 〇。鈍化層2 〇可以為石夕氮化物、石夕氮氧 化物專4或其化合物,而且可以由cVD、PVD等等及其組 合所形成。已經發現500埃厚的矽氮化物與4,5〇〇埃厚的矽 氮氧化物可以作為鈍化層2〇。接著,用光抗蝕劑圖樣化鈍 化層20,並且蝕刻以形成通道9〇覆蓋在至少一部分打線墊 100上,如圖5所顯示。含氟的化學物質,例如夠被用 於蝕刻鈍化層20。於該實施例中,以蝕刻·ash•蝕刻處理形 成通道90,意指第一蝕刻,接著為ash,接著為第二蝕刻, 最好能或不能與第一蝕刻相同。也可以使用其他適合的方 法形成通道90。 於實施例中,形成第一蝕刻以形成部分通道9〇,並移除 δ亥第一姓刻所使用的光抗姓劑之後,在基板1 〇所有的區域 上’形成多硫亞氨層(未顯示),並圖樣化形成通道覆蓋打線 墊100與其他可能的區域。為了形成通道90的剩餘部分,實 行該第二蝕刻。可以使用或不使用於該第一蝕刻所使用的 同一蝕刻化學物質。該第二蝕刻處理會蝕刻該多硫亞氨層 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 559965 A7 _B7 五、發明説明(5 ) 未覆蓋的任何區域。 如圖5所顯示’當形成通道90,為了使溝槽μ凹進低於金 屬區1 8的上表面,實行由上往下的蝕刻,於實施例中為銅 填充。於該實施例中所呈現的鈍化層2〇 ,係由上往下姓刻 ,可以確保從通道90徹底移除鈍化層2〇,以提供給後續的 絲焊。該銅填充的高度大於眾多特徵或溝槽14的高度,而 凹處15形成在溝槽上,介於該溝槽的高度與該銅填充的高 度間。凹處15至少大約為100埃,而更特別的是大約為6〇〇 埃。熟悉此項技藝之人士能夠裁定,凹處丨5的深度不能大 於溝槽14的高度。於實施例中,凹處的總量介於大約1 〇〇埃 與2000埃之間,或者更特別的是介於大約600埃與2〇〇〇埃之 間。 希望凹處1 5夠深,使探針80能適用於一部分的打線墊1 〇〇 ’該探針將沿著溝槽14的上面滑動,而且與金屬區丨8接觸 ,如圖5所顯示《該凹處也能夠使任何增加在探針8〇上的殘 骸脫離且沉積在至少一凹處15,或者刮去在溝槽14上表面 的殘骸。此外,使用溝槽14,能阻止探針80與打線墊1 〇〇中 的金屬區18的底部接觸,並且能移除至少部分已接觸的金 屬區1 8,與先前技藝的案例一樣,未使用溝槽會導致較小 的絲焊接觸區。 由於該溝槽與金屬區是共面的,所以使用打線墊能夠防 止對該打線墊的穿透,以確保該探針與該金屬區之間的接 觸是足夠的。此外,此些溝槽與該探針的接觸會產生不傳 導的殘骸,會黏附在該探針的頂端,並增加打線墊的損毀 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A7
五、發明説明(6 或減少電接觸金屬區18的能力。 參考圖5,於實施例中,探針8〇直接與一部分的打線塾 100接觸,意指該探針不是經〇間層與打線墊⑽的部分 接觸 在形成凹處15之後,選擇性地形成第二障壁層22或腐蝕 障壁層22覆蓋在溝槽U與金屬區18上,保護打線墊1〇〇遠離 含氧或腐蝕的空氣。於實施例中,第二障壁層22為薄玻璃 材料,係由CVD或旋轉沉積。例如,第二障壁層22可以是 包括矽、碳、氧與氫的材料,例如與Kulicke & s〇ffa Industries Inc·的〇P2(SM)防止氧化處理聯合銷售的薄膜。 第二障壁層22的厚度小於凹處15的高度。於實施例中,第 二障壁層22小於大約100埃。 另一選擇,第二障壁層22可以為固體、膠體或液體形式 的腐蝕抗化劑。當使用液體的腐蝕抗化劑時,沉積該腐蝕 抗化劑,使至少部分填充凹處15覆蓋在溝槽14上。然而使 用液體的腐蝕抗化劑,凹處15能夠作為該液體的儲存槽, 而由於該液體與金屬區18的可濕性,會在整個期間釋放該 液體。因此,在整個期間以來自凹處15的液體腐蝕抗化劑 取代金屬區18上表面蒸發掉的腐蝕抗化劑,直到不再剩下 液體。各個凹處15所能容納的液體腐蝕抗化劑的總量為溝 槽14的凹處15的容積功能。較長的金屬區18需要被保護, 以遠離氧化環境,所以需要更多的液體腐蝕抗化劑,以及 較大的凹處15的容積。熟悉此項技藝之人士可依據凹處15 的高度,以及凹處15的直徑或寬度來識別凹處15的容積。 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A7 ___B7___ 五、發明説明(7 ) 於另一實施例中,第二障壁層22為助熔劑,可包括氣化 物或氟化物。通常,以蝕刻加熱移除該助熔劑。任何的腐 蝕會發生在金屬區18。後續該助熔劑蒸發掉或幾乎完全由 球體取代,在絲焊期間為線黏著的一部分,將在下面進一 步描述。 如果未形成第二障壁層22,在絲焊之前,於氮、氫、氬 或類似的環境中實行一標準的預清潔處理。另一選擇,隔 離通道90避免或最低限度地曝露於氧氣環境中。 形成打線墊1〇〇與第二障壁層22之後,假設希望,半導體 基板10係屬於一封裝基板(未顯示),而加熱係為了在半導體 基板10絲焊至少一打線墊1 〇〇,或者為了彼此間的電連接, 渴望在該封裝基板上有一墊。於實施例中,擠壓形成一金 屬線的線墊,而接著加熱在該線的末端形成一球狀體。接 著使用一鐵砧或環狀縫合清除打線墊1 〇〇的該球狀體與線β 藉由環狀縫合,超音波功率與壓力適用於線黏著24,適合 將線黏著24直接黏附在打線墊1 〇〇,意指該金屬線或線黏著 24不需經由中間層連接部分打線墊100。於一實施例中,該 金屬線或線黏著24直接附著在該銅填充的上表面,其中直 接與前面的陳述具有相同的意思。所產生的結構顯示於圖7 中。線黏著24可以為球狀體、楔形物或任何其他適合的形 狀。 如果使用第*一障壁層22’而且為腐蚀抗化劑,則僅出現 在絲焊之前或期間。另一選擇,如果使用助熔劑作為第二 障壁層22,該助熔劑可出現在絲焊之前、期間或之後。通 -10- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) 559965 A7 ____B7 五、發明説明(8 ) 常,於絲焊期間取代該助熔劑,而且加熱驅離該腐蝕抗化 劑。然而,如果使用玻璃作為第二障壁層22,該玻璃會在 絲焊之前及絲焊期間出現。於此實施例中,當線黏著24適 用於覆蓋第二障壁層22,第二障壁層22會在金屬區18的角 落裂開,而在整個期間第二障壁層22剩餘的部分會因金屬 區1 8或溝槽14而裂開分離β線黏著之後所完成的產品可能 沒有第二障壁層22,即使第二障壁層22使用於後續的處理 。因此,於一實施例中,在附著該金屬線的期間該金屬 線或線黏著24穿透第二障壁層22或腐蝕障壁層。於另一實 施例中,當附著該金屬線或線黏著24的期間,移除該腐蝕 障壁層或障壁層22。 於圖8中顯示打線墊100的構造圖,包括複數個特徵,以 及圍繞著眾多特徵的銅金屬層。於顯示的實施例中,所曝 路的溝槽14被金屬區1 8圍繞形成行列圖樣,也可以使用任 何其他的圖樣與任何數量的溝槽14 ^然而,金屬區丨8的區 域至少大約為打線墊1〇〇與線黏著24接觸的百分之三十四。 此外,溝槽14可以為任何的形狀,例如矩形、正方形或圓 柱形。 因為凹處1 5能增加探針與絲焊的可靠程度,形成凹陷有 溝槽的最後層的金屬打線墊是有利的,藉由化學機械拋光 ’而減少拋光成碟狀,以及控制探針80進入打線墊1〇〇的穿 透深度,因而,限制於針探期間損毁打線墊100。此些凹處 使探針80上所增加的任何殘骸,沉積在至少一凹處中,因 而清潔探針80。此外,多次重覆針探之後,凹處1 5容許剩 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
裝 訂
559965 A7 _____B7 五、發明説明(9 ) 餘金屬。針探之後,特別是多次重覆針探,剩餘的金屬能 增加絲焊處理的可靠程度及簡單性。另外,由於凹處15能 增加該金屬的表面區,對於由凹處15支援絲焊所產生的上 視圖,線黏著24能夠附著在金屬區18。再者,該上視圖考 慮將玻璃障壁層覆蓋在金屬區18之上,而使溝槽14更容易 破裂’提高黏著的強度與黏著的電接觸。 在則面的詳述中,已經以相關的特定實施例描述本發明 然而,熟悉此項技藝之人士應明白不需違背本發明如下 面的申請專利所提出的範圍,即可進行各種的改變與變化 。因此,本說明書與附圖係著重在說明,而沒有 思❶所有的此等改變希望包含於本發明的範圍内。 此等好處、其他優點與解決問題的方法已經在上面相關 的特定實施例中說明。然而,此等好處、優點、解決問題 的方法與任何元件不會被解釋為任何或所有申請專利範圍 的一緊要的、必要的或不可缺的特徵或元件,而該元件所 引起的任何好處、優點或解答,會發生或變得更明顯。如 於此所使用的,該名詞”包括”、,,組成,,或任何其它的變化, 希望涵蓋但不排除包括,因此包括一表列 法、技藝或裝置,不是只包括此些元件,而且=二 未特別列出或存在該處理、方法、技藝或裝置中的元件。 -12-
Claims (1)
- 559965 A B c D 夂、申請專利範圍 i 一種在半導體基板(ίο)上製造打線墊(1〇〇)的方法,包括: 在該半導體基板上形成一介電層(12); 圖樣化該介電層(12),於該介電層(12)的打線墊區中 形成複數個特徵(14); 沉積一銅層(16)於該等複數個特徵(14)之中的該介電 層(12),並沈積在該等複數個特徵(14)上; 回蝕該銅層(18)以容納一探針(80)後,化學機械拋光 該銅層(16)以形成一實質上平坦表面,其該平坦表面包 括該等複數個特徵(14)的曝露上方表面與該銅層(18)的 上方表面; 以回蝕該等複數個特徵(14)以在該回蝕鋼層中形成凹 處(15);以及 在該回蝕銅層上及該等凹處中鋪上一障壁層(22)。 2·如申請專利範圍第1項之方法,進一步包括: 在該半導體基板上形成一鈍化層(2〇);以及 回姓之前,形成至少部分通道(9〇)於該打線墊區上該 鈍化層(20)。 3·如申請專利範圍第2項之方法,進一步包括: 在該鈍化層上形成一多硫亞氨層;以及 回姓之前,形成至少部分通道於該打線墊區上的該鈍 化層。 4· 一種半導體基板製造方法,包括: 提供一半導體基板(10); 在該基板(10)上形成一介電層(12); -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A8 B8 C8 __ __D8 六、申請專利範圍~^ 一 '~一 姓刻該介電層(12),以在一打線墊區中形成複數個特 徵(14); 在該介電層(12)上沉積銅層(16),以在該介電層(12)上 形成一銅層(18),而且一銅填充(is)在該等特徵之間及 上面; 移除該銅層(16)之一部份與該銅填充(18),以形成一 實質上平坦表面,該平坦表面包括該銅填充(18)的上方 表面,以及各個特徵(14)的上方表面; 凹進的該等複數個特徵(14),以形成低於該銅填充 (18)上方表面的該等凹處(15);以及 將一金屬線(24)直接附著在該銅填充(18)的上方表面。 5. —種半導體結構製造的方法,包括·· 提供一半導體基板(10); 在該基板(10)上形成一介電層(12); 蝕刻該介電層(12),以在一打線墊區中形成複數個特 徵(14); 在該介電層(12)上沉積銅(16),以在該介電層(12)上形 成一銅層(16),而且一銅填充(18)在該等特徵(14)之間及 上面; 平坦化該銅層(16)與該銅填充(18),以形成一實質上 平坦表面,該平坦表面包括用於直接容納該探針(8〇)的 該銅填充(18)的上方表面與每個特徵(14)的上方表面; 以及 凹進該等複數個特徵(14),以形成低於該銅填充(18) -14- 本紙張尺度適用中國國家搮準(CNS) A4規格(210 X 297公釐) 訂559965 A8 B8 C8 —-—____D8 六、申請專利範園 的上方表面的該等凹處(15)。 6,如申請專利範圍第5項之方法,進一步包括使用一探針 (80)直接探測該銅填充(18)的上方表面。 7· 一種半導體結構,包括·· 一半導體基板(10); 一介電層(12),且覆蓋在該基板(1〇)上,並且具有沈 積於一打線墊區中的複數個特徵(14),其中該等特徵具 有一第一高度; 一位於該等特徵周圍的一銅填充(18),其延伸到一第 一兩度,其中該第二高度比第一高度高,藉此在該等特 徵上形成介於該第一高度與第二高度之間的該等凹處 (15); 一障壁層(22),其覆蓋在該銅填充(18)上且位於該等 凹處(15)中。 8 · 一種半導體結構,包括: 一半導體基板(10); 一介電層(12),其覆蓋在該基板(10)上,並且具有沈 積於一打線墊區中的複數個特徵(14),其中該等特徵具 有一第一高度; 一位於該等特徵周圍的一鋼填充(18),其延伸到一第 一同度’其中該第二高度比第一高度高,藉此在該等特 徵上形成’丨於該第一尚度與第二高度之間的該等凹 (15) 〇 -15-
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/952,527 US6531384B1 (en) | 2001-09-14 | 2001-09-14 | Method of forming a bond pad and structure thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
TW559965B true TW559965B (en) | 2003-11-01 |
Family
ID=25492992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091120027A TW559965B (en) | 2001-09-14 | 2002-09-03 | Method of forming a bond pad and structure thereof |
Country Status (8)
Country | Link |
---|---|
US (1) | US6531384B1 (zh) |
EP (1) | EP1430523A2 (zh) |
JP (1) | JP4451134B2 (zh) |
KR (1) | KR100896141B1 (zh) |
CN (1) | CN1296980C (zh) |
AU (1) | AU2002323303A1 (zh) |
TW (1) | TW559965B (zh) |
WO (1) | WO2003025998A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100448344B1 (ko) * | 2002-10-22 | 2004-09-13 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스케일 패키지 제조 방법 |
US7372153B2 (en) * | 2003-10-07 | 2008-05-13 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated circuit package bond pad having plurality of conductive members |
US7214605B2 (en) * | 2003-10-09 | 2007-05-08 | Intel Corporation | Deposition of diffusion barrier |
US7247564B2 (en) * | 2004-06-28 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Electronic device |
US7213329B2 (en) * | 2004-08-14 | 2007-05-08 | Samsung Electronics, Co., Ltd. | Method of forming a solder ball on a board and the board |
US7429795B2 (en) * | 2005-09-27 | 2008-09-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad structure |
KR100699865B1 (ko) * | 2005-09-28 | 2007-03-28 | 삼성전자주식회사 | 화학기계적 연마를 이용한 자기 정렬 콘택 패드 형성 방법 |
KR100699892B1 (ko) * | 2006-01-20 | 2007-03-28 | 삼성전자주식회사 | 솔더접합신뢰도 개선을 위한 락킹 구조를 갖는 반도체 소자및 인쇄회로기판 |
US7598620B2 (en) * | 2006-05-31 | 2009-10-06 | Hebert Francois | Copper bonding compatible bond pad structure and method |
WO2008015500A1 (en) * | 2006-08-01 | 2008-02-07 | Freescale Semiconductor, Inc. | Method and apparatus for improvements in chip manufacture and design |
US7812448B2 (en) * | 2006-08-07 | 2010-10-12 | Freescale Semiconductor, Inc. | Electronic device including a conductive stud over a bonding pad region |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
CN101675516B (zh) | 2007-03-05 | 2012-06-20 | 数字光学欧洲有限公司 | 具有通过过孔连接到前侧触头的后侧触头的芯片 |
US8134235B2 (en) | 2007-04-23 | 2012-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional semiconductor device |
KR101538648B1 (ko) | 2007-07-31 | 2015-07-22 | 인벤사스 코포레이션 | 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정 |
US7888257B2 (en) * | 2007-10-10 | 2011-02-15 | Agere Systems Inc. | Integrated circuit package including wire bonds |
EP2195837A1 (en) * | 2007-10-31 | 2010-06-16 | Agere Systems Inc. | Bond pad support structure for semiconductor device |
KR100933685B1 (ko) * | 2007-12-18 | 2009-12-23 | 주식회사 하이닉스반도체 | 필링 방지를 위한 본딩패드 및 그 형성 방법 |
US8053900B2 (en) * | 2008-10-21 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
KR20100060309A (ko) * | 2008-11-27 | 2010-06-07 | 주식회사 동부하이텍 | 반도체 소자 |
JP5353313B2 (ja) * | 2009-03-06 | 2013-11-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
US8259415B2 (en) * | 2009-06-22 | 2012-09-04 | Seagate Technology Llc | Slider bond pad with a recessed channel |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
JP5610905B2 (ja) * | 2010-08-02 | 2014-10-22 | パナソニック株式会社 | 半導体装置 |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
KR101059490B1 (ko) * | 2010-11-15 | 2011-08-25 | 테세라 리써치 엘엘씨 | 임베드된 트레이스에 의해 구성된 전도성 패드 |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
JP2012124452A (ja) * | 2010-12-06 | 2012-06-28 | Samsung Electro-Mechanics Co Ltd | プリント基板およびその製造方法 |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
CN102612262A (zh) * | 2011-01-18 | 2012-07-25 | 三星半导体(中国)研究开发有限公司 | 焊盘结构及其制造方法 |
US8314026B2 (en) | 2011-02-17 | 2012-11-20 | Freescale Semiconductor, Inc. | Anchored conductive via and method for forming |
US9177914B2 (en) * | 2012-11-15 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pad structure over TSV to reduce shorting of upper metal layer |
US9978637B2 (en) | 2013-10-11 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs) |
US20160093583A1 (en) | 2014-09-25 | 2016-03-31 | Micron Technology, Inc. | Bond pad with micro-protrusions for direct metallic bonding |
CN105742226B (zh) * | 2014-12-09 | 2019-05-21 | 中国科学院微电子研究所 | 半导体器件制造方法 |
US9960130B2 (en) * | 2015-02-06 | 2018-05-01 | UTAC Headquarters Pte. Ltd. | Reliable interconnect |
US9953940B2 (en) * | 2015-06-26 | 2018-04-24 | International Business Machines Corporation | Corrosion resistant aluminum bond pad structure |
CN108807320A (zh) * | 2018-06-01 | 2018-11-13 | 武汉新芯集成电路制造有限公司 | 芯片及键合垫的形成方法 |
KR20220083938A (ko) | 2020-12-11 | 2022-06-21 | 삼성디스플레이 주식회사 | 표시 장치 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH069200B2 (ja) * | 1987-03-31 | 1994-02-02 | 株式会社東芝 | 金属配線の形成方法 |
US5244534A (en) * | 1992-01-24 | 1993-09-14 | Micron Technology, Inc. | Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs |
US5382831A (en) | 1992-12-14 | 1995-01-17 | Digital Equipment Corporation | Integrated circuit metal film interconnect having enhanced resistance to electromigration |
JP2972484B2 (ja) * | 1993-05-10 | 1999-11-08 | 日本電気株式会社 | 半導体装置の製造方法 |
US5976971A (en) * | 1995-07-19 | 1999-11-02 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having an interconnection structure |
US5904563A (en) * | 1996-05-20 | 1999-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for metal alignment mark generation |
JP3526376B2 (ja) * | 1996-08-21 | 2004-05-10 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6114187A (en) * | 1997-01-11 | 2000-09-05 | Microfab Technologies, Inc. | Method for preparing a chip scale package and product produced by the method |
JP3031301B2 (ja) * | 1997-06-25 | 2000-04-10 | 日本電気株式会社 | 銅配線構造およびその製造方法 |
US6593241B1 (en) | 1998-05-11 | 2003-07-15 | Applied Materials Inc. | Method of planarizing a semiconductor device using a high density plasma system |
JP2002527886A (ja) * | 1998-10-05 | 2002-08-27 | キューリック、アンド、ソファー、インベストメンツ、インコーポレーテッド | 半導体の銅ボンドパッドの表面保護 |
US6306750B1 (en) * | 2000-01-18 | 2001-10-23 | Taiwan Semiconductor Manufacturing Company | Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability |
TW437030B (en) * | 2000-02-03 | 2001-05-28 | Taiwan Semiconductor Mfg | Bonding pad structure and method for making the same |
CN1314225A (zh) * | 2000-02-18 | 2001-09-26 | 德克萨斯仪器股份有限公司 | 铜镀层集成电路焊点的结构和方法 |
US6383935B1 (en) * | 2000-10-16 | 2002-05-07 | Taiwan Semiconductor Manufacturing Company | Method of reducing dishing and erosion using a sacrificial layer |
-
2001
- 2001-09-14 US US09/952,527 patent/US6531384B1/en not_active Expired - Lifetime
-
2002
- 2002-08-20 WO PCT/US2002/026607 patent/WO2003025998A2/en active Application Filing
- 2002-08-20 JP JP2003529519A patent/JP4451134B2/ja not_active Expired - Lifetime
- 2002-08-20 KR KR1020047003730A patent/KR100896141B1/ko active IP Right Grant
- 2002-08-20 AU AU2002323303A patent/AU2002323303A1/en not_active Abandoned
- 2002-08-20 EP EP02757276A patent/EP1430523A2/en not_active Withdrawn
- 2002-08-20 CN CNB028178254A patent/CN1296980C/zh not_active Expired - Lifetime
- 2002-09-03 TW TW091120027A patent/TW559965B/zh not_active IP Right Cessation
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8138079B2 (en) | 1998-12-21 | 2012-03-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US8021976B2 (en) | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US8026588B2 (en) | 2002-10-15 | 2011-09-27 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US8742580B2 (en) | 2002-10-15 | 2014-06-03 | Megit Acquisition Corp. | Method of wire bonding over active area of a semiconductor circuit |
US9142527B2 (en) | 2002-10-15 | 2015-09-22 | Qualcomm Incorporated | Method of wire bonding over active area of a semiconductor circuit |
US9153555B2 (en) | 2002-10-15 | 2015-10-06 | Qualcomm Incorporated | Method of wire bonding over active area of a semiconductor circuit |
Also Published As
Publication number | Publication date |
---|---|
US6531384B1 (en) | 2003-03-11 |
WO2003025998A2 (en) | 2003-03-27 |
WO2003025998A3 (en) | 2003-06-12 |
US20030054626A1 (en) | 2003-03-20 |
KR100896141B1 (ko) | 2009-05-12 |
CN1296980C (zh) | 2007-01-24 |
AU2002323303A1 (en) | 2003-04-01 |
JP2005522019A (ja) | 2005-07-21 |
JP4451134B2 (ja) | 2010-04-14 |
CN1554116A (zh) | 2004-12-08 |
EP1430523A2 (en) | 2004-06-23 |
KR20040035779A (ko) | 2004-04-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW559965B (en) | Method of forming a bond pad and structure thereof | |
TWI342588B (en) | Semiconductor device and manufacturing method of the same | |
KR100400037B1 (ko) | 콘택 플러그를 구비하는 반도체 소자 및 그의 제조 방법 | |
US6376353B1 (en) | Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects | |
TWI326360B (en) | Method of fabricating cantilever type probe and method of fabricating probe card using the same | |
TW200845173A (en) | Method of manufacturing a semiconductor device and a semiconductor manufacturing equipment | |
US6424021B1 (en) | Passivation method for copper process | |
US6200889B1 (en) | Semiconductor bonding pad | |
US6218732B1 (en) | Copper bond pad process | |
JP2000340569A (ja) | 半導体装置の配線構造及びその形成方法 | |
TWI244160B (en) | Method for manufacturing dual damascene structure with a trench formed first | |
US20090256217A1 (en) | Carbon nanotube memory cells having flat bottom electrode contact surface | |
KR20100070633A (ko) | 반도체 소자의 본딩 패드 구조 및 그의 제조방법 | |
KR101138113B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
JP4481065B2 (ja) | 半導体装置の製造方法 | |
KR100822916B1 (ko) | 반도체 장치 및 그 전기적 파라미터 테스트 방법 | |
CN107845605A (zh) | 半导体器件的制造方法 | |
KR100559037B1 (ko) | 금속배선 및 그의 형성방법 | |
JP2003031574A (ja) | 半導体装置およびその製造方法 | |
TW497213B (en) | Method for removing carbon-rich particles adhered on exposed copper surface of copper/low k dielectric dual damascene structure | |
JP2002110730A (ja) | ボンディングパッド及び半導体装置 | |
KR100268917B1 (ko) | 반도체소자의배선구조및배선형성방법 | |
KR20240115161A (ko) | 패드 산화 방지를 위한 캡 층 | |
TW461033B (en) | A reticular pad structure for removing cracks in inter-metal dielectrics on bonding pad and its fabrication | |
TW512449B (en) | Method to prevent defect formation in chemical mechanical polishing process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |