TW559965B - Method of forming a bond pad and structure thereof - Google Patents

Method of forming a bond pad and structure thereof Download PDF

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Publication number
TW559965B
TW559965B TW091120027A TW91120027A TW559965B TW 559965 B TW559965 B TW 559965B TW 091120027 A TW091120027 A TW 091120027A TW 91120027 A TW91120027 A TW 91120027A TW 559965 B TW559965 B TW 559965B
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TW
Taiwan
Prior art keywords
copper
layer
features
dielectric layer
height
Prior art date
Application number
TW091120027A
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English (en)
Inventor
Thomas S Kobayashi
Scott K Pozder
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Motorola Inc
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Publication of TW559965B publication Critical patent/TW559965B/zh

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    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

559965 A7 ___ B7 五、發明説明(1 ) — 參考先前的申請 本申請書已經於2001年9月14日在美國提出,專利申請號 碼為 09/952,527 〇 ~ 發明的籤疇 本發明大體而言是有關半導體的範疇,而更特別的是有 關半導體的打線墊的範脅。 發明背景 在工業的半導體製程中,以銅取代移開的鋁,使一銅線 黏著附著在銅打線墊上是需要的。銅打線墊的問題為使用 化學機械拋光(CMP)時,會發生中間凹下。解決的方法是在 該銅打線墊中形成氧化物溝槽,以改善平坦化。然而,氧 化物溝槽難以確實地接觸具有探針縫合或線黏著的金屬。 若/又有溝槽’不只該CMP處理更困難,而且該探針縫合會 損宝又該打線塾’以至於危及線黏著的能力。因而,為了打 線塾的存在,需考慮溝槽的存在與銅線的線黏著,對銅打 線墊與探針縫合接觸的可靠程度。 圖示的簡述 以範例且不受限於附圖的方式說明本發明,其中相同的 參考符號表示類似的元件,而其中: 圖1說明根據本發明的實施例,陳列溝槽的部分半導體基 板的剖面圖; 圖2說明一部分具有形成一金屬層的圖丨的半導體基板; 圖3說明平坦化後,圖2的半導體基板; 圖4說明形成鈍化層後,圖3的半導體基板; -4-
559965 A7 _________B7 五、發明説明(2 ) 圖5說明圖樣化及姓刻該鈍化層後,圖4的半導體基板; 圖6說明形成一腐蝕障壁後,圖5的半導體基板; 圖7說明絲焊後的部分半導體基板;以及 圖8是根據本發明的實施例的打線墊的上視圖。 熟悉此技藝之人士會瞭解於圖中所說明的此些元件是為 了簡單清楚,因此不需要按比例繪製。例如,於圖中,相 對於其他的元件,加大若干元件的尺寸,以幫助促進對本 發明的實施例的瞭解。 詳述 於一實施例中,形成包括介電區與銅填充的溝槽打線墊 ,以改善銅線絲焊對銅打線墊與針探縫合的可靠程度。藉 由申請專利範圍,以及透過對參考附圖的較佳了解來闡述 本發明。 如圖1所顯示’在半導體基板1〇的表面上形成及圖樣化介 電層,以形成溝槽14與絕緣區12。於此所使用的名詞"基板 表面係用於指示基板10上的此些特徵頂的大部分曝露表 面。基板10為一直被製造的半導體基板,但不包括在最後 金屬層的後續處理期間所發生的形成打線墊。因此,基板 1 〇具有形成於其中的電晶體、位元線、字線等等。基板1 〇 具有一半導體層,例如石夕、鎵神化物、石夕鍺化物等等,而 且也包括一絕緣體,例如,矽絕緣體(S0I)。該介電層為最 後金屬層的介電層,而且能夠由化學氣相沉積(CVD)形成, 旋轉成類似的或上述的組合。該介電層為曝露在空氣中, 也幾乎完全不會起反應的介電材料,例如可以是四乙基氧 -5- 559965
石夕烧(TEOS)氣體。於實施例中,該介電層大約為〇」到工微 米的厚度。於實施例中,溝槽14與介於溝槽14間的通道9具 有相同的厚度’而另-實施例中,溝槽14的最大寬度不會 大於約4微米。於貫施例中,溝槽丨4為絕緣材料。溝槽的材 料與絕緣區12-樣是有好處的,因為只需要一沉積與一圖 樣化的處理步驟。如果溝槽14與絕緣區12為不同的材料, 沉積與圖樣化超過丨介電材料,對製造處理而言,會增加整 個製程的時間。 立形成溝槽14與絕緣區12之後,在該基板表面上形成第一 障壁層(未顯示),於實施例中,該第一障壁層為钽,由 形成大約400埃。其他耐火材料與其氮化物,例如TiN、Ti 與TaN,能夠被使用作為該第一障壁層。此外,也能夠使用 原子層沈積(ALD)或另外的方法。在該第一障壁層上形成一 種子層(未顯示)。於實施例中,該種子層為銅,由pvD形成 約800到1,500埃的厚度。 如圖2所顯不,在絕緣區12上及溝槽14之間與上面形成的 金屬層16,最好為銅。如果選擇使用該第一障壁層與該種 層’金屬層16也會覆蓋在其上。於實施例中,金屬層以為 一銅層與一銅填充,沉積在此些特徵或溝槽14之間及其上 。也可以使用其他有傳導性的材料,例如鎢與銅合金。以 電鍍或另一適合的處理形成金屬層16。所形成的金屬層16 的總量應該至少與通道9的高度一樣厚。於實施例中,沉積 8,000埃的銅。 形成金屬層16之後,例如以平坦化移除部分金屬層16 , -6- 本紙張尺度適财S 8家搮_(CNS) A4規格(2ι〇x 297公董) ------ 559965 A7 -_______Β7 五、發明説明(4 ) 以形成如圖3所顯示的鑲嵌結構18或金屬區18。通常,化學 機械拋光金屬層16 ,以產生金屬區18與溝槽14,一起形成 打線層1〇〇。此外,回蝕金屬層16以產生金屬區18。於該實 施例中,金屬層16為一銅層與一銅填充,平坦化該銅層與 銅填充,以形成幾乎完全平坦的表面,包括該銅填充的上 表面及所有溝槽14的上表面。金屬區18與溝槽14為打線墊 100或打線墊區100的一部分。 如圖4所顯示,形成打線墊1〇〇之後,在打線墊1〇〇與絕緣 區12上开> 成鈍化層2 〇。鈍化層2 〇可以為石夕氮化物、石夕氮氧 化物專4或其化合物,而且可以由cVD、PVD等等及其組 合所形成。已經發現500埃厚的矽氮化物與4,5〇〇埃厚的矽 氮氧化物可以作為鈍化層2〇。接著,用光抗蝕劑圖樣化鈍 化層20,並且蝕刻以形成通道9〇覆蓋在至少一部分打線墊 100上,如圖5所顯示。含氟的化學物質,例如夠被用 於蝕刻鈍化層20。於該實施例中,以蝕刻·ash•蝕刻處理形 成通道90,意指第一蝕刻,接著為ash,接著為第二蝕刻, 最好能或不能與第一蝕刻相同。也可以使用其他適合的方 法形成通道90。 於實施例中,形成第一蝕刻以形成部分通道9〇,並移除 δ亥第一姓刻所使用的光抗姓劑之後,在基板1 〇所有的區域 上’形成多硫亞氨層(未顯示),並圖樣化形成通道覆蓋打線 墊100與其他可能的區域。為了形成通道90的剩餘部分,實 行該第二蝕刻。可以使用或不使用於該第一蝕刻所使用的 同一蝕刻化學物質。該第二蝕刻處理會蝕刻該多硫亞氨層 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 559965 A7 _B7 五、發明説明(5 ) 未覆蓋的任何區域。 如圖5所顯示’當形成通道90,為了使溝槽μ凹進低於金 屬區1 8的上表面,實行由上往下的蝕刻,於實施例中為銅 填充。於該實施例中所呈現的鈍化層2〇 ,係由上往下姓刻 ,可以確保從通道90徹底移除鈍化層2〇,以提供給後續的 絲焊。該銅填充的高度大於眾多特徵或溝槽14的高度,而 凹處15形成在溝槽上,介於該溝槽的高度與該銅填充的高 度間。凹處15至少大約為100埃,而更特別的是大約為6〇〇 埃。熟悉此項技藝之人士能夠裁定,凹處丨5的深度不能大 於溝槽14的高度。於實施例中,凹處的總量介於大約1 〇〇埃 與2000埃之間,或者更特別的是介於大約600埃與2〇〇〇埃之 間。 希望凹處1 5夠深,使探針80能適用於一部分的打線墊1 〇〇 ’該探針將沿著溝槽14的上面滑動,而且與金屬區丨8接觸 ,如圖5所顯示《該凹處也能夠使任何增加在探針8〇上的殘 骸脫離且沉積在至少一凹處15,或者刮去在溝槽14上表面 的殘骸。此外,使用溝槽14,能阻止探針80與打線墊1 〇〇中 的金屬區18的底部接觸,並且能移除至少部分已接觸的金 屬區1 8,與先前技藝的案例一樣,未使用溝槽會導致較小 的絲焊接觸區。 由於該溝槽與金屬區是共面的,所以使用打線墊能夠防 止對該打線墊的穿透,以確保該探針與該金屬區之間的接 觸是足夠的。此外,此些溝槽與該探針的接觸會產生不傳 導的殘骸,會黏附在該探針的頂端,並增加打線墊的損毀 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A7
五、發明説明(6 或減少電接觸金屬區18的能力。 參考圖5,於實施例中,探針8〇直接與一部分的打線塾 100接觸,意指該探針不是經〇間層與打線墊⑽的部分 接觸 在形成凹處15之後,選擇性地形成第二障壁層22或腐蝕 障壁層22覆蓋在溝槽U與金屬區18上,保護打線墊1〇〇遠離 含氧或腐蝕的空氣。於實施例中,第二障壁層22為薄玻璃 材料,係由CVD或旋轉沉積。例如,第二障壁層22可以是 包括矽、碳、氧與氫的材料,例如與Kulicke & s〇ffa Industries Inc·的〇P2(SM)防止氧化處理聯合銷售的薄膜。 第二障壁層22的厚度小於凹處15的高度。於實施例中,第 二障壁層22小於大約100埃。 另一選擇,第二障壁層22可以為固體、膠體或液體形式 的腐蝕抗化劑。當使用液體的腐蝕抗化劑時,沉積該腐蝕 抗化劑,使至少部分填充凹處15覆蓋在溝槽14上。然而使 用液體的腐蝕抗化劑,凹處15能夠作為該液體的儲存槽, 而由於該液體與金屬區18的可濕性,會在整個期間釋放該 液體。因此,在整個期間以來自凹處15的液體腐蝕抗化劑 取代金屬區18上表面蒸發掉的腐蝕抗化劑,直到不再剩下 液體。各個凹處15所能容納的液體腐蝕抗化劑的總量為溝 槽14的凹處15的容積功能。較長的金屬區18需要被保護, 以遠離氧化環境,所以需要更多的液體腐蝕抗化劑,以及 較大的凹處15的容積。熟悉此項技藝之人士可依據凹處15 的高度,以及凹處15的直徑或寬度來識別凹處15的容積。 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A7 ___B7___ 五、發明説明(7 ) 於另一實施例中,第二障壁層22為助熔劑,可包括氣化 物或氟化物。通常,以蝕刻加熱移除該助熔劑。任何的腐 蝕會發生在金屬區18。後續該助熔劑蒸發掉或幾乎完全由 球體取代,在絲焊期間為線黏著的一部分,將在下面進一 步描述。 如果未形成第二障壁層22,在絲焊之前,於氮、氫、氬 或類似的環境中實行一標準的預清潔處理。另一選擇,隔 離通道90避免或最低限度地曝露於氧氣環境中。 形成打線墊1〇〇與第二障壁層22之後,假設希望,半導體 基板10係屬於一封裝基板(未顯示),而加熱係為了在半導體 基板10絲焊至少一打線墊1 〇〇,或者為了彼此間的電連接, 渴望在該封裝基板上有一墊。於實施例中,擠壓形成一金 屬線的線墊,而接著加熱在該線的末端形成一球狀體。接 著使用一鐵砧或環狀縫合清除打線墊1 〇〇的該球狀體與線β 藉由環狀縫合,超音波功率與壓力適用於線黏著24,適合 將線黏著24直接黏附在打線墊1 〇〇,意指該金屬線或線黏著 24不需經由中間層連接部分打線墊100。於一實施例中,該 金屬線或線黏著24直接附著在該銅填充的上表面,其中直 接與前面的陳述具有相同的意思。所產生的結構顯示於圖7 中。線黏著24可以為球狀體、楔形物或任何其他適合的形 狀。 如果使用第*一障壁層22’而且為腐蚀抗化劑,則僅出現 在絲焊之前或期間。另一選擇,如果使用助熔劑作為第二 障壁層22,該助熔劑可出現在絲焊之前、期間或之後。通 -10- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) 559965 A7 ____B7 五、發明説明(8 ) 常,於絲焊期間取代該助熔劑,而且加熱驅離該腐蝕抗化 劑。然而,如果使用玻璃作為第二障壁層22,該玻璃會在 絲焊之前及絲焊期間出現。於此實施例中,當線黏著24適 用於覆蓋第二障壁層22,第二障壁層22會在金屬區18的角 落裂開,而在整個期間第二障壁層22剩餘的部分會因金屬 區1 8或溝槽14而裂開分離β線黏著之後所完成的產品可能 沒有第二障壁層22,即使第二障壁層22使用於後續的處理 。因此,於一實施例中,在附著該金屬線的期間該金屬 線或線黏著24穿透第二障壁層22或腐蝕障壁層。於另一實 施例中,當附著該金屬線或線黏著24的期間,移除該腐蝕 障壁層或障壁層22。 於圖8中顯示打線墊100的構造圖,包括複數個特徵,以 及圍繞著眾多特徵的銅金屬層。於顯示的實施例中,所曝 路的溝槽14被金屬區1 8圍繞形成行列圖樣,也可以使用任 何其他的圖樣與任何數量的溝槽14 ^然而,金屬區丨8的區 域至少大約為打線墊1〇〇與線黏著24接觸的百分之三十四。 此外,溝槽14可以為任何的形狀,例如矩形、正方形或圓 柱形。 因為凹處1 5能增加探針與絲焊的可靠程度,形成凹陷有 溝槽的最後層的金屬打線墊是有利的,藉由化學機械拋光 ’而減少拋光成碟狀,以及控制探針80進入打線墊1〇〇的穿 透深度,因而,限制於針探期間損毁打線墊100。此些凹處 使探針80上所增加的任何殘骸,沉積在至少一凹處中,因 而清潔探針80。此外,多次重覆針探之後,凹處1 5容許剩 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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559965 A7 _____B7 五、發明説明(9 ) 餘金屬。針探之後,特別是多次重覆針探,剩餘的金屬能 增加絲焊處理的可靠程度及簡單性。另外,由於凹處15能 增加該金屬的表面區,對於由凹處15支援絲焊所產生的上 視圖,線黏著24能夠附著在金屬區18。再者,該上視圖考 慮將玻璃障壁層覆蓋在金屬區18之上,而使溝槽14更容易 破裂’提高黏著的強度與黏著的電接觸。 在則面的詳述中,已經以相關的特定實施例描述本發明 然而,熟悉此項技藝之人士應明白不需違背本發明如下 面的申請專利所提出的範圍,即可進行各種的改變與變化 。因此,本說明書與附圖係著重在說明,而沒有 思❶所有的此等改變希望包含於本發明的範圍内。 此等好處、其他優點與解決問題的方法已經在上面相關 的特定實施例中說明。然而,此等好處、優點、解決問題 的方法與任何元件不會被解釋為任何或所有申請專利範圍 的一緊要的、必要的或不可缺的特徵或元件,而該元件所 引起的任何好處、優點或解答,會發生或變得更明顯。如 於此所使用的,該名詞”包括”、,,組成,,或任何其它的變化, 希望涵蓋但不排除包括,因此包括一表列 法、技藝或裝置,不是只包括此些元件,而且=二 未特別列出或存在該處理、方法、技藝或裝置中的元件。 -12-

Claims (1)

  1. 559965 A B c D 夂、申請專利範圍 i 一種在半導體基板(ίο)上製造打線墊(1〇〇)的方法,包括: 在該半導體基板上形成一介電層(12); 圖樣化該介電層(12),於該介電層(12)的打線墊區中 形成複數個特徵(14); 沉積一銅層(16)於該等複數個特徵(14)之中的該介電 層(12),並沈積在該等複數個特徵(14)上; 回蝕該銅層(18)以容納一探針(80)後,化學機械拋光 該銅層(16)以形成一實質上平坦表面,其該平坦表面包 括該等複數個特徵(14)的曝露上方表面與該銅層(18)的 上方表面; 以回蝕該等複數個特徵(14)以在該回蝕鋼層中形成凹 處(15);以及 在該回蝕銅層上及該等凹處中鋪上一障壁層(22)。 2·如申請專利範圍第1項之方法,進一步包括: 在該半導體基板上形成一鈍化層(2〇);以及 回姓之前,形成至少部分通道(9〇)於該打線墊區上該 鈍化層(20)。 3·如申請專利範圍第2項之方法,進一步包括: 在該鈍化層上形成一多硫亞氨層;以及 回姓之前,形成至少部分通道於該打線墊區上的該鈍 化層。 4· 一種半導體基板製造方法,包括: 提供一半導體基板(10); 在該基板(10)上形成一介電層(12); -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 559965 A8 B8 C8 __ __D8 六、申請專利範圍~^ 一 '~一 姓刻該介電層(12),以在一打線墊區中形成複數個特 徵(14); 在該介電層(12)上沉積銅層(16),以在該介電層(12)上 形成一銅層(18),而且一銅填充(is)在該等特徵之間及 上面; 移除該銅層(16)之一部份與該銅填充(18),以形成一 實質上平坦表面,該平坦表面包括該銅填充(18)的上方 表面,以及各個特徵(14)的上方表面; 凹進的該等複數個特徵(14),以形成低於該銅填充 (18)上方表面的該等凹處(15);以及 將一金屬線(24)直接附著在該銅填充(18)的上方表面。 5. —種半導體結構製造的方法,包括·· 提供一半導體基板(10); 在該基板(10)上形成一介電層(12); 蝕刻該介電層(12),以在一打線墊區中形成複數個特 徵(14); 在該介電層(12)上沉積銅(16),以在該介電層(12)上形 成一銅層(16),而且一銅填充(18)在該等特徵(14)之間及 上面; 平坦化該銅層(16)與該銅填充(18),以形成一實質上 平坦表面,該平坦表面包括用於直接容納該探針(8〇)的 該銅填充(18)的上方表面與每個特徵(14)的上方表面; 以及 凹進該等複數個特徵(14),以形成低於該銅填充(18) -14- 本紙張尺度適用中國國家搮準(CNS) A4規格(210 X 297公釐) 訂
    559965 A8 B8 C8 —-—____D8 六、申請專利範園 的上方表面的該等凹處(15)。 6,如申請專利範圍第5項之方法,進一步包括使用一探針 (80)直接探測該銅填充(18)的上方表面。 7· 一種半導體結構,包括·· 一半導體基板(10); 一介電層(12),且覆蓋在該基板(1〇)上,並且具有沈 積於一打線墊區中的複數個特徵(14),其中該等特徵具 有一第一高度; 一位於該等特徵周圍的一銅填充(18),其延伸到一第 一兩度,其中該第二高度比第一高度高,藉此在該等特 徵上形成介於該第一高度與第二高度之間的該等凹處 (15); 一障壁層(22),其覆蓋在該銅填充(18)上且位於該等 凹處(15)中。 8 · 一種半導體結構,包括: 一半導體基板(10); 一介電層(12),其覆蓋在該基板(10)上,並且具有沈 積於一打線墊區中的複數個特徵(14),其中該等特徵具 有一第一高度; 一位於該等特徵周圍的一鋼填充(18),其延伸到一第 一同度’其中該第二高度比第一高度高,藉此在該等特 徵上形成’丨於該第一尚度與第二高度之間的該等凹 (15) 〇 -15-
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KR100896141B1 (ko) 2009-05-12
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