TW512449B - Method to prevent defect formation in chemical mechanical polishing process - Google Patents

Abstract

This invention provides a method to prevent defect formation in chemical mechanical polishing (CMP) process, which includes following steps: sequentially forming a first dielectric layer and a second dielectric layer on a semiconductor substrate, in which the wet etching rate of the first dielectric layer is greater than that of the second dielectric layer; performing a dry etching process to from a plural number of the first holes in a plural number of the predetermined contact regions individually, in which every first hole penetrates the second dielectric layer and reaches a predetermined depth of the first dielectric layer; performing a wet etching process to achieve a predetermined lateral width in the first dielectric layer for the first hole; forming a plural number of the second holes in a plural number of predetermined contact regions, in which the ratio of the opening diameter of the second hole to the diameter of the predetermined contact region is less than 0.55 and the opening diameter of the second hole is smaller than the bottom diameter of the second hole; forming a conductive layer on the surface of the semiconductor substrate to fully fill every second hole; and performing a CMP process to remove part of the conductive layer so that the surface of the conductive layer is on the same plane as that of the surface of the second dielectric layer.

Description

i. The invention relates to a chemical mechanical polishing (ch㈣ica; lfflechanicai P ^ nbhing (CMP)) process applied to wire metal inlay j, amascene) technology, and in particular to a method that can prevent the ACMp process from generating dishing and Erosion method.

In the metal wire process, when applied to the logic element process and the contact window process of the upper and lower layers, the chemical mechanical polishing j viheEliCai ® mechanical polishing (CMP) method is used to planarize the metal conductor. The damascene technology 5 currently used is to fill the metal into the contact window of the insulating layer, and then use the CMP process to remove the metal outside the contact window, so that the metal shape is buried in the insulating layer. However, during the polishing process, the pressure transmitted by the polishing pad will be shared by the bumps on the surface of the wafer. Therefore, depending on the density and area of the metal wire, the degree of polishing will be different. In general, when an insulating layer with a large j-area area is used as a polishing stop layer, a better polishing effect will be obtained. 'However, when the area ratio of the metal wire to the insulating layer is too large, over-polising is liable to occur.

The degree of excessive polishing depends not only on the elasticity of the polishing pad and the chemical properties of the polishing liquid, but also on the density and size of the metal wire pattern. Please refer to the first figure, which shows that when the CMP process is performed on the metal wires 2 with a high density (more than 50%) distribution, the surface area of the insulating layer 1 is too small, which will lead to excessive grinding, which will cause erosion of reduced thickness. ) Phenomenon, so the surface result after CMP will be shown as dotted line 3. Please refer to the second figure, which shows that after a large area of the metal wire 5 is rapidly ground, the metal wire 5 and the insulating material 4 are removed at different rates, so the metal wire

〇593o795TW.ptd Page 5 512449 V. Description of the invention (2) The central area of 5 will produce a dish-like & u., Slab-like depression, this phenomenon is commonly called concave hUishing), so the surface after CMP The result is shown in dotted line 6. If a soft polishing pad is used, the dent will be more pronounced.

Make the mouth: Here, the main purpose of the present invention is to propose a method to prevent the CMP clothing from sinking and erosion to solve the conventional problems. The present invention: a method for preventing erosion in a CMP process is provided, which includes the following steps: firstly forming a first dielectric layer and a second dielectric layer on the surface of a semiconductor substrate;丨 Female W Xiyan-The first wet etching rate of the first dielectric layer of Renminbi M is the eight-bed wet-wet etch rate; a dry-name engraving process is performed in order to form a plurality of firsts in a plurality of predetermined contact window areas. Holes ... The mother-brother-hole system runs through the second dielectric layer until the first: a predetermined depth; a wet etching is performed. # — 结 人; β ~ clothing ^, the A predetermined transverse width to form a plurality of second holes in the plurality of pre-touch areas, wherein the ratio of the second hole and the opening diameter i of the second hole is less than 0.55, and the ratio is less than the The diameter of the bottom of the second hole is long; 2-a conductive layer is formed on the bottom surface, and it is filled up to the first material channel = = to remove a part of the conductive layer so that the surface of the conductive layer and the second dielectric The surface of the electrical layer is cut evenly. Ben Meming proposed a method to prevent the CMP process from generating depressions, including the following steps: sequentially in half of the dome] Wan electric layer and a second dielectric layer, 1: ;; substrate, surface formation-the first-dielectric greater than the second The dielectric- " wet etch rate of the electrical layer is based on the predetermined metal wire area ^ 2 = xetching, and several first holes are attacked in the form of iodine, each of which is 512449. 5. Description of the invention (3) The first hole passes through the second dielectric layer to a first predetermined depth of the first dielectric layer; a wet etching process is performed to etch the first dielectric layer in each first hole to a second A predetermined depth, and completely removing the first dielectric layer between adjacent first holes to form a second hole penetrating the plurality of first holes in the predetermined metal wire region; on the surface of the semiconductor substrate Forming a conductive layer and filling the second hole; and performing a CMP process to remove a portion of the conductive layer so that the surface of the conductive layer is aligned with the surface of the second dielectric layer. Brief Description of the Drawings Figure 1 shows the invasion of high-density metal wires caused by excessive grinding. Figure 2 shows the pitting of a large area of metal wire caused by excessive grinding. Figures 3A to 3E show a method for preventing a CMP process from generating a backlash phenomenon in the first embodiment of the present invention. Figures 4A to 4E show a method for preventing the CMP process from generating a sinking phenomenon in the second embodiment of the present invention. [Explanation of symbols] Plane contact window area ~ 12; First dielectric layer ~ 14, 34; First hole ~ 18, 3 8; Conductive layer ~ 2 2, 4 2; Semiconductor substrate ~ 10, 30; Plane metal wire Area ~ 32; Second dielectric layer ~ 16, 36; Second hole ~ 20, 40; Metal wire ~ 24,44. [First embodiment]

0593-5795TW.ptd Page 7 512449 V. Description of the invention (4) The first embodiment of the present invention provides a method to prevent the cMp process from eroding. It can be used to meet the high density (more than 50%) metal. The connection of the wire is in the process of clothing. Please refer to FIGS. 3A to 3B, which show the first embodiment of the present invention, the method for preventing erosion in the CMP process. As shown in FIG. 3A, a plurality of predetermined contact window regions 12 5 are defined on the surface of the two-body substrate 10. The arrangement density of the predetermined contact window regions 12 is greater than 50%. The first sequence is formed on the surface of the semiconductor substrate 10—the first dielectric layer 14 and the first and second electrical layers 16, where the wet etching rate of the first dielectric layer 14 must be greater than the wet #etching rate of an electric layer 16 . The preferred method of use of the present invention is to control the wet-etching rate ratio of the first dielectric layer Ϊ4 and the second dielectric layer 16 to • 1, so one way is to use borophosphosilicate glass “with ㈧ as the first electrical layer 14 And a silane oxide (silane oxide) is used as the dielectric layer 16; another method is to use an oxide as the first dielectric layer 14 ′ and a nitride as the second dielectric layer μ. As shown in FIG. 3B, a first contact hole 18 is defined and formed in a predetermined contact window area 12 using a lithography process and a dry process process. Each first hole 18 penetrates the second dielectric layer 16 to the first dielectric layer. η — predetermined depth (referring to the exposure of the underlying conductive material): As shown in Figure 3C, the iron undergoes a wet engraving process to insert the first hole i8 '

The second dielectric layer 16 and the first dielectric layer 14 are etched until—a predetermined lateral width, 2 are formed in each of the predetermined contact window regions 12—a second hole, ^ 20. Since the first dielectric layer 14 and the first The wet etching rate ratio of the second dielectric layer 16 is ^ ° · 1, and the first dielectric layer η and the second dielectric layer are engraved laterally at a rate of 3: 1. Therefore, the opening diameter dl of the second hole 20 will be Less than the bottom ^ Long⑽〗 About 0593-5795TW.ptd V. Description of the invention (5) Equal to the diameter of the predetermined contact window) 'i The diameter of the predetermined contact window area in the second hole 2 is best controlled. Marriage! Γ ° As shown in FIG. 3D, a conductive layer 22 is formed on the surface of the semiconductor substrate 10, and each of the second holes 20 is filled. The conductive layer 22 may be composed of a titanium nitride / titanium layer and a metallic layer. Finally, as shown in the first paragraph, 'C-MP; MP process, remove part of the conductive layer 22 until the surface of the second dielectric layer 16 is exposed, so that the surface of the remaining conductive layer 22 and the first dielectric layer The surface of the electrical layer 16 is cut into a line, and a plurality of high-density metal wires 24 are manufactured. Since the ratio of the opening diameter of the second hole 20 to the diameter length D of the predetermined contact window area 12 is controlled to be less than 55%, the separation distance of the conductive layer 22 on the surface of the second dielectric layer 16 can be effectively increased, so that Avoiding the CMP process from over-grinding the second dielectric layer 16, thereby preventing the conventional technology from generating a corrosion phenomenon. In addition, another wet etching process may be continued to completely remove the second dielectric layer 16 until the surface of the first dielectric layer 14 is exposed. [Second Embodiment] The second embodiment of the present invention proposes a method for preventing the occurrence of the sag phenomenon in the CMP process, which can be applied to a metal wire process with a large area, such as making a bond pad, a wire, and the like. Please refer to the 4th to 45th people: FIG. 4, which shows a pimple prevention according to the second embodiment of the present invention? Method of producing sinking phenomenon | As shown in FIG. 4A, a predetermined metal wire region 32 is defined on the surface of a semiconductor substrate 30. First, a first dielectric layer 34 and a second dielectric layer 36 are sequentially formed on the surface of the semiconductor substrate 30. The first dielectric layer 34

0593-5795TW.ptd Page 9 512449 I. Explanation of the Invention (6)!

The wet etching rate of .-. I must be greater than the wet etching rate of the second dielectric layer 36. This invention | The preferred method of use is to control the wet money engraving rate ratio of the first dielectric layer 34 and the second dielectric layer 36 to 3: 1, so one way is to use borophosphosilicate glass (BPSG) as the first Dielectric layer 34, and the use of silane oxide (Csi lane oxide) as the second dielectric layer 36; Another way is to use | oxide as the first dielectric layer 34, and use nitride as the second dielectric i 电 层 36。 Electrical layer 36. As shown in FIG. 4B, a lithography process and a dry etching process are used to define a plurality of disconnected first holes 38 in a predetermined metal wire area 32, and each first hole 38 passes through the second interface. The electrical layer 36 and the first dielectric layer 4 3 4 reach a first predetermined depth h 1. Compared with the dry-etching process 5 of the first hole 18 of the first embodiment, the dry-etching process of the second embodiment can etch only the first dielectric layer 34 to a first predetermined time by shortening the dry-etching time. Depth h 1 to form a shallower first hole 38. Then, as shown in Figures 4C and 4C (Figure 4C is a schematic cross-sectional view taken along the tangent line 4-4 of Figure 4C '), a wet-relief process is performed to place the first part in each first hole 38. A dielectric layer 34 is etched to a predetermined lateral width and a second predetermined depth h2 (referring to the ability to expose the conductive material of the lower layer). The important point of the second embodiment is that the wet-money engraving rate ratio of the first dielectric layer 34 and the second dielectric layer 36 is about 3: 1, and by appropriately increasing the wet etching time, it is possible to The first dielectric layer 314 is etched in a large amount until the first dielectric layer 34 between adjacent first holes 38 is completely removed to penetrate all the bottom areas of the first holes 38, and the A second hole 40 is formed in the region 32. In this way, the diameter 4 of the bottom of the second hole 40 is approximately equal to the diameter D of the predetermined metal wire region 32, to

Page 10 512449 Five 'Explanation of the invention (7) In the second, the surface of the hole 40 contains a plurality of openings a. As shown in FIG. 4D, a conductive layer 4 2 ′ is formed on the surface of the semiconductor substrate 30 and the second hole 40 is filled. Among them, the conductive layer 42 may be composed of a nitride layer, a layer, and a metal tungsten / copper layer. Finally, as shown in FIG. 4E, a CMP process is performed on the dysprosium f42, and a part of the conductive layer 42 is removed until the surface 5 of the second dielectric layer 46 is exposed to expose the surface of the conductive layer 42 and the dielectric. The surface of the layer 46 is cut to make a large area of gold & wire 4 A. Since the surface of the first hole 40 contains a plurality of openings ^ θ, the conductive layer 42 on the surface of the second dielectric layer 46 can be made. Distributed into a plurality of small area areas, it is possible to avoid the CMP process to directly grind the electrical layer 4 2 ′ outside the large area area, thereby preventing the depression phenomenon caused by the conventional technology. In addition to this, another wet etching process may be continued, and the second dielectric layer 46 is finished until the surface of the first dielectric layer 44 is exposed.么 # ^ The car used conventional techniques to use different polishing pads, polishing liquids, and grinders to improve the endpoint detection method to prevent defects in the CMP process. Wen Shan, increasing the pattern density of :: 22, 42 on the surfaces of the second dielectric layers 16, 46 to prevent t μ Γ and the dry resistance transmitted by the polishing pad from maintaining the shear resistance can effectively improve CMP. Erosion or depression caused by the process. To the limit, the invention has been disclosed as above with a preferred embodiment, but it is not explained by gods. Anyone skilled in this art can make some changes and modifications without departing from the scope of the present invention. So, the Baotian of this invention? . The appended application patent shall prevail.

Claims (1)

6. Applying for a patent ^ ~ *-*-1 · ^ Polish · A method for preventing defects in the chemical mechanical polishing (& χ1η ^ CMP) process, including the following steps: A contact window is provided for a semiconductor substrate, and its surface A plurality of predetermined 1 domains A > | T \ | A second sequence is formed on the surface of the semiconductor substrate to form a first dielectric layer and a 箆 -eight ^ electrical layer. The wet engraving rate is greater than the wet etching rate of the 1M electrical layer of the brother; C c), in the window area, a line, a, and a dry etching process are performed in order to make contact with the plurality of predetermined contacts — > into a plurality of A first hole, wherein each of the first holes penetrates the μ dielectric layer up to a predetermined depth of the first dielectric layer; _ Rudi j) perform a wet etching process, the The first total width d is a predetermined width, so as to form a plurality of second holes in the plurality of predetermined contact areas respectively; (e) forming a conductive layer on the surface of the semiconductor substrate and filling it with each A second hole; and ^ performing a CMP process, Removing the conductive layer to make the surface electrically conductive layer and the surface of the second dielectric layer cut flush. 2. The method according to item 1 of the scope of patent application, wherein the ratio of the opening diameter of the second hole to the diameter length of the predetermined contact window area is less than 0 · υ 3 'and the opening diameter of the second hole is less than The bottom diameter of the second hole is _ long. 3. The method according to item 1 of the scope of patent application, wherein the wet etching rate ratio of the first dielectric layer to the second dielectric layer is not less than 3. 4. The method according to item 3 of the scope of patent application, wherein the first introduction 512449 6. Scope of patent application The electrical layer is composed of rotten glass fiber (BPSG), and the second dielectric layer is composed of silane oxide (e oxide). 5. The method of claim 3, wherein the first dielectric layer is composed of an oxide, and the second dielectric layer is composed of a nitride. 6. The method according to item 1 of the Chinese Patent Application, wherein the length of the bottom of the second hole is the same as the diameter of the predetermined contact window. 7. The method as described in item 1 of the patent scope, wherein after performing the CMP process, another wet etching process may be performed to remove the second dielectric layer on the surface of the semiconductor substrate. 8 * Methods for preventing defects in the chemical mechanical polishing (CMP) process, including the following steps: (a) providing a semiconductor substrate with a predetermined metal wire region defined on the surface; ^ (b) sequentially A first dielectric layer and two second dielectric layers are formed on the surface of the semiconductor substrate, wherein the wet etching rate of the first dielectric layer is greater than that of the first one; the wet money engraving rate of the% layer; (c) performing a dry etching process to form a plurality of first holes in the predetermined metal wire region, wherein each first hole penetrates the second dielectric layer to a first predetermined depth of the first dielectric layer; (D) performing a wet-relief process to etch the first dielectric layer in each first hole to a second predetermined depth, i to completely complete the first dielectric layer between adjacent first holes Removing to form a second hole penetrating the plurality of first holes in the predetermined metal wire region; 0593-5795TW.ptd 51244V VI. Application scope of patents-(0) forming a conductive layer on the surface of the semiconductor substrate and filling it with the first hole; and (ί) performing a CMP process to remove the conductive layer of Sa The second dielectric layer is aligned on the conductive layer in Table 2. The method described in item 8 of Erdou Shen's patent scope, wherein the wet etching rate ratio of the first dielectric layer to the green dielectric layer is Not less than 3. a method described in item g of the patent scope, wherein the first dielectric layer is composed of butterfly silicon glass (BPSG) 5 and the second dielectric layer is composed of silane oxide ( η 〇xide). η. According to the method described in item 9 of the scope of patent application, Π: the electrical layer is composed of an oxide, and the second dielectric layer is composed of an emulsion. — i 2 · Method 2 2 τ described in item 8 of the scope of the patent application, the diameter of the bottom of the hole of the first hole is the same as that of the predetermined metal wire plaque = 21: 3. Jiang Sifeng Waterfall < § # After its CMP process, another wet-etching process can be performed. Removing the second dielectric layer.