CN107845605A - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
- Publication number
- CN107845605A CN107845605A CN201710674657.XA CN201710674657A CN107845605A CN 107845605 A CN107845605 A CN 107845605A CN 201710674657 A CN201710674657 A CN 201710674657A CN 107845605 A CN107845605 A CN 107845605A
- Authority
- CN
- China
- Prior art keywords
- film
- semiconductor substrate
- periphery
- manufacture method
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 82
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 54
- 239000010937 tungsten Substances 0.000 claims abstract description 54
- 239000010936 titanium Substances 0.000 claims abstract description 49
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 239000007788 liquid Substances 0.000 claims abstract description 29
- 238000004140 cleaning Methods 0.000 claims abstract description 25
- 238000005507 spraying Methods 0.000 claims abstract description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 9
- 229960002163 hydrogen peroxide Drugs 0.000 claims description 7
- 238000002156 mixing Methods 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- 229910052731 fluorine Inorganic materials 0.000 claims 2
- 239000011737 fluorine Substances 0.000 claims 2
- 239000002253 acid Substances 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 18
- 238000005516 engineering process Methods 0.000 abstract description 14
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 32
- 239000010410 layer Substances 0.000 description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 239000004411 aluminium Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 101100314162 Candida albicans (strain SC5314 / ATCC MYA-2876) YBL053 gene Proteins 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 101150044955 tof1 gene Proteins 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 101100370021 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) TOF2 gene Proteins 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000006722 reduction reaction Methods 0.000 description 3
- 101100310637 Arabidopsis thaliana SON1 gene Proteins 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 101100417245 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPN4 gene Proteins 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- LVGUZGTVOIAKKC-UHFFFAOYSA-N 1,1,1,2-tetrafluoroethane Chemical compound FCC(F)(F)F LVGUZGTVOIAKKC-UHFFFAOYSA-N 0.000 description 1
- QGHDLJAZIIFENW-UHFFFAOYSA-N 4-[1,1,1,3,3,3-hexafluoro-2-(4-hydroxy-3-prop-2-enylphenyl)propan-2-yl]-2-prop-2-enylphenol Chemical group C1=C(CC=C)C(O)=CC=C1C(C(F)(F)F)(C(F)(F)F)C1=CC=C(O)C(CC=C)=C1 QGHDLJAZIIFENW-UHFFFAOYSA-N 0.000 description 1
- KLZUFWVZNOTSEM-UHFFFAOYSA-K Aluminum fluoride Inorganic materials F[Al](F)F KLZUFWVZNOTSEM-UHFFFAOYSA-K 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/0209—Cleaning of wafer backside
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/02087—Cleaning of wafer edges
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Abstract
本公开涉及半导体器件的制造方法。作为阻挡金属膜,通过溅射工艺形成钛膜,并且通过CVD工艺将氮化钛膜形成为覆盖钛膜。接下来,通过朝向半导体衬底的背面喷射清洁化学液体来清洁其背面,并且通过使清洁化学液体从背侧朝向外围部分的表面侧环绕来去除位于外围部分中的阻挡金属膜的部分。接下来,通过CVD工艺将钨膜形成为覆盖阻挡金属膜。
Description
相关申请的交叉参考
2016年9月20日提交的日本专利申请第2016-182803号的包括说明书、附图和摘要的公开结合于此作为参考。
技术领域
本发明涉及一种半导体器件及其制造方法,并且可以适当地用于例如包括作为阻挡金属膜的钛膜和作为布线层材料的钨膜等的半导体器件中。
背景技术
多层布线结构通常被应用为半导体器件的布线结构。在半导体器件中,层间绝缘膜被形成为覆盖其上形成有半导体元件的半导体衬底,并且多层布线结构形成在层间绝缘膜之上。镶嵌(damascene)工艺被用作形成布线的一种工艺。
在镶嵌工艺中,对应于布线层的图案的布线沟槽形成在绝缘膜中。接下来,形成预定的导电膜以覆盖绝缘膜,其中阻挡金属膜插入到布线沟槽中。接下来,执行抛光工艺以去除导电膜的位于绝缘膜的上表面之上的部分,使得在布线沟槽中形成布线层。
在一些半导体器件中,钨膜被应用为导电膜,并且钛膜(下层)和氮化钛膜(上层)的层压膜被应用为阻挡金属膜。为了形成钨膜以填充布线沟槽,通过CVD(化学气相沉积)工艺形成钨膜。当通过CVD工艺形成钨膜时,六氟化钨(WF6)被用作材料气体。
当通过六氟化钨形成钨膜时,六氟化钨可以与下面的阻挡金属层的钛膜反应,从而使得粘性降低。这种现象在半导体衬底的外围部分(覆盖钛膜的氮化钛膜的厚度较小)变得尤其显著。因此,在半导体衬底(晶圆)的外围部分中明显发生由于钨膜的抛光工艺期间施加的物理负载而使钨膜剥离的问题。
为了解决该问题,例如,日本未审查专利申请公开第Hei 10(1998)-107032号提出了一种抑制钨膜剥离的技术,其中,通过利用钳位环钳位其外围部分,从而在半导体衬底的外围部分中不形成钨膜。
此外,日本未审查专利申请公开第Hei 7(1995)-273045号提出了一种在形成钨膜时使用两种类型的钳位件的技术。所提出的技术如下:在生长钨的核的阶段中,接触型钳位件(紧密地粘合至半导体衬底的外围部分)被用于防止六氟化钨包裹在其外围部分周围;以及在批量(as a bulk)形成钨膜的阶段中,通过使用与其外围部分隔开的间隔钳位件来在其外围部分中形成钨膜。
此外,日本未审查专利申请公开第Hei 11(1999)-145085号提出了一种通过氮化在半导体衬底的外围部分中暴露的钛膜以形成氮化钛膜来抑制钨膜剥离的技术。
发明内容
在通过CVD工艺形成钨膜的技术中,如上所述,存在通过六氟化钨与下面的阻挡金属膜(钛膜)之间的反应可从半导体衬底(晶圆)的外围部分剥离钨膜的问题。
其他问题和新的特征将从本说明书的描述和附图中变得清楚。
根据一个实施例的半导体器件的制造方法包括以下步骤。形成绝缘膜为覆盖半导体衬底的表面。在绝缘膜中形成开口。包括钛膜的阻挡金属膜形成为覆盖包括开口的内侧的绝缘膜。在阻挡金属膜中,去除钛膜位于半导体衬底的外围部分中的部分。钨膜形成为覆盖阻挡金属膜。去除阻挡金属膜的位于绝缘膜的上表面之上的部分以及钨膜的位于绝缘膜的上表面之上的部分,保留阻挡金属膜的位于开口中的部分以及钨膜的位于开口中的部分。
根据一个实施例的半导体器件的制造方法,可以防止钨膜剥离。
附图说明
图1是示出根据一个实施例的半导体器件的制造方法的一个步骤的截面图;
图2是示出同一实施例中的图1所示步骤之后执行的步骤的截面图;
图3是示出同一实施例中的图2所示步骤之后执行的步骤的截面图;
图4是示出同一实施例中的图3所示步骤之后执行的步骤的截面图;
图5是示出同一实施例中的图4所示步骤中的整个半导体衬底的截面图;
图6是示出同一实施例中的在图4所示步骤之后执行的利用湿蚀刻装置去除位于半导体衬底的外围部分中的阻挡金属膜的部分的步骤的部分包括截面的侧视图;
图7是示出同一实施例中的用于解释图6所示步骤的整个半导体衬底的截面图;
图8是示出同一实施例中的在图6所示步骤之后执行的步骤的截面图;
图9是示出同一实施例中的在图8所示步骤之后执行的步骤的截面图;
图10是示出同一实施例中的在图9所述步骤之后执行的步骤的截面图;
图11是示出同一实施例中的在图10所述步骤之后执行的步骤的部分截面图;
图12是示出根据比较示例的半导体器件的制造方法的一个步骤的截面图;
图13是示出在图12所示步骤之后执行的步骤的截面图;
图14是用于解释根据比较示例的半导体器件的制造方法的问题的截面图;
图15是示出根据同一实施例的第一变形例的利用湿蚀刻装置去除位于半导体衬底的外围部分中的阻挡金属膜的部分的步骤的部分地包括截面的侧视图;
图16是示出用于解释同一变形例中的图15所示步骤的整个半导体衬底的截面图;
图17是示出根据同一实施例的第二变形例的利用斜蚀刻装置去除位于半导体衬底的外围部分中的阻挡金属膜的部分的步骤的部分地包括截面的侧视图;以及
图18是示出同一变形例中的用于解释图17所示步骤的整个半导体衬底的截面图。
具体实施方式
将描述根据一个实施例的半导体器件的制造方法。如图1所示,在半导体衬底的芯片形成区域TFR中形成诸如晶体管的预定半导体元件SEE。在本说明书中,为了附图的简化通过矩形的双点划线表示半导体元件SEE。
接下来,如图2所示,例如包括氧化硅膜等的层间绝缘膜ILF形成为覆盖半导体元件SEE。接下来,通过执行预定的光刻工艺和蚀刻工艺形成穿透层间绝缘膜ILF的接触孔CHL。接下来,在接触孔CHL中形成电耦合至半导体元件SEE的接触插塞CPG。
接下来,如图3所示,氮氧化硅膜SON1形成为覆盖层间绝缘膜ILF。接下来,例如包括TEOS(原硅酸四乙酯)氧化物膜的氧化硅膜TOF1形成为覆盖氮氧化硅膜SON1。接下来,通过执行预定的光刻工艺和蚀刻工艺在氧化硅膜TOF1中形成对应于线图案的布线沟槽ICG。
接下来,如图4所示,形成阻挡金属膜BMF。阻挡金属膜BMF是钛膜TF(下层)和氮化钛膜TNF(上层)的层压膜。首先,通过溅射工艺将钛膜TF形成为覆盖氧化硅膜TOF1,包括布线沟槽ICG的内侧。接下来,通过CVD工艺将氮化钛膜TNF形成为覆盖钛膜TF。
此时,在半导体衬底SUB的外围部分WPR中,如图4和图5所示,氮化钛膜TNF的厚度变得小于芯片形成区域TFR中的厚度。在图5中,为了描述的方便仅示出了阻挡金属膜BMF而没有示出层间绝缘膜。此外,外围部分WPR例如是从半导体衬底SUB的端部开始近似1.5至2mm的区域。
接下来,去除阻挡金属膜BMF位于半导体衬底SUB的外围部分WPR中的部分。这里,与半导体衬底SUB的背面的清洁一起执行上述步骤。如图6所示,以半导体衬底SUB的背面面对晶圆台WS的这种方式,将半导体衬底SUB安装在湿式清洁装置WCM的晶圆台WS之上。用于防止清洁化学液体的散布的屏蔽板SP被布置在晶圆台WS(半导体衬底SUB)之上。晶圆台WS设置有用于喷射清洁背面的清洁化学液体的化学液体喷嘴CNZ。
用于朝向半导体衬底SUB的表面喷射惰性气体(诸如氮气)的气体喷嘴GNZ(参见图7)被布置在屏蔽板SP和晶圆台WS之间。接下来,如图6和图7所示,朝向半导体衬底SUB的背面从化学液体喷嘴CNZ喷射清洁化学液体CMS。例如,硫酸和过氧化氢溶液的混合液体(SPM:硫酸-过氧化氢混合物)被用作清洁化学液体。
在半导体衬底SUB的背面中心附近喷射的清洁化学液体CMS从中心附近朝向半导体衬底SUB的外围流动并且朝向外围部分WPR环绕(参见箭头)。随着清洁化学液体CMS环绕外围部分WPR的表面,去除位于外围部分WPR中的包括钛膜TF的阻挡金属膜BMF的部分。
此时,可以通过从气体喷嘴GNZ在半导体衬底SUB的表面上喷射氮气NIG来防止清洁化学液体CMS流入芯片形成区域TFR。通过半导体衬底SUB的旋转次数来控制将被去除的位于外围WPR中的阻挡金属膜BMF的部分的宽度(区域)。以这种方式,如图8所示,与半导体衬底SUB的背面的清洁一起去除阻挡金属膜BMF的位于外围部分WPR中的部分。
接下来,如图9所示,形成钨膜WF。钨膜WF通过CVD工艺形成。半导体衬底SUB的温度被设置为近似400℃至500℃。压力被设置为近似几Torr至100Torr(近似133Pa至13300Pa)。形成钨膜WF的工艺主要包括三个步骤:即,SiH4照射步骤(预成核)、成核步骤和主成形(depot)步骤。
首先,在SiH4照射步骤中,只有SiH4(不供应WF6)被提供给半导体衬底SUB,使得沉积厚度为几nm等级的超薄非晶Si。这是为了稳定下一成核步骤中的钨膜的生长。
接下来,在成核步骤中,通过SiH4还原反应(2WF6+3SiH4→2W+3SiF4+6H2)形成钨膜。该钨膜用作用于稳定下一主成形步骤的膜。在该工艺中,阶梯覆盖性能不如H2还原反应的情况,因此将要形成的钨膜的厚度被设置为近似100nm以下。
然后,在主成形步骤中,通过H2还原反应(WF6+3H2→W+6HF)形成钨膜。该膜形成在阶梯覆盖性能方面是卓越的,并且大部分(厚度)的钨膜形成在该主成形步骤中。
在形成钨膜WF的步骤中,预先去除阻挡金属膜BMF位于半导体衬底SUB的外围部分WPR中的部分。从而,六氟化钨(WF6)绝不与半导体衬底SUB的外围部分WPR中下方的阻挡金属膜(钛膜)反应。这将在下文中进行描述。
接下来,如图10所示,通过对钨膜WF等执行化学机械抛光(CMP),去除位于氧化硅膜TOF1的上表面之上的钨膜WF的部分和阻挡金属膜BMF的部分,留下位于布线沟槽ICG中的钨膜WF的部分和阻挡金属膜BMF的部分。因此,在布线沟槽ICG中留下的钨膜WF的部分和阻挡金属膜BMF的部分形成第一层的布线层ME1。
接下来,如图11所示,形成包括上层的布线层的多层布线结构。这里,示出了芯片形成区域TFR。通过高密度等离子体工艺,氧化硅膜HDP1形成为覆盖布线层ME1。通过图案化铝膜等,铝布线层ME2形成在氧化硅膜HDP1的表面之上。
接下来,通过高密度等离子体工艺将氧化硅膜HDP2形成为覆盖铝布线层ME2。氧化硅膜TOF2形成为覆盖氧化硅膜HDP2。接下来,氧化硅膜TOF2和氧化硅膜HDP2被平坦化。接下来,作为覆盖氧化物膜的氧化硅膜CTOF1形成为覆盖氧化硅膜TOF2等。
接下来,通过图案化铝膜等在氧化硅膜CTOF1的表面之上形成铝布线层ME3。氧化硅膜HDP3和氧化硅膜TOF3形成为覆盖铝布线层ME3,然后它们被平坦化。接下来,如果需要的话形成又一上层(未示出)的布线层,然后形成最上层的铝布线层MET、覆盖铝布线层MET的氧化硅膜HDPT、氧化硅膜TOFP和氮氧化硅膜SONP。因此,完成半导体器件的主要部分。
在半导体器件的上述制造方法中,当形成用作布线层ME1的钨膜WF时,预先去除位于半导体衬底SUB的外围部分WPR中的阻挡金属膜BMF(钛膜TF)的部分。从而,六氟化钨(WF6)绝不与半导体衬底SUB的外围部分WPR中的钛膜TF反应,从而可以防止钨膜WF的剥离。这将与根据比较示例的半导体器件的制造方法进行比较来描述。在比较示例中,与上述半导体器件的那些构件相同的构件将用相同的参考标号来表示,并且不再重复它们的描述(除非有必要)。
首先,如图12所示,通过与图1至图4所示相似的步骤形成阻挡金属膜BMF。通过假设工艺将钛膜TF形成为覆盖氧化硅膜TOF1。接下来,通过CVD工艺将氮化钛膜TNF形成为覆盖钛膜TF。此时,在半导体衬底SUB的外围部分WPR中,氮化钛膜TNF的厚度变得小于芯片形成区域TFR中的厚度。
接下来,如图13所示,通过CVD工艺形成钨膜WF。此时,与参照图9的描述相似,通过包括SiH4照射步骤、成核步骤和主成形步骤的三个步骤形成钨膜WF。
这里,一般已知六氟化钨(WF6)容易与硅(Si)、铝(Al)或钛(Ti)反应。在六氟化钨(WF6)和硅(Si)之间的反应(2WF6+3Si→2W+3SiF4)中,例如侵蚀杂质扩散层,使得会发生结击穿。在六氟化钨(WF6)和铝(Al)的反应(WF6+2Al→W+2AlF3)中,形成高阻抗AlF3,使得例如可以增加过孔接触阻抗。在六氟化钨(WF6)和钛(Ti)的反应(2WF6+3Ti→2W+3TiF4)中,发生侵蚀并且会发生膜剥离。
包括钛膜TF(下层)和氮化钛膜TNF(上侧)的层压膜的阻挡金属膜BMF被形成为其上将形成钨膜WF的底层。由于钨膜WF与层间绝缘膜ILF之间的粘合力较低,所以氮化钛膜TNF被形成为粘合膜,用于增强与钨膜的粘合。另一方面,钛膜TF被形成为用于增强与层间绝缘膜ILF的粘合并减小与接触插塞CPG等的接触阻抗的膜。
该氮化钛膜TNF用作用于防止钛膜TF直接暴露给六氟化钨(WF6)的阻挡膜。因此,重要的是作为针对损害的措施,考虑到六氟化钨(WF6)扩散到氮化钛膜TNF中以足够的厚度形成氮化钛膜TNF。
对于氮化钛膜TNF,要求降低布线层或过孔的阻抗。此外,要求确保其中形成布线层等的布线沟槽等的良好覆盖。从这些观点来看,变得重要的是减小氮化钛膜TNF的厚度。
当减小氮化钛膜TNF的厚度时,变得难以确保钛膜TF对于六氟化钨(WF6)的阻挡特性。尤其地,在半导体衬底SUB的外围部分WPR中,由于制造装置的特性,氮化钛膜TNF的厚度变得小于芯片形成区域TFR中的厚度。
为此,变得越来越难以保护钛膜TF免受六氟化钨(WF6)影响,并且当形成钨膜WF时,钛(Ti)更加容易与六氟化钨(WF6)反应(2WF6+3Ti→2W+3TiF4)。
因此,如图14所示,从半导体衬底SUB的外围部分WPR中剥离钨膜WF等,从而成为杂质,其可以是降低半导体器件的产量的一个因素。
在根据该实施例的半导体器件中,不同于根据比较示例的半导体器件,位于半导体衬底SUB的外围部分WPR中的氮化钛膜TNF具有相对较小厚度的部分以及钛膜TF的部分在形成钨膜WF之前被去除。从而,当形成钨膜WF时,钛膜TF绝不与半导体衬底SUB的外围部分WPR中的六氟化钨(WF6)反应,从而可以防止钨膜WF的剥离。
(第一变形例)
在半导体器件的上述制造方法中,已经描述了与半导体衬底SUB的背面的清洁一起执行位于半导体衬底SUB的外围部分WPR中的阻挡金属膜BMF的部分的去除的情况。这里,作为第一变形例,将描述通过在半导体衬底的外围部分上喷射化学液体去除阻挡金属膜(钛膜)的技术。
如图15所示,半导体衬底SUB被放置在湿式清洁装置WCM的晶圆台WS之上,其中半导体衬底SUB的表面朝上。用于防止化学液体的散射的屏蔽板SP被布置在半导体衬底SUB上方。用于喷射清洁化学液体的化学液体喷嘴CNZ布置在屏蔽板SP与半导体衬底SUB之间。
如图15和图16所示,朝向半导体衬底SUB的表面侧上的外围部分喷射清洁化学液体CMS。例如,氨和过氧化氢溶液的混合物(APM:氢氧化铵-过氧化氢混合物)或者氢氟酸和过氧化氢溶液的混合液体(FPM:氢氟酸-过氧化氢混合物)被用作清洁化学液体。
通过在半导体衬底SUB的外围部分上喷射清洁化学液体CMS来去除位于外围部分WPR中的包括钛膜TF的阻挡金属膜BMF的部分。此时,通过扫描宽度RAD(通过其在半导体衬底SUB的半径方向上扫描化学液体喷嘴CNZ)和半导体衬底SUB的旋转次数来控制将被去除的、位于外围部分WPR中的阻挡金属膜BMF的部分的宽度(区域)。根据该技术,如图16所示,也可以去除位于半导体衬底SUB的外围部分WPR中的阻挡金属膜BMF(钛膜TF)的部分。
(第二变形例)
这里,作为去除位于半导体衬底SUB的外围部分WPR中的阻挡金属膜BMF的部分的技术的第二变形例,将描述通过使用斜蚀刻装置去除阻挡金属膜(钛膜)的技术。
如图17所示,半导体衬底SUB被放置在斜蚀刻装置BEM的晶圆台RFW之上,其中半导体衬底SUB的表面朝上。晶圆台RFW还用作向其施加高频功率的电极。上电极UEL被布置在晶圆台RFW上方。上电极UEL耦合至地电位。
环形下电极LEL被布置为环绕晶圆台RFW的外围。下电极LEL耦合至地电位。环形绝缘环ISR布置在晶圆台RFW与下电极LEL之间。屏蔽板GDP布置在晶圆台RFW(半导体衬底SUB)和上电极UEL之间。
为了允许工艺气体朝向半导体衬底SUB的外围部分流动,在上电极UEL和屏蔽板GDP之间设置间隙。在屏蔽板GDP等中,用于发送氦气的通道被设置在屏蔽板GDP与晶圆台RFW(半导体衬底SUB)之间的空间中。
如图17所示,通过上电极UEL和屏蔽板GDP之间的间隙,朝向半导体衬底SUB的外围部分发送工艺气体PRG。此外,氦气HEG被发送到半导体衬底SUB与屏蔽板GDP之间的空间中,使得工艺气体PRG不朝向半导体衬底SUB的芯片形成区域流动。例如,四氟乙烷(CF4)、六氟化硫(SF6)或氧气(O2)被用作工艺气体PRG。
接下来,预定的高频功率被施加给晶圆台REF。因此,在包括半导体衬底SUB的外围部分的区域中以环形生成等离子体。通过向生成的等离子体中发送工艺气体PRG,对位于半导体衬底SUB的外围部分中的阻挡金属膜BMF(钛膜TF)的部分执行蚀刻处理。以这种方式,如图18所示,去除位于半导体衬底SUB的外围部分中的阻挡金属膜BMF的部分。
在上述实施例中,包括钨膜的布线层ME1被描述为示例。上述技术不限于这种布线层ME1,而是可以类似地应用于钨过孔。此外,该方法不限于第一层的布线层ME1,而是还可以应用于形成例如包括钨膜的布线层作为第二层以上的布线层的情况。
可以根据需要进行在包括变形例的实施例中描述的半导体器件的制造方法的各种组合。
由发明人做出的本发明已经基于优选实施例在上面进行了具体的描述,但不需要说,本发明不应该限于优选实施例,而是在不背离本发明的精神的范围内对本发明进行各种修改。
Claims (11)
1.一种半导体器件的制造方法,包括以下步骤:
形成绝缘膜以覆盖半导体衬底的表面;
在所述绝缘膜中形成开口;
形成包含钛膜的阻挡金属膜以覆盖包括所述开口的内侧的所述绝缘膜;
在所述阻挡金属膜中,去除所述钛膜的位于所述半导体衬底的外围部分中的部分;
形成钨膜以覆盖所述阻挡金属膜;以及
去除所述阻挡金属膜的位于所述绝缘膜的上表面之上的部分以及所述钨膜的位于所述绝缘膜的上表面之上的部分,保留所述阻挡金属膜的位于所述开口中的部分以及所述钨膜的位于所述开口中的部分。
2.根据权利要求1所述的半导体器件的制造方法,
其中去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤与通过第一清洁化学液体清洁所述半导体衬底的背表面的步骤同时执行。
3.根据权利要求2所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,控制所述半导体衬底的旋转次数。
4.根据权利要求2所述的半导体器件的制造方法,
其中在所述半导体衬底的表面上喷射惰性气体的同时,执行去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤。
5.根据权利要求2所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,硫酸和过氧化氢溶液的混合液体被用作所述第一清洁化学液体。
6.根据权利要求1所述的半导体器件的制造方法,
其中通过在所述半导体衬底的所述外围部分上喷射第二清洁化学液体来执行去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤。
7.根据权利要求6所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,控制所述半导体衬底的旋转次数以及在所述半导体衬底的半径方向上扫描用于喷射所述第二清洁化学液体的第一喷嘴的扫描宽度。
8.根据权利要求6所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,氢氟酸和过氧化氢溶液的混合液体被用作所述第二清洁化学液体。
9.根据权利要求6所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,氨和过氧化氢溶液的混合液体被用作所述第二清洁化学液体。
10.根据权利要求1所述的半导体器件的制造方法,
其中在去除所述钛膜的位于所述半导体衬底的所述外围部分中的部分的步骤中,对所述半导体衬底的所述外围部分执行等离子体蚀刻处理。
11.根据权利要求10所述的半导体器件的制造方法,
其中在所述等离子体蚀刻处理中使用基于氟的气体。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016182803A JP2018049867A (ja) | 2016-09-20 | 2016-09-20 | 半導体装置の製造方法 |
JP2016-182803 | 2016-09-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107845605A true CN107845605A (zh) | 2018-03-27 |
Family
ID=61618056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710674657.XA Pending CN107845605A (zh) | 2016-09-20 | 2017-08-09 | 半导体器件的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10269631B2 (zh) |
JP (1) | JP2018049867A (zh) |
CN (1) | CN107845605A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108575055A (zh) * | 2018-04-24 | 2018-09-25 | 广东工业大学 | 一种差分过孔分析方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273045A (ja) | 1994-03-30 | 1995-10-20 | Sony Corp | タングステン膜の成膜方法 |
JPH10107032A (ja) | 1996-10-02 | 1998-04-24 | Hitachi Ltd | 薄膜形成方法 |
JPH11145085A (ja) | 1997-11-05 | 1999-05-28 | Sony Corp | タングステン・プラグの形成方法 |
JP2007194468A (ja) * | 2006-01-20 | 2007-08-02 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR100705936B1 (ko) * | 2006-06-30 | 2007-04-13 | 주식회사 하이닉스반도체 | 반도체 소자의 비트라인 형성방법 |
-
2016
- 2016-09-20 JP JP2016182803A patent/JP2018049867A/ja active Pending
-
2017
- 2017-08-09 CN CN201710674657.XA patent/CN107845605A/zh active Pending
- 2017-08-17 US US15/679,310 patent/US10269631B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108575055A (zh) * | 2018-04-24 | 2018-09-25 | 广东工业大学 | 一种差分过孔分析方法 |
CN108575055B (zh) * | 2018-04-24 | 2020-11-13 | 广东工业大学 | 一种差分过孔分析方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2018049867A (ja) | 2018-03-29 |
US10269631B2 (en) | 2019-04-23 |
US20180082891A1 (en) | 2018-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11462470B2 (en) | Method of forming graphene and metallic cap and barrier layers for interconnects | |
US20180174961A1 (en) | Air Gap Structure and Method | |
US6531384B1 (en) | Method of forming a bond pad and structure thereof | |
US6403461B1 (en) | Method to reduce capacitance between metal lines | |
US9842768B2 (en) | Method for forming semiconductor device structure | |
US6159857A (en) | Robust post Cu-CMP IMD process | |
US6645863B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US20150137378A1 (en) | Semiconductor Device having Voids and Method of Forming Same | |
US20030022110A1 (en) | Degradation-free low-permittivity dielectrics patterning process for damascene | |
US10886222B2 (en) | Via contact, memory device, and method of forming semiconductor structure | |
KR100891401B1 (ko) | 반도체 소자의 화학적기계적 연마 방법 | |
US12087826B2 (en) | Method for forming a semiconductor structure | |
US20240194522A1 (en) | Surface modification layer for conductive feature formation | |
US6130149A (en) | Approach for aluminum bump process | |
CN107845605A (zh) | 半导体器件的制造方法 | |
KR20030020847A (ko) | 반도체 장치의 제조 방법 | |
US20040110365A1 (en) | Method of forming a planarized bond pad structure | |
US5897374A (en) | Vertical via/contact with undercut dielectric | |
US20170148735A1 (en) | Interconnect Structure for Semiconductor Devices | |
CN100355069C (zh) | 半导体装置及其制造方法 | |
US8575022B2 (en) | Top corner rounding of damascene wire for insulator crack suppression | |
US20170345780A1 (en) | Surface Conditioning And Material Modification In A Semiconductor Device | |
US6403469B1 (en) | Method of manufacturing dual damascene structure | |
US20230068625A1 (en) | Semiconductor structure and manufacturing method thereof | |
US6399503B1 (en) | Method of preventing dishing phenomenon atop a dual damascene structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180327 |
|
WD01 | Invention patent application deemed withdrawn after publication |