CN1296980C - 形成具有凹槽的焊盘的方法 - Google Patents

形成具有凹槽的焊盘的方法 Download PDF

Info

Publication number
CN1296980C
CN1296980C CNB028178254A CN02817825A CN1296980C CN 1296980 C CN1296980 C CN 1296980C CN B028178254 A CNB028178254 A CN B028178254A CN 02817825 A CN02817825 A CN 02817825A CN 1296980 C CN1296980 C CN 1296980C
Authority
CN
China
Prior art keywords
copper
layer
top surface
dielectric layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB028178254A
Other languages
English (en)
Other versions
CN1554116A (zh
Inventor
托马斯·S·小林
斯科特·K·波兹德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nxp American Corp
Vlsi Technology Co ltd
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1554116A publication Critical patent/CN1554116A/zh
Application granted granted Critical
Publication of CN1296980C publication Critical patent/CN1296980C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05546—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

一种焊盘(100)，通过首先在一个焊盘区域中提供铜(18)与氧化硅功能部件(14)的平整化组合而形成。氧化硅功能部件(14)经过蚀刻处理，来在焊盘区域上的铜中形成多个凹槽(15)。在所述铜上和所述凹槽中的氧化硅功能部件上形成一个腐蚀阻隔层(22)。通过直接将探针贴附到所述铜上来对晶片(10)进行探测。一个丝焊部(24)被直接固附在铜(18)上。由于凹陷功能部件(15)的存在，防止了探针(80)完全刺穿铜(18)。利用所述铜中的凹槽(15)，丝焊部(24)更易于破坏和刺穿腐蚀阻隔层，并且不太易于在焊盘(100)上滑动。

Description

形成具有凹槽的焊盘的方法
技术领域
本发明总体上属于半导体技术领域，更具体地说属于半导体上的焊盘技术领域。
背景技术
随着在半导体加工业中发展到利用铜来取代铝，需要能够将铜丝焊部(copper wire bond)固连到铜质焊盘上。伴随铜质焊盘的一个问题是，当对它们进行化学机械抛光(CMP)时，会发生表面凹陷现象。一种解决方案是在铜质焊盘上成形氧化槽，来提高平整度。但是，氧化槽会使得难以可靠地将金属与探针或者丝焊部发生接触。不带有切槽，不仅更难以进行CMP工艺，而且探针会损坏所述垫片，从而损害对丝焊部的接触能力。因此，需要一种焊盘结构，其允许存在切槽，并且不仅可以将铜丝丝焊到铜质焊盘上，而且能够可靠地与探针发生接触。
发明内容
本发明的目的是满足上述需要，提供一种在半导体衬底上制取焊盘的方法。
根据本发明的第一个方面，提供了一种在半导体衬底上制取焊盘的方法，包括：在该半导体衬底上形成一个介电层；对介电层进行图案化处理，以在该介电层上的焊盘区域中形成多个功能部件；在介电层的上方、多个功能部件之间以及多个功能部件上淀积一个铜层；对铜层进行化学机械抛光处理，以成形一个平整的表面，该表面由多个功能部件的显露顶表面以及铜层的顶表面组成，铜层的顶表面在经过深内蚀刻之后用于直接接收一个探针；对所述多个功能部件进行深内蚀刻，以在经过深内蚀刻的铜层中形成凹槽；以及在经过深内蚀刻的铜层上和所述凹槽中形成一个阻挡层。
根据本发明的第二个方面，提供了一种用于制取半导体结构的方法，包括：提供一个半导体衬底；在该半导体衬底上成形一个介电层；对介电层进行蚀刻处理，以在一个焊盘区域中形成多个功能部件；在介电层上淀积铜，以在该介电层上形成一个铜层，并且在所述功能部件之间以及其上形成铜填料；去除部分铜层和铜填料，以形成一个平整的表面，该表面包括铜填料的顶表面和各个功能部件的顶表面；对所述多个功能部件进行凹陷处理，以形成低于铜填料顶表面的凹槽；以及将一根导线直接连接到铜填料的顶表面上。
根据本发明的第三个方面，提供了一种用于制取半导体结构的方法，包括：提供一个半导体衬底；在该半导体衬底上形成一个介电层；对介电层进行蚀刻，以在一个焊盘区域中形成多个功能部件；在介电层上淀积铜，以在该介电层上形成一个铜层，并且在所述功能部件之间以及其上形成铜填料；对铜层和铜填料进行平整化处理，以形成一个平整的表面，该表面包括铜填料的顶表面和各个功能部件的顶表面，其中铜填料的顶表面用于直接接收一个探针；以及对多个功能部件进行凹陷处理，来形成低于铜填料的顶表面的凹槽。
附图简述
下面借助于示例对本发明进行例证，但是本发明并不局限于附图中所示内容，在附图中，相似的附图标记指示相似构件，其中：
图1示出了一个半导体衬底一部分的横剖视图，示出了根据本发明一实施例的切槽；
图2示出了图1中所示的那部分半导体衬底，其上成形有一个金属层；
图3示出了图2中所示半导体衬底在平整化处理之后的状态；
图4示出了图3中所示半导体衬底在钝化层形成之后的状态；
图5示出了图4中所示半导体衬底在对钝化层施加图案和蚀刻处理之后的状态；
图6示出了图5中所示半导体衬底在成形一个腐蚀阻挡层之后的状态；
图7示出了所述半导体衬底的一部分在丝焊操作之后的状态；而
图8是一个根据本发明一实施例的焊盘的俯视图。
本技术领域中的熟练技术人员将会明白，附图中的构件鉴于简单化和清晰化而示出，并且无需按照比例进行绘制。例如，附图中某些构件的尺寸可能被相对于其它构件放大，以有助于增进对本发明的实施例的理解。
具体实施方式
在一个实施例中，形成一个包括介电区域和铜填料的开槽式焊盘，用以改善将铜丝可靠地丝焊到铜质焊盘和探针上。本发明由权利要求加以限定，并且通过参照附图更好地得以理解。
如图1中所示，在半导体衬底10的一个表面上形成有一个介电层，该介电层形成某种图案，来形成切槽14和隔离区域12。如在此所用，术语“衬底表面”被用于指代衬底10上的功能部件(features)的最顶部显露表面。衬底10是一种半导体衬底，其已经被处理至形成焊盘，但是并不包括焊盘，焊盘的形成操作发生在对最后金属层进行处理的过程中。因此，衬底10可以具有形成于其内的晶体管、位线、字线以及类似器件。衬底10具有一个半导体层，比如硅层、砷化镓层、锗化硅层以及类似材料层，并且可以包括一个绝缘体，比如硅绝缘体(SOI)。所述介电层是用于最后金属层的介电层，并且可以利用化学汽相淀积(CVD)、自旋(spin on)、类似工艺或者它们的组合而形成。所述介电层是一种当暴露于空气中时基本上不会发生反应的介电材料，并且比如可以是通过利用四乙基原硅烷(TEOS)气体制成的二氧化硅。在一个实施例中，介电层的厚度为0.1至1微米。在一个实施例中，切槽14与切槽14之间的开口9的厚度相同，并且在另外一个实施例中，切槽14的最大宽度不超过约4微米。在一个实施例中，切槽14是一种绝缘材料。有益的是，所述切槽与隔离区域12为相同材料，因为这样仅需要进行一次淀积操作和一次图案化处理。如果切槽14与隔离区域12为不同材料，那么会需要对不止一种介电材料进行淀积操作和图案化处理，增加了制造工艺的周期。
在成形了切槽14和隔离区域12之后，可以在所述衬底表面上成形一个第一阻挡层(未示出)。在一个实施例中，第一阻挡层是利用PVD工艺制成的400埃左右厚的钽层。其它耐火金属以及它们的氮化物，比如TiN、Ti以及TaN，也可以被用作第一阻挡层。可选择地，可以使用原子层淀积(ALD)工艺或者其它方式。可以在第一阻挡层上成形一个籽晶层(seed layer)(未示出)。在一个实施例中，所述籽晶层是利用PVD形成的铜层，其厚度大约为800至1500埃。
如图2中所示，在隔离区域12上、切槽14之间以及切槽14上形成有一个金属层16，最好是铜层。如果选择使用了第一阻挡层和籽晶层，那么金属层16也将位于它们之上。在一个实施例中，金属层16是铜层和铜填料，它们淀积于所述功能部件或者切槽14之间以及它们之上。也可以使用其它导电材料，比如钨和铜的合金。金属层16利用电镀或者其它合适工艺形成。金属层16的厚度必须被制成至少等于开口9的高度。在一个实施例中，铜的淀积厚度为8000埃。
在成形了金属层16之后，部分金属层16比如利用平整化处理而被去除，以便如图3中所示出的那样，形成镶嵌结构18或者金属区域18。一般来说，金属层16经过化学机械抛光处理来获得金属区域18，金属区域18与切槽14一同形成了焊盘100。可选择地，金属层16可以经过深内蚀刻处理来获得金属区域18。在金属层16为铜层和铜填料的实施例中，铜层和铜填料经过平整化处理来形成一个基本上平整的表面，该平整表面包括铜填料的顶表面和各个切槽14的顶表面。金属区域18和切槽14是焊盘100或者焊盘区域100中的部分。
如图4中所示，在成形了焊盘100之后，在焊盘100和隔离区域12上成形一个钝化层20。该钝化层20可以是氮化硅、氧氮化硅、类似材料或者它们的组合，并且可以利用CVD、PVD、类似工艺或者它们的组合而形成。已经发现，500埃厚的氮化硅和4500埃厚的氧氮化硅用作钝化层20非常有效。接下来，如图5中所示出的那样，利用光阻材料对钝化层20进行图案化处理，并且对其进行蚀刻处理，来至少在焊盘100的一部分上形成开口90。一种含氟化学物质，比如CF4，可以被用于对钝化层20进行蚀刻。在一个实施例中，开口90利用一种蚀刻-灰化-蚀刻工艺(etch-ash-etch process)形成，意味着首先执行第一次蚀刻，随后进行灰化，接着执行第二次蚀刻，第二次蚀刻可以与第一次蚀刻相同或者不同。也可以使用其它适合于成形开口90的方法。
在一个实施例中，在执行了第一次蚀刻来形成开口90的一部分并且将用于第一次蚀刻中的光阻材料去除之后，在衬底10的整个表面上形成一个聚酰亚胺层(未示出)，并且对其进行图案化处理，来在焊盘100上并且能够在其它区域上形成开口。为了形成开口90的剩余部分，执行第二次蚀刻。可以使用与第一次蚀刻中所用蚀刻化学物质相同或者不同的蚀刻化学物质。第二次蚀刻工艺将对任何未被聚酰亚胺层覆盖起来的区域进行蚀刻。
如图5中所示，在成形开口90的同时，为了使得切槽14凹陷于金属区域18的顶表面的下方，执行过蚀刻(over etch)，在一个实施例中，金属区域18为铜填料。在存在有钝化层20的实施例中，过蚀刻用于确保钝化层20被完全从开口90中去除，以便进行后续的丝焊操作。所述铜填料的高度大于所述多个功能部件或者切槽14的高度，并且在切槽14上形成位于切槽高度与铜填料高度之间的凹槽15。凹槽15至少为100埃左右，并且更具体地说，至少为600埃左右。作为本技术领域中的普通技术人员可以确信，凹槽15的深度不会超过切槽14的高度。在一个实施例中，所述凹槽的深度处于100埃至2000埃之间，或者更具体地说，处于600埃与2000埃之间。
所希望的是，凹槽15的深度足以使得当探针80被施加到焊盘100的一部分上时，探针将沿着切槽14的顶部进行滑动，并且与金属区域18发生接触，如图5中所示出的那样。所述凹槽也可以允许任何积累在探针80上的碎屑脱落下来，并且跌落入至少一个凹槽15中或者被从切槽14的顶部上刮除。此外，切槽14的存在防止了如同现有技术中那样探针80与焊盘100中的金属区域18的底部发生接触，并且至少将所接触到的金属区域18部分去除，在所述现有技术中，未使用切槽并且会导致用于丝焊操作的接触区域较小。
使用切槽与金属区域共面的焊盘防止了焊盘被彻底刺穿，用以确保探针与金属区域之间充分接触。此外，将切槽与探针发生接触可以形成非导电性碎屑，它们会粘附到探针的尖端上，并且增大焊盘受损的可能性或者降低与金属区域18电接触的能力。
正如可以从图5中看出的那样，在一个实施例中，探针80直接与焊盘100的一部分发生接触，意味着探针将不会经由中间层与焊盘100上的所述部分发生接触。
在成形了凹槽15之后，在切槽14和金属区域18上任选性地成形一个第二阻挡层22或者腐蚀阻挡层22，来防止焊盘100受到含氧气氛或者腐蚀气氛。在一个实施例中，第二阻挡层22是由CVD或自旋淀积的薄玻璃材料。例如，第二阻挡层22可以是一种包括硅、碳、氧以及氢的材料，比如与Kulicke & Soffa Industries Inc.的OP2(SM)防氧化工艺组合出售的薄膜。第二阻挡层22的厚度小于凹槽15的高度。在一个实施例中，第二阻挡层22小于约100埃。
可选择地，第二阻挡层22可以是一种呈固体、胶体或者液体形式的腐蚀抑制剂。当使用液体的腐蚀抑制剂时，这种腐蚀抑制剂被存放成至少局部填充切槽14上的凹槽15。通过使用一种液体的腐蚀抑制剂，凹槽15可以用作所述液体的存储器，由于所述液体与金属区域18的可湿性，所述液体会随着时间的流逝而消失。因此，从金属区域18顶表面蒸发掉的腐蚀抑制剂会随着时间的流逝由来自于凹槽15的液体腐蚀抑制剂进行补充，直到没有液体。可以保存在各个凹槽15内的液体腐蚀抑制剂的量是切槽14上的凹槽15容积的一个函数。需要防止金属区域18接触氧化环境的时间越长，就需要越多的液体腐蚀抑制剂，并且凹槽15的容积就必须越大。作为普通技术人员将会认识到，凹槽15的容积取决于凹槽15的高度以及凹槽15的直径或者宽度。
在另外一个实施例中，第二阻挡层22是一种熔剂(flux)，其可以包括氯化物或者氟化物。通常，对所述熔剂进行加热，并且通过蚀刻操作去除任何已经在金属区域18上发生的腐蚀现象。接着，如同将在下面进一步解释的那样，所述熔剂会在丝焊操作中蒸发掉或者基本上由球体取代，所述球体是丝焊部中的部分。
如果没有形成第二阻挡层22，那么可以在丝焊操作之前在氮气、氢气、氩气或者类似气氛下执行标准的预清洁工艺。可选择地，开口90可以保持与氧气隔绝或者以最少方式暴露在氧气中。
在成形了焊盘100和第二阻挡层22之后，如果需要，半导体衬底10被连接在一个封装基片(未示出)上，并且受到加热，以便将至少一个焊盘100丝焊到半导体衬底10上，或者模制到一个位于封装基片上的垫片上，以便在它们之间形成电连接。在一个实施例中，为了形成丝焊部，挤压出一根金属线，并且随后受到加热，以便在该金属线的端部形成一个球体。接着，使用一个铁砧或者圆环针将所述球体和金属线扯拽到焊盘100上。利用所述圆环针向丝焊部24上施加超声波能量和压力，以便将丝焊部24直接粘接到焊盘100上，意味着金属线或者丝焊部24不会经由中间层与焊盘100上的所述部分发生接触。在一个实施例中，金属丝或者丝焊部24直接连接在铜填料的顶表面上，其中“直接”具有与前述的相同的含义。最终的结构在图7中示出。丝焊部24可以呈球形、楔形或者任何其它合适形状。
如果使用了第二阻挡层22并且是一种腐蚀抑制剂，那么其可以仅在丝焊操作之前或者之中存在。可选择地，如果使用了一种熔剂作为第二阻挡层22，那么这种熔剂可以在丝焊操作之前、之中或者之后存在。通常，熔剂在丝焊操作和加热来将腐蚀抑制剂去除的过程中消失。但是，如果使用一种玻璃作为第二阻挡层22，那么这种玻璃将在丝焊操作之前或者之中存在。在该实施例中，当丝焊部24被施加到第二阻挡层22上时，第二阻挡层22会在金属区域18的拐角处发生龟裂，并且随着时间的流逝，第二阻挡层22的剩余部分也会发生龟裂，逐步从金属区域18或者切槽14上脱落下来。可以使得最终产品在丝焊操作之后不具有第二阻挡层22，即使第二阻挡层22被用于加工程序中。因此，在一个实施例中，第二阻挡层22或者腐蚀阻挡层在对金属丝进行连接的过程中由金属丝或者丝焊部24刺穿。在另外一个实施例中，腐蚀阻隔剂或者阻挡层22在对金属丝或者丝焊部24进行连接操作的同时被去除。
在图8中示出了焊盘100的“地形化”视图，该焊盘100包括多个功能部件和一个环绕在所述多个功能部件周围的金属层，该金属层可以是铜。在所示出的实施例中，显露出来的切槽14被制成成排成列的图案，并且由金属区域18环绕起来；也可以使用任何其它图案或者任何数目的切槽14。但是，与丝焊部24发生接触的金属区域18的面积必须至少为焊盘100的34％。此外，切槽14可以呈任何形状，比如长方形、正方形或者圆柱形。
成形最终带有凹陷切槽的金属焊盘是有益的，因为凹槽15增加了探针与丝焊操作的可靠性，减轻了由于化学机械抛光所导致的抛光凹陷现象，并且控制探针80在焊盘100内的刺入度，由此限制焊盘100在探测过程中受到损坏。所述凹槽还允许任何聚积在探针80上的碎屑跌落入至少一个凹槽中，由此对探针80进行清洁。此外，凹槽15可以允许金属在多次重复探测之后仍有残留。在探测之后，尤其是多次探测之后仍然残留有金属，增加了丝焊工艺的可靠性和简便性。此外，由于凹槽15所导致的地形图案有助于进行丝焊操作，因为凹槽15增大了丝焊部24可以固附到金属区域18上的金属表面面积。还有，所述地形图案允许金属区域18和切槽14上的玻璃阻挡层更易于发生断裂，增强了焊接强度和焊接部的电接触性。
在前面的描述中，已经参照具体实施例对本发明进行了描述。但是，本技术领域的普通技术人员将会明白，在不脱离所附权利要求中陈述的本发明保护范围的条件下，可以进行各种改进和改变。因此，说明书和附图应该被看作是例证目的，而并非加以限制，并且希望将所有的这种改进被包括在本发明的保护范围之内。
在前面已经针对具体实施例对益处、其它优点以及问题解决方案进行了描述。但是，益处、优点、问题解决方案以及任何会导致产生或者明确任何益处、优点或者解决方案的构件，均不用于构成任何权利要求或者所有权利要求中的关键、必要或者基本特征或者构件。如在此所用，术语“包括”“包含”或者任何类似用语，均用于覆盖一种非排它性包括，比如一种包括一组构件的工艺、方法、物品或者设备，不仅包括这些构件，而且可以包括未明确列出或者对于这种工艺、方法、物品或者设备来说固有的其它构件。

Claims (6)

1.一种在半导体衬底(10)上制取焊盘(100)的方法，包括：
在该半导体衬底上形成一个介电层(12)；
对介电层(12)进行图案化处理，以在该介电层(12)上的焊盘区域中形成多个功能部件(14)；
在介电层(12)的上方、多个功能部件(14)之间以及多个功能部件(14)上淀积一个铜层(16)；
对铜层(16)进行化学机械抛光处理，以形成一个平整的表面，该表面由多个功能部件(14)的显露顶表面以及铜层(18)的顶表面组成，铜层(18)的顶表面在经过深内蚀刻之后用于直接接收一个探针(80)；
对所述多个功能部件(14)进行深内蚀刻，以在经过深内蚀刻的铜层中形成凹槽(15)；以及
在经过深内蚀刻的铜层上和所述凹槽中形成一个阻挡层(22)。
2.如权利要求1所述的方法，还包括：
在所述半导体衬底上形成一个钝化层(20)；和
在进行深内蚀刻处理之前，在所述焊盘区域上的钝化层(20)中形成至少一个局部开口(90)。
3.如权利要求2所述的方法，还包括：
在所述钝化层上形成一个聚酰亚胺层；和
在进行深内蚀刻处理之前，在所述焊盘区域上的聚酰亚胺层中形成至少一个局部开口。
4.一种用于制取半导体结构的方法，包括：
提供一个半导体衬底(10)；
在该半导体衬底(10)上成形一个介电层(12)；
对介电层(12)进行蚀刻处理，以在一个焊盘区域中形成多个功能部件(14)；
在介电层(12)上淀积铜(16)，以在该介电层(12)上形成一个铜层(16)，并且在所述功能部件(14)之间以及其上形成铜填料(18)；
去除部分铜层(16)和铜填料(18)，以形成一个平整的表面，该表面包括铜填料(18)的顶表面和各个功能部件(14)的顶表面；
对所述多个功能部件(14)进行凹陷处理，以形成低于铜填料(18)顶表面的凹槽(15)；以及
将一根导线(24)直接连接到铜填料(18)的顶表面上。
5、一种用于制取半导体结构的方法，包括：
提供一个半导体衬底(10)；
在该半导体衬底(10)上形成一个介电层(12)；
对介电层(12)进行蚀刻，以在一个焊盘区域中形成多个功能部件(14)；
在介电层(12)上淀积铜(16)，以在该介电层(12)上形成一个铜层(16)，并且在所述功能部件(14)之间以及其上形成铜填料(18)；
对铜层(16)和铜填料(18)进行平整化处理，以形成一个平整的表面，该表面包括铜填料(18)的顶表面和各个功能部件(14)的顶表面，其中铜填料(18)的顶表面用于直接接收一个探针(80)；以及
对多个功能部件(14)进行凹陷处理，来形成低于铜填料(18)的顶表面的凹槽(15)。
6.如权利要求5所述的方法，还包括将一个探针(80)直接作用到铜填料(18)的顶表面上。
CNB028178254A 2001-09-14 2002-08-20 形成具有凹槽的焊盘的方法 Expired - Lifetime CN1296980C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/952,527 2001-09-14
US09/952,527 US6531384B1 (en) 2001-09-14 2001-09-14 Method of forming a bond pad and structure thereof

Publications (2)

Publication Number Publication Date
CN1554116A CN1554116A (zh) 2004-12-08
CN1296980C true CN1296980C (zh) 2007-01-24

Family

ID=25492992

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028178254A Expired - Lifetime CN1296980C (zh) 2001-09-14 2002-08-20 形成具有凹槽的焊盘的方法

Country Status (8)

Country Link
US (1) US6531384B1 (zh)
EP (1) EP1430523A2 (zh)
JP (1) JP4451134B2 (zh)
KR (1) KR100896141B1 (zh)
CN (1) CN1296980C (zh)
AU (1) AU2002323303A1 (zh)
TW (1) TW559965B (zh)
WO (1) WO2003025998A2 (zh)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
US7372153B2 (en) * 2003-10-07 2008-05-13 Taiwan Semiconductor Manufacturing Co., Ltd Integrated circuit package bond pad having plurality of conductive members
US7214605B2 (en) * 2003-10-09 2007-05-08 Intel Corporation Deposition of diffusion barrier
US7247564B2 (en) * 2004-06-28 2007-07-24 Hewlett-Packard Development Company, L.P. Electronic device
US7213329B2 (en) * 2004-08-14 2007-05-08 Samsung Electronics, Co., Ltd. Method of forming a solder ball on a board and the board
US7429795B2 (en) * 2005-09-27 2008-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure
KR100699865B1 (ko) * 2005-09-28 2007-03-28 삼성전자주식회사 화학기계적 연마를 이용한 자기 정렬 콘택 패드 형성 방법
KR100699892B1 (ko) * 2006-01-20 2007-03-28 삼성전자주식회사 솔더접합신뢰도 개선을 위한 락킹 구조를 갖는 반도체 소자및 인쇄회로기판
US7598620B2 (en) * 2006-05-31 2009-10-06 Hebert Francois Copper bonding compatible bond pad structure and method
WO2008015500A1 (en) * 2006-08-01 2008-02-07 Freescale Semiconductor, Inc. Method and apparatus for improvements in chip manufacture and design
US7812448B2 (en) * 2006-08-07 2010-10-12 Freescale Semiconductor, Inc. Electronic device including a conductive stud over a bonding pad region
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US8134235B2 (en) 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device
CN103178032B (zh) 2007-07-31 2017-06-20 英闻萨斯有限公司 使用穿透硅通道的半导体封装方法
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
WO2009058143A1 (en) * 2007-10-31 2009-05-07 Agere Systems Inc. Bond pad support structure for semiconductor device
KR100933685B1 (ko) * 2007-12-18 2009-12-23 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
US8053900B2 (en) * 2008-10-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect
KR20100060309A (ko) * 2008-11-27 2010-06-07 주식회사 동부하이텍 반도체 소자
JP5353313B2 (ja) * 2009-03-06 2013-11-27 富士通セミコンダクター株式会社 半導体装置
US8259415B2 (en) * 2009-06-22 2012-09-04 Seagate Technology Llc Slider bond pad with a recessed channel
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
JP5610905B2 (ja) * 2010-08-02 2014-10-22 パナソニック株式会社 半導体装置
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
JP2012124452A (ja) * 2010-12-06 2012-06-28 Samsung Electro-Mechanics Co Ltd プリント基板およびその製造方法
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
CN102612262A (zh) * 2011-01-18 2012-07-25 三星半导体(中国)研究开发有限公司 焊盘结构及其制造方法
US8314026B2 (en) 2011-02-17 2012-11-20 Freescale Semiconductor, Inc. Anchored conductive via and method for forming
US9177914B2 (en) * 2012-11-15 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad structure over TSV to reduce shorting of upper metal layer
US9978637B2 (en) * 2013-10-11 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)
US20160093583A1 (en) 2014-09-25 2016-03-31 Micron Technology, Inc. Bond pad with micro-protrusions for direct metallic bonding
CN105742226B (zh) * 2014-12-09 2019-05-21 中国科学院微电子研究所 半导体器件制造方法
US9960130B2 (en) * 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
US9953940B2 (en) * 2015-06-26 2018-04-24 International Business Machines Corporation Corrosion resistant aluminum bond pad structure
CN108807320A (zh) * 2018-06-01 2018-11-13 武汉新芯集成电路制造有限公司 芯片及键合垫的形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244858A (ja) * 1987-03-31 1988-10-12 Toshiba Corp 金属配線の形成方法
JPH06318590A (ja) * 1993-05-10 1994-11-15 Nec Corp 半導体装置の製造方法
WO2000021126A1 (en) * 1998-10-05 2000-04-13 Kulicke & Soffa Investments, Inc. Semiconductor copper bond pad surface protection

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
US5382831A (en) 1992-12-14 1995-01-17 Digital Equipment Corporation Integrated circuit metal film interconnect having enhanced resistance to electromigration
US5976971A (en) * 1995-07-19 1999-11-02 Ricoh Company, Ltd. Fabrication process of a semiconductor device having an interconnection structure
US5904563A (en) * 1996-05-20 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal alignment mark generation
JP3526376B2 (ja) * 1996-08-21 2004-05-10 株式会社東芝 半導体装置及びその製造方法
US6114187A (en) * 1997-01-11 2000-09-05 Microfab Technologies, Inc. Method for preparing a chip scale package and product produced by the method
JP3031301B2 (ja) * 1997-06-25 2000-04-10 日本電気株式会社 銅配線構造およびその製造方法
US6593241B1 (en) 1998-05-11 2003-07-15 Applied Materials Inc. Method of planarizing a semiconductor device using a high density plasma system
US6306750B1 (en) * 2000-01-18 2001-10-23 Taiwan Semiconductor Manufacturing Company Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability
TW437030B (en) * 2000-02-03 2001-05-28 Taiwan Semiconductor Mfg Bonding pad structure and method for making the same
CN1314225A (zh) * 2000-02-18 2001-09-26 德克萨斯仪器股份有限公司 铜镀层集成电路焊点的结构和方法
US6383935B1 (en) * 2000-10-16 2002-05-07 Taiwan Semiconductor Manufacturing Company Method of reducing dishing and erosion using a sacrificial layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63244858A (ja) * 1987-03-31 1988-10-12 Toshiba Corp 金属配線の形成方法
JPH06318590A (ja) * 1993-05-10 1994-11-15 Nec Corp 半導体装置の製造方法
WO2000021126A1 (en) * 1998-10-05 2000-04-13 Kulicke & Soffa Investments, Inc. Semiconductor copper bond pad surface protection

Also Published As

Publication number Publication date
US20030054626A1 (en) 2003-03-20
CN1554116A (zh) 2004-12-08
WO2003025998A2 (en) 2003-03-27
TW559965B (en) 2003-11-01
KR20040035779A (ko) 2004-04-29
EP1430523A2 (en) 2004-06-23
JP2005522019A (ja) 2005-07-21
AU2002323303A1 (en) 2003-04-01
WO2003025998A3 (en) 2003-06-12
KR100896141B1 (ko) 2009-05-12
US6531384B1 (en) 2003-03-11
JP4451134B2 (ja) 2010-04-14

Similar Documents

Publication Publication Date Title
CN1296980C (zh) 形成具有凹槽的焊盘的方法
US7750488B2 (en) Method for bonding wafers to produce stacked integrated circuits
US7419906B2 (en) Method for manufacturing a through conductor
US7649268B2 (en) Semiconductor wafer
CN112771656A (zh) 通过在直接键合工艺期间捕获污染物并阻止裂纹来增强微电子结构中的键合
US20020113273A1 (en) Semiconductor device having contact plug and method for manufacturing the same
TW200406812A (en) Method of forming a raised contact for a substrate
JP2008182269A (ja) 軟金属導体およびその形成方法
JPH0777218B2 (ja) 同平坦面の金属層および絶縁層の形成方法
US6200889B1 (en) Semiconductor bonding pad
US6791196B2 (en) Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same
US6645863B2 (en) Method of manufacturing semiconductor device and semiconductor device
US6703709B1 (en) Structures formed using silicide cap as an etch stop in multilayer metal processes
CN114072896A (zh) 半导体器件和制造半导体器件的方法
US7176127B2 (en) Method of manufacturing semiconductor device having through hole with adhesion layer thereon
US20110269308A1 (en) Method for manufacturing semiconductor device
US6740564B2 (en) Method for manufacturing a semiconductor device
US6972251B2 (en) Method for fabricating copper damascene structures in porous dielectric materials
CN109712963A (zh) Cpi测试结构及基于该结构的失效分析方法
US6690580B1 (en) Integrated circuit structure with dielectric islands in metallized regions
Di Cioccio et al. An overview of patterned metal/dielectric surface bonding: Mechanism, alignment and characterization
US20170345780A1 (en) Surface Conditioning And Material Modification In A Semiconductor Device
JP4209033B2 (ja) 半導体装置の製造方法
US7128946B2 (en) Plate for forming metal wires and method of forming metal wires using the same
US6887790B1 (en) Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1070466

Country of ref document: HK

C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: WD

Ref document number: 1070466

Country of ref document: HK

C56 Change in the name or address of the patentee

Owner name: FISICAL SEMICONDUCTOR INC.

Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP.

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: FREESCALE SEMICONDUCTOR, Inc.

Address before: Texas in the United States

Patentee before: FreeScale Semiconductor

CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: Delaware

Patentee after: NXP American Corp.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170512

Address after: Delaware

Patentee after: VLSI Technology Co.,Ltd.

Address before: Delaware

Patentee before: NXP American Corp.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070124