TW461033B - A reticular pad structure for removing cracks in inter-metal dielectrics on bonding pad and its fabrication - Google Patents

Abstract

This invention presents a reticular pad structure for removing cracks in inter-metal dielectrics (IMD) on bonding pad. The structure includes at least the following: a bonding pad area placed on the conducting layer of a semiconductor substrate, an insulating layer placed on the surface of the bonding pad area, multiple openings placed in the insulating layer and arranged in reticular form, the first metal layer which fills the multiple openings, and the second metal layer placed on the surfaces of the insulating layer and the first metal layer.

Description

461033 V. Description of the invention (l) Field of the invention: The present invention relates to a structure for removing cracks in an inter-mediate dielectrics (IMD) on a bonding pad and a method for forming the same, and particularly relates to a method for eliminating the cracks. Reticulated pad structure with cracks in the metal dielectric layer on the pad and a method for forming the same. BACKGROUND OF THE INVENTION In the current semiconductor industry, the manufacturing of integrated circuits is mainly divided into: wafer manufacturing, integrated circuit manufacturing, integrated circuit cutting and packaging, and so on. After the integrated circuit is formed on the wafer, a bonding pad area is usually formed in order to carry out subsequent chip packaging steps. A general bonding pad structure is composed of a metal and a mesoporous layer, that is, a metal dielectric layer (I nter-Mediate. Dielectrics, IMD) is excavated in a number of Via hole, then fill metal in the via hole to form a metal plug, and finally form a metal layer on the inner metal dielectric layer. Wherein the material of the inner metal dielectric layer is usually oxidized The metal filled in the via is usually crane metal. Since the metal dielectric layer in the conventional pad is composed of a via hole array, the metal dielectric layer is not separated into a plurality of independent regions by metal plugs formed in the via holes. Chip blocking

Page 4 4 6 1 03 3 r 5. Description of the invention (2) In the process, the pad structure with an array of interlayer holes is prone to generate internal metal dielectric oxide cracks. Until now, most of the methods to solve the above-mentioned cracks of the inner metal dielectric layer oxide mainly consisted of changing the composition of the inner metal dielectric layer oxide film (for example: using HDP (high density plasma) and PETE0S (plasma enhanced TE0S) to Forming an inner metal dielectric layer), using different inner metal dielectric layer oxide thin film layers to reduce the pressure on the inner metal dielectric layer oxide. (Although the above method can increase the processing window to avoid oxide cracks, but because of this kind of structure, the structure is composed of metal, internal, metal dielectric oxide and tungsten plug on a small area. Stack structure, so when external force is applied to it, it is easy to produce oxide cracks on the pad. Therefore, even by changing the composition of the oxide film of the inner metal dielectric layer, the compression resistance of the oxide film is enhanced. The pressure resistance of the inner metal dielectric layer oxide in the area on the pad still cannot resist the external force σ applied to the chip during packaging. '..'. ':. For the traditional pad structure, please refer to the Republic of China Patent " An integrated circuit [a pad structure and a manufacturing method thereof (patent application number 85 1 0 5 3 5 9 ·) ". Also," a conventional pad structure with an interposer hole array is shown in Fig. 1A ~ Fig. 1 " C, it can be seen from the figure that 'the metal dielectric layer 1 102 in the conventional pad on the semiconductor substrate 100 has not been separated into a plurality of independent regions by the metal-filled interlayer hole 104' in the wafer During the packaging process, the pads must withstand great external forces

Page 5 461033 V. Description of the invention (3) Pulling, once the external force is very large, the welding gall is difficult to bear, and the internal metal dielectric layer oxide cracks begin to occur. If there is no proper structure to block the crack extension, the metal dielectric layer will oxidize. It is very easy for things to extend in the direction of the stress. When the cracks continue to extend and cracks are formed across the pad structure, the structure of the pad will be severely damaged, and the resistance to external forces will be greatly reduced. During the chip packaging process, the structure of this pad with a dielectric layer array of 104 has no good structure to suppress crack extension, so it is easy to produce internal metal dielectric layer oxide cracks. Therefore, how to solve the pad structure because of the internal metal dielectric layer oxide cracks generated during the chip packaging process has become an urgent problem in the industry. OBJECT AND SUMMARY OF THE INVENTION The object of the present invention is to provide a net-like pad structure and a method for forming the same, so as to increase the strength of the pad. Another object of the present invention is to provide a net-shaped pad structure and a method for forming the same, so as to solve the problem of cracks in the inner metal dielectric layer of the conventional pad structure due to the chip packaging process. The method for forming a bonding pad of an integrated circuit provided by the present invention includes the following steps: (1) providing a semiconductor substrate, wherein

Page 6 461033 V. Description of the invention (4) There is a soldering region on the semiconductor substrate. You, t ^ / • beetle Q forms an insulating layer on the surface of the pad area. (3) A plurality of openings are formed in the insulating layer by using a tree > 2 < {Fen AΛ, * || 4i Ία., ^ 扪 with a micro-shirt and an etching technique, in which the plurality of openings are arranged in a mesh shape. (P-deposited-first-metal layer on the insulating layer and the plurality of openings, and filled the openings. (5) Planarize the first metal layer β (β) to form a second metal layer between the insulating layer and the A metal layer surface. The present invention provides a pad structure for an integrated circuit, which at least includes: a pad area: 'on a semiconductor substrate, an insulation layer on the surface of the pad area, wherein the insulation layer has an arrangement A plurality of openings formed into a network, a first metal layer, filled in the plurality of openings, and a second metal layer, which are located on the surfaces of the insulating layer and the first metal layer. '... Wherein the above semiconductor substrate has at least one conductive region, and the insulating layer includes oxygen compounds or nitrogen oxides, the material of the first metal layer includes tungsten, and the material of the second metal layer includes aluminum, copper, aluminum silicon copper, or Copper alloy. 'Any one of the above openings and adjacent openings may not be connected together, and the distance between them is about 100 times the size of the opening diameter. In addition, any of the above openings and adjacent openings may be connected. Together to The insulating layer is divided into a plurality of rectangular blocks or pillar blocks having twelve sides independent of each other (not in contact with each other). The insulating layer is divided into a plurality of twelve sides independent of each other (not in contact with each other). The side of the column block 'the length of the shortest side in any column block is about 1 times the size of the opening, and the length of the second shortest side is about 2 times the size of the opening

Page 7 461033 V. Description of the invention (5) The following. Detailed description of the invention. The object of the present invention is to provide a net-shaped pad structure and a method for forming the same, so as to increase the strength of the pad. Another object of the present invention is to provide a net-shaped solder pad structure and a method for forming the same, in order to solve the problem of cracks in the internal (metal dielectric layer) cracks caused by the traditional process of chip packaging. An embodiment is described in detail. The mesh pad structure for eliminating cracks in the metal dielectric layer on the pad provided by the present invention is as follows: '... Please refer to FIG. ) Of the structure _... includes: a _ pad region on the semiconductor. Substrate 2 0 field 201, wherein the semiconductor substrate 2 0 0 has at least one conductive region and the pad region 2 0 1 twisted connection, An insulating layer 2 0 2 on the surface of the pad region 201, wherein the insulating factory layer 2 2 has a plurality of openings 2 0 4 arranged in a mesh, wherein the plurality of posts 2 4 are arranged in a mesh. Shape, and the distance between any opening 2 0 4 and the adjacent opening 2 0 4 is less than 100 times the size of the opening 2 0 4, and one is used to fill a plurality of openings 2 0 4 A metal layer (not shown), and a second layer on the surface of the insulating layer 202 and the first metal layer Metal layer (not shown)

Page 8 461033 V. Description of Invention (6). In the above embodiment, the plurality of openings 204 on the pad are arranged in a net shape and filled with the first metal layer, and the distance between any opening 204 and the adjacent opening 204 is about this opening. 2 04 diameter is less than 100 times. Therefore, during the chip packaging process, this pad having a plurality of openings arranged in a mesh pattern has greater strength than a conventional pad having an array of via holes. It is less likely to cause cracks in the insulating layer due to the external force applied during packaging, and even if a crack occurs in a certain area of the insulating layer, the crack will be blocked by the opening 2 0 4 which is adjacent to the first metal layer, so Avoid cracks from spreading to other areas. The above-mentioned insulating layer 202 can be used as an inner metal dielectric layer, and its material includes an oxide or an oxynitride. The material of the first metal layer includes tungsten, the material of the second metal layer includes aluminum, copper, aluminum silicon copper, or copper alloy, and the conductive region may be made of a metal material. In addition, here are three preferred embodiments to explain in detail the distribution of the plurality of openings 2 0 4 arranged in the mesh in the insulating layer 2 2. For these three preferred embodiments', please refer to Fig. 3A, Fig. 3B, and Fig. 3C, respectively. As shown in FIG. 3A, each opening 204 is adjacent to the adjacent opening 204, and is not connected. The distance between each opening 204 and the adjacent opening 204 is about this. The opening 2 is smaller than 100 times the size of the aperture. As shown in FIG. 3B, each opening 204 is connected to the adjacent opening 204, and the insulating layer 2 0 is separated by the plurality of openings 2 0 4 to be independent of each other (not to each other).

5. Description of the invention (7) ~;-Contact) A plurality of rectangular blocks. As shown in FIG. 3c, each opening 204 is connected to an adjacent opening 204, and the insulating layer 202 is separated by the plurality of openings 204 into a plurality of independent (not in contact with) each other. A column block with twelve sides is shown. The length of the shortest side in each column block is about 100 times the size of the opening 204. The side with the second shortest side The length is about 100 times the size of the opening 204. Here is an embodiment, which details the method for forming the mesh pad for eliminating cracks in the metal dielectric layer on the pad provided by the present invention as follows: Please refer to FIG. 4. The method for forming the solder pad of the present invention includes: first, a semiconductor A pad region 300 is provided on the conductive layer 300 of the substrate. Then an insulating layer 3 0 4 is formed on the surface of the rod. The surface of the field 3 2 is then formed by using lithography and engraving techniques to form a plurality of openings 3 0 6 in the insulating layer 3 0 4, wherein the plurality of openings 3 0 6 are arranged in a net shape, and the distance between any opening 306 and the adjacent opening 306 is approximately 3.06 of this opening. The diameter of the opening is smaller than 1000 times. .... Then referring to FIG. 5, a first metal layer 3 08 is deposited on the insulating layer 3 04 and the opening 3 06, and fills the opening 3 06. This first metal plant layer 3 0 8 is then planarized. Finally, a second metal layer 3 10 is formed on the surfaces of the insulating layer 304 and the first metal layer 308. In the above embodiment, since the plurality of openings 3 06 on the pad are arranged in a net shape and filled with the first metal layer 3 0 8 ′, and any one of the openings 3 6 is adjacent to

Page 10 461033 V. Description of the invention The distance between the openings 3 and 6 is less than 100 times the size of the openings in the chip packaging process. The openings of 3 6 6 are more traditional and have 8 /, There are a plurality of openings arranged in a mesh pattern, which is more common because of the seal, and even if a certain insulation layer is born: generated: cracks spread to other areas. The above-mentioned insulating layer 304 can be used as an inner metal dielectric layer, and its material includes oxides or oxynitrides, and the formation method thereof

Methods include HDP (high density plasma) and PECVD (Piasnia enhanced chemical vapor deposition). In addition, the material of the first metal layer 308 includes tungsten, and it can use, for example, physical vapor deposition (PVD) 'CVD (chemical....).

It is formed by similar processes such as vapor deposition), base ore method, etc. As for the method of planarizing the first metal layer 308, it includes chemical mechanical pol ishing or spin coating wave glass method (sp i n -on g 1 as s). In addition, the material of the second metal layer 3 10 includes aluminum, copper, aluminum-silicon-copper, or copper alloy 'and it can be formed using a similar process such as a physical vapor deposition method, a sputtering method, or the like. The conductive layer 3 0 0 may be made of a metal material. Of course, for the distribution of the plurality of openings 306 arranged in a mesh pattern in the insulating layer 304, reference may also be made to the three preferred embodiments shown in FIGS. 3A, 3B, and 3C.

Page 11 4 6 1 03 3 V. Description of the invention (9) Of course, the pad structure and the forming method of the present invention can be used to deposit between any metal layer or any two metal layers to solve the traditional pad structure because the chip packaging process The problem of internal metal dielectric layer cracks. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, as long as it is using a mesh The pad structure is used to increase the strength of the pad, so as to solve the problem of cracks in the inner metal dielectric layer generated during the chip packaging process in the conventional pad structure, all should be regarded as the protection scope of the present invention. The scope of patent protection of the present invention depends on the scope of the attached patent application and its equivalent fields.

Page 12

Claims (1)

4 61 0 3 3 VI. Scope of patent application 1. A bonding pad structure of an integrated circuit, the structure includes at least: a pad area on a semiconductor substrate; an insulation layer on the pad area On the surface, the insulating layer has a plurality of openings arranged in a mesh shape; a first metal layer filled in the plurality of openings; and a second metal layer on the surface of the insulating layer and the first metal layer . 2. The structure according to item 1 of the patent application range, wherein the above-mentioned semiconductor substrate has at least one conductive region. 3. The structure according to item 1 of the patent application range, wherein the above-mentioned insulating layer includes an oxide or an oxynitride. 4. For the structure of item '1 of the scope of patent application, wherein the material of the first metal layer mentioned above includes tungsten. 5. For the structure of item 1 of the scope of patent application, wherein the material of the second metal layer mentioned above includes aluminum, copper, aluminum silicon copper or copper alloy '. 6. If the structure of the scope of the patent application is item 1, the distance between any one of the openings mentioned above and the adjacent opening is about 1000 times or less the size of the opening. Page 15 461033 6. Scope of patent application 7. For the structure of scope 1 of the patent application scope, there may be a gap between any of the openings described above and adjacent openings, and the distance between them is approximately 1 0 0 times or less. 8. For the structure of the scope of patent application item 1, any one of the openings mentioned above and adjacent openings can be connected together to separate the insulating layer into a plurality of rectangular blocks that are independent (not in contact with each other). 9. The structure of item 1 of the scope of patent application, in which any one of the openings described above and adjacent openings can be connected together to separate the insulating layer into a plurality of twelve independent ones (not in contact with each other). A side cylinder block, in which the length of the shortest side of any one of the cylinder blocks is less than or equal to 1 times the size of the opening, and the length of the second shortest side is about 2 Times below. 10. —A method for forming a bonding pad of an integrated circuit, the method includes at least the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a pad region; — forming an insulating layer on the pad region On the surface; using lithography and etching techniques to form a plurality of openings in the insulating layer, wherein the plurality of openings are arranged in a network; depositing a first metal layer on the insulating layer and the plurality of openings, and Page 16 461033 6. Scope of patent application Fill the openings; flatten the first metal layer; and form a second metal layer on the surface of the insulating layer and the first metal layer. 11. The method of claim 10, wherein the semiconductor substrate has at least one conductive region. 12. The method according to item 10 of the scope of patent application, wherein said insulating layer comprises an oxide or an II oxide. 1 3. The method of claim 10 in the scope of patent application, wherein the material of the first metal layer mentioned above includes tungsten. 14. The method according to item 10 of the scope of patent application, wherein the material of the second metal layer comprises aluminum, copper, aluminum silicon copper, or copper alloy. 15. The method according to item 10 of the scope of patent application, wherein the distance between any one of the openings mentioned above and the adjacent opening is about 1000 times or less the size of the opening. 16. The method according to item 10 of the scope of patent application, wherein any one of the openings described above may have a gap between adjacent openings, and the distance between them is less than 100 times the size of the opening. Page 17 4 6 1 03 3 VI. Application for patent scope 1 7. The method for applying for patent item No. 10, wherein any one of the openings mentioned above and adjacent openings can be connected together to separate the insulating layer Into a plurality of rectangular blocks that are independent of each other (not in contact with each other). 1 8. The method according to item 10 of the scope of patent application, wherein any one of the openings described above and adjacent openings can be connected together to separate the insulating layer into a plurality of independent (non-contact) A cylinder block with two sides, wherein the length of the shortest side in any one of the cylinder blocks is less than or equal to 1 times the size of the opening, and the length of the second shortest side is about the opening. Less than 2 times. 19. The method according to item 10 of the scope of patent application, wherein the method for planarizing the first metal layer includes a chemical mechanical polishing method or a spin-on glass method (spin-on gUss) ° 2 0. — A solder pad structure for integrated circuits, the structure includes at least: a solder pad area on a conductive layer; an insulating layer on the surface of the solder pad area, where the The insulating layer has a plurality of openings arranged in a network; a first metal layer filled in the plurality of openings; and a second metal layer located on the surface of the insulating layer and the first metal layer. Page 18 461033 VI. The scope of patent application. 2 1. The structure according to item 20 of the scope of patent application, wherein the aforementioned conductive layer is located in a semiconductor substrate. 2 2. The structure according to item 20 of the scope of patent application, wherein the above-mentioned conductive layer includes a metal layer. 2 3. The structure according to item 20 of the patent application scope, wherein the above-mentioned insulating layer comprises an oxide or an oxynitride. 24. The structure according to item 20 of the scope of patent application, wherein the material of the first metal layer mentioned above includes tungsten. 25. The structure according to item 20 of the scope of patent application, wherein the material of the second metal layer includes aluminum, copper, aluminum silicon copper, or copper alloy. 2 6 For the structure of the 20th scope of the patent application, the distance between any one of the openings mentioned above and the adjacent opening is about 100 times or less the size of the opening. 27. The structure according to item 20 of the scope of patent application, wherein any one of the openings described above may have a gap between adjacent openings and the distance between them is less than 100 times the size of the opening. Page 19, 461033 6. Application for patent scope 2 8. The structure of item 20 in the scope of patent application, in which any one of the openings mentioned above and adjacent openings can be connected together to separate the insulation layers from each other ( Multiple rectangular blocks that do not touch each other). 2 9. The structure according to item 20 of the scope of patent application, wherein any one of the openings described above and adjacent openings can be connected together to separate the insulating layer into a plurality of independent (non-contact) A cylinder block with two sides, wherein the length of the shortest side in any one of the cylinder blocks is less than or equal to 1 times the size of the opening, and the length of the second shortest side is about the opening. Less than 2 times. 30. A method for forming a bonding pad of an integrated circuit, the method includes at least the following steps: forming a pad region on a conductive layer; forming an insulating layer on the surface of the pad region; using micro Shadowing and etching techniques to form a plurality of openings in the insulating layer, wherein the plurality of openings are arranged in a mesh shape; depositing a first metal layer on the insulating layer and the plurality of openings and filling the plurality of openings; Planarizing the first metal layer; and forming a second metal layer on the surface of the insulating layer and the first metal layer. Page 20 4 61 03 3 VI. Scope of patent application 3 1. The method according to item 30 of the scope of patent application, wherein the aforementioned conductive layer is located in a semiconductor substrate. 32. The method of claim 30, wherein the above-mentioned conductive layer comprises a metal layer. 33. The method according to claim 30, wherein the above-mentioned insulating layer comprises an oxide or an oxynitride. 34. The method of claim 30, wherein the material of the first metal layer includes tungsten. 35. The method of claim 30, wherein the material of the second metal layer includes aluminum, copper, aluminum silicon copper, or copper alloy. 36. The method according to item 30 of the scope of patent application, wherein the distance between any one of the openings mentioned above and the adjacent opening is about 1000 times or less the size of the opening. 3 7. The method according to item 30 of the scope of patent application, wherein any one of the above mentioned, there may be a gap between the opening and an adjacent opening, and the distance between them is less than 100 times the size of the opening. 3 8. The method of applying for item 30 of the patent scope, wherein any one of the above Page 21 461033 6. Scope of patent application The opening and adjacent openings can be connected together to separate the insulating layer into a plurality of rectangular blocks that are independent (not in contact with each other). 39. The method according to item 30 of the scope of patent application, wherein any one of the openings described above and adjacent openings can be connected together to separate the insulating layer into a plurality of independent (not in contact with) each having ten A cylinder block with two sides, wherein the length of the shortest side in any one of the cylinder blocks is less than or equal to 1 times the size of the opening, and the length of the second shortest side is about the opening. Less than 2 times. 40. The method of claim 30, wherein the method for planarizing the first metal layer includes a chemical mechanical polishing method (che in ica 1 mechanical polishing) or a spin-on glass method ). Page 22