TW558756B - Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device Download PDF

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Publication number
TW558756B
TW558756B TW090116490A TW90116490A TW558756B TW 558756 B TW558756 B TW 558756B TW 090116490 A TW090116490 A TW 090116490A TW 90116490 A TW90116490 A TW 90116490A TW 558756 B TW558756 B TW 558756B
Authority
TW
Taiwan
Prior art keywords
pattern
light
wiring
hole
hole pattern
Prior art date
Application number
TW090116490A
Other languages
English (en)
Chinese (zh)
Inventor
Akira Imai
Katsuya Hayano
Norio Hasegawa
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW558756B publication Critical patent/TW558756B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/30—Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/946—Step and repeat

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Memories (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW090116490A 2000-07-14 2001-07-05 Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device TW558756B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000215092A JP3983960B2 (ja) 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置

Publications (1)

Publication Number Publication Date
TW558756B true TW558756B (en) 2003-10-21

Family

ID=18710571

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090116490A TW558756B (en) 2000-07-14 2001-07-05 Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device

Country Status (4)

Country Link
US (2) US6403413B2 (https=)
JP (1) JP3983960B2 (https=)
KR (1) KR100698989B1 (https=)
TW (1) TW558756B (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI812962B (zh) * 2021-02-22 2023-08-21 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI918951B (zh) 2021-09-02 2026-03-21 以色列商應用材料以色列公司 檢測半導體取樣中的結構元件的局部形狀偏差的電腦化系統及電腦化方法和非暫態電腦可讀取儲存媒體

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US7233887B2 (en) * 2002-01-18 2007-06-19 Smith Bruce W Method of photomask correction and its optimization using localized frequency analysis
JP2003273245A (ja) * 2002-03-15 2003-09-26 Hitachi Ltd 半導体記憶装置
US6649945B1 (en) 2002-10-18 2003-11-18 Kabushiki Kaisha Toshiba Wiring layout to weaken an electric field generated between the lines exposed to a high voltage
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US8461038B2 (en) * 2011-03-02 2013-06-11 Texas Instruments Incorporated Two-track cross-connects in double-patterned metal layers using a forbidden zone
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JP2013254815A (ja) * 2012-06-06 2013-12-19 Ps4 Luxco S A R L 半導体装置およびその製造方法
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KR102248436B1 (ko) * 2014-05-23 2021-05-07 삼성전자주식회사 반도체 소자의 제조방법
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Publication number Priority date Publication date Assignee Title
TWI812962B (zh) * 2021-02-22 2023-08-21 日商鎧俠股份有限公司 半導體裝置及其製造方法
TWI918951B (zh) 2021-09-02 2026-03-21 以色列商應用材料以色列公司 檢測半導體取樣中的結構元件的局部形狀偏差的電腦化系統及電腦化方法和非暫態電腦可讀取儲存媒體

Also Published As

Publication number Publication date
JP2002031883A (ja) 2002-01-31
US20020155656A1 (en) 2002-10-24
KR20020007195A (ko) 2002-01-26
US20020005542A1 (en) 2002-01-17
KR100698989B1 (ko) 2007-03-26
JP3983960B2 (ja) 2007-09-26
US6403413B2 (en) 2002-06-11
US6750496B2 (en) 2004-06-15

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