TW498522B - Semiconductor device and its manufacture method - Google Patents

Semiconductor device and its manufacture method Download PDF

Info

Publication number
TW498522B
TW498522B TW090105543A TW90105543A TW498522B TW 498522 B TW498522 B TW 498522B TW 090105543 A TW090105543 A TW 090105543A TW 90105543 A TW90105543 A TW 90105543A TW 498522 B TW498522 B TW 498522B
Authority
TW
Taiwan
Prior art keywords
main plane
substrate
semiconductor wafer
semiconductor device
sealing resin
Prior art date
Application number
TW090105543A
Other languages
English (en)
Inventor
Hideko Ando
Hiroshi Kikuchi
Ikuo Yoshida
Toshihiko Sato
Tomo Shimizu
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW498522B publication Critical patent/TW498522B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01056—Barium [Ba]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Ceramic Capacitors (AREA)

Description

A7 、發明說明（！） tjg領域 ϋ »1* ϋ 1 I# ϋ ϋ Βϋ l_i I · I I (請先閱讀背面之注意事項再填寫本頁) 本發明係關於-半導體裳置及A 本發明係關於適用於—半導 支#，特別言之， 裝置且古—批#祕 κ^足有效技術，該半導骨渔 们 於該封装體中，倾“片…：
件係經載置於同一基板上。 導阮日曰片與被動7L 揭 公:::平::。98 號(u.s._ 體電路之半導體晶片、(:備下僅:^ 卜、十、八如Y、 僅％馬日曰片）< 熱發散至外部。 ^報所記述之封裝基板之態樣爲：在模& 形成之襯墊上，係經由焊錨 、土 4 ，、面 由¥錫孔冗以面朝下地安裝晶片。係 无於模組基板與晶片之間隙内之封 硯墊及焊錫孔穴。 山訂 二谷咨般之一個以上的電子裝置，係與晶片共同 杈組基板頂面。另外，係經由密封材料，以將用以 被封上述晶片與電子裝置之罩蓋固定在模組基板頂面，並 經由接著劑以將熱匯座固定於罩蓋頂面。於晶片頂面(内 面)人罩鬼底面之間隙内，係填充熱傳導材料，晶片所產 生的熱係透過此熱傳導材料及罩蓋以傳達至熱匯座。 經濟部智慧財產局員工消費合作社印製 上述公報所記述之封裝基板之另一態樣爲··於晶片之頂 面（内面）上，係經由兩面壓感性熱傳導接著磁帶，以與熱 匯座直接接合。於此態樣中，由於係去除用以密封晶片與 私子裝置之罩盍，故晶片之熱可更有效率地傳達至熱匯 座0 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） A7
經濟部智慧財產局員工消費合作社印製 對近年之高速L S ][而言 課題，所行對策之一爲：於安裝、木曰成馬重要的 大完|日&不、 日曰片 < 基板上安裝小型之 合里卵片電容器，以減低中周波區域之噪立。 於此情況下，係要求將電容 曰 以妒y、杰y J叱地靠近晶片配置， 以'%短連接兩者之配線。然而 u L 之發鼽景士 从、k々 U $成有鬲速LSI之晶片 下，：3作=:容器極度地靠近晶片配置之情況 中，而產生降低與基板之連接可靠性的問題。 又化 另外，對於如前述純記述之 罩 :'基板上之晶片與電容器之封裝體而言， 之尺寸容許誤差，必須供给多旦時’爲吸收罩 —抑， 、1、、。夕里的熱傳導材料，故若蔣 谷态極度地靠近晶片配置， 、 料會與電容器接觸。 」“片邊w出之熱傳導 其結果使得電容器不僅暴露於源自晶片 亦暴露於自熱料材制傳㈣高熱巾 ^ =靠性’而成爲更深-層的問題。再者；二： 導材科係由如Ag糊般之導電性材料所構成之情況下:、、 會產生經由熱傳導材料而使晶片與電 發i短路的問題。 4私谷茶I 本發明《目的在於提供_種技術，以提昇安裝於 之被動元件之連接可靠性。 ；日印片 本發明之另-目的在於提供另一種技術，以確保安裝於 驟 芸 JCCOL 材 且 之 亦 間 旁 5-
本紙張尺度賴+關家鮮(CNS)A4 (210 X 297 ) 1^---------t-------I ^---------___ (請先閱讀背面之注意事項再填寫本頁) 498522 A7 B7 五、發明說明（3 ) 晶片旁之被動元件之電可靠性。 ml ϋ n aj I 1 I n ·1 I -I ϋ (請先閱讀背面之注意事項再填寫本頁)
…由本説明書之記述及所附圖示，可明確知悉本發明之寸 述及其他目的、與本發明之嶄新特徵。 J 於本申請錢揭示之發明中，兹簡單説明具代表之 概要如次。 本發明之半導體裝置係具有備置配線層之基板、面朝 地安裝於該基板主平面上之半導體晶片、安裝於該基板主 平面上之被動元件、填充於該半導體晶片主平面與該基板 王平面之間隙内之密封樹脂、密封該半導體晶片與該被動 疋件〈罩蓋、以及填充於該罩蓋與該半導體晶片間之散傳 等材料，而該被動元件係配置於該密封樹脂所附著之區域 内，且至少其一部份係經該密封樹脂所覆蓋。 本發明之半導體裝置之製造方法係具有下述步驟： 曰（=)於備置配線層之基板主平面上，面朝下地安裝半導體 (b)於該基板主平面上安裝該半導體晶片之區域旁安裝被 動元件； 6(c)於該半導體晶片主平面與該基板主平面之間隙内填充 密封樹脂，以該密封樹脂塗覆該被動元件； 經濟部智慧財產局員工消費合作社印製 (d )於該半導體晶片之頂面供給熱傳導材料；以及 (〇於該半導體晶片之頂面，經由該熱傳導材料以固定用 以密封該半導體晶片與該被動元件之罩蓋。 圖式簡單説明 圖1爲本發明一實施型態之半導體裝置之平面圖。 -6 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 公釐） 498522 A7
五、發明說明（4 ) 圖2爲沿圖1之II-II線之截面圖。 圖3爲圖2之重要部份放大截面圖。 (請先閱讀背面之注意事項再填寫本頁) 圖4舄圖示記憶晶片與晶片電容器之連接狀態之圖。 圖5爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖6爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖7(a)爲晶片電容器之平面圖。 圖7(b)爲沿圖7(a)之A-A線之截面圖。 圖8爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖9爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖10爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖11爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖12爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 經濟部智慧財產局員工消費合作社印製 圖13爲圖示本發明一實施型態之半導體裝置製造方法之 截面圖。 圖14爲圖示本發明另一實施型態之半導體裝置之平面 圖。 圖15爲圖示本發明另一實施型態之半導體裝置之平面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 498522 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（5 ) 圖。 圖16爲圖示本發明另一實施型態之半導體裝置之截面 圖。 圖Π爲圖示本發明另一實施型態之半導體裝置之重要部 份放大截面圖。 較佳具體實施例之敘述 以下係基於圖示以詳細説明本發明之實施型態。又，在 用以説明實施型態之整個圖中，同一啷件係編爲同一符 號，以省略重覆的説明。 (實施型態1) 圖1爲本發明一實施型態之半導體裝置之平面圖，圖2爲 沿圖1之II-II線之截面圖，圖3爲圖2之重要部份放大截面 圖。 本實施型態爲安裝記憶晶片1之封裝體，於該記憶晶片i 中例如係形成高速微處理機（MPU : miCr〇processor unit)。 此半導體裝置之封裝基板2係由陶瓷所構成，其内部係 形成由電源配線及接地配線所構成之多層配線3。另外， 封裝基板2之主平面（頂面）及底面係形成數個電極襯墊4、 5，彼等係自上述配線3連接電力。配線3及電極襯墊4、5 係含w(鎢），而電極襯墊4、5之表面係經施行(鎳）及 A u(金）之電鍍。 係藉由倒裝晶片之方式，以將記憶晶片i面朝下地安裝 於封裝基板2之主平面中央部份上。亦即，係經由連接至 記憶晶片i主平面(底面)之數個焊錫隆起物(隆起電極％， —.ΓΙΙΓ-----•-裝---- (請先閱讀背面之注意事項再填寫本頁) 訂： -8-
發明說明（ 經濟部智慧財產局員工消費合作社印製 、使"己匕曰曰片1自封裝基板2主平面之前述電極襯墊4連接 電力。 w於記憶^片1旁係安裝數個晶片電容器7。此等晶片電容 态7係沿著記憶晶片1之外圍配置，經由焊錫8以自封裝基 ,2王+平、面心I述電極襯墊4連接電力。如圖4所示，此等 %各w 7係木封裝基板2之電源配線與接地配線之間並 地連接’減低記憶晶片i在驅動時產生的噪音，而進行 高速的作動。 此半導體裝置（封裝體）之外部連接端子係由數個焊錫隆 起物9所構成’而彼等焊錫隆起物9係連接至封裝基板2底 面（電極觀墊5。相較於連接至記憶晶片丨主平面之前述焊 、易隆I物6此等焊錫隆起物9係由具較低熔點之焊錫材料 所構成係、、二由此等焊錫隆起物9，以使半導體裝置安裝 於電腦之母板等上。 於記憶晶片1主平面（底面）與封裝基板2主平面之間隙 内，係蜞充作爲密封材料之底層填料樹脂（密封樹脂）丨〇， 其係用以保護兩者之連接部份與緩和熱應力。此底層填料 樹脂10例如係由填充有矽氧之環氧樹脂等絕緣材料所構 成。 底層填料樹脂10之外緣係延伸至記憶晶片丨之外側，全 面復盍住安裝於記憶晶片！旁之晶片電容器7。另外，於晶 片電容器7底面與封裝基板2主平面之間隙内，亦填充底層 填料樹脂10之一部份。亦即，底層填料樹脂1〇係填充於記 憶晶片1及晶片電容器7各自的底面、與封裝基板2主平面 ί^.--------Μ —— (請先閱讀背面之注意事項再填寫本頁) 訂· A7 B7 五、發明說明（7 經濟部智慧財產局員工消費合作社印製 之間隙内，同時全面覆蓋住晶片電容器7。 系猎由覆盖封裝基板2整個 密封安裝於封裝基板2主平面 /H11’以 门 之^ 5己丨思日曰片1及晶只雷交盟 7。係經由接著劑12，以使 “-奋备 基板2之主平面上。&此罩盖此腳邵山固定於封裳 材料13，豆2面一己恤晶片1頂面之間隙内係填充熱傳導 /、’、用以將1己憶晶片1在驅動時產生的熱透過罩 至：：。此熱傳導材料13例如係由如岣糊般熱 傅導率同 < 導電材料所構成。 如後所述，於封裝體之組裝步財，在填充熱傳導材料 至记f思曰曰片1與罩蓋丨丨之間時，爲吸收罩蓋丨1之尺寸 許誤差⑽部Ua之高度偏差等），會供給多量的熱傳導π 料13。爲此，熱傳導材料13之外緣係延伸至記憶晶片工之 外側，其一部份係到達安裝於記憶晶片1旁之前述晶片電 容器7頂面。 、然而，因爲於本實施型態之半導體裝置中，由絕緣材料 所構成之底層填料樹脂1〇不僅填充於記憶晶片丨與封裝基 板2之間隙内，而且全面覆蓋住晶片電容器7，因此並無發 生下述情事之虞：經由自記憶晶片丨外側溢出的導電性 傳導材料13，使晶片電容器7之間產生短路，或使晶片 各益7與記憶晶片1之間產生短路。 另外’因爲於本實施型態之半導體裝置中，配置於記 晶片1旁之晶片電容器7係經底層填料樹脂丨〇所塗覆，因 片電容器7與封裝基板2之連接強度高。由是可抑制晶 容 材 熱 電 1It iI (請先閱讀背面之注意事項再填寫本頁) · 曰曰 憶 此 片 -10 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 498522 A7
五、發明說明（8 ) 經濟部智慧財產局員工消費合作社印製 電容器7與電極4之連接可靠性降低，而提昇晶片電容器7 之連接壽命。 其次，利用圖5至圖13，依步驟順序説明以上述方式構 成之本實施型態半導體裝置之製造方法。 就封裝體之組裝而言’首先係如圖5所示’預先將坪錫 隆起物6連接至記憶晶片丨之主平面上，決定該焊錫隆起物 6於封裝基板2主平面之電極襯墊4上之位置後，藉由倒轉 焊錫隆起物6,以將記憶晶片丨面朝下地安裝於封裝基板2 之主平面中央部份上。焊錫隆起物6例如係由含2重量％811 <Pb-Sn合金（液相線溫度爲32〇τ s 325O)所構成。 其次，洗淨封裝基板2之主平面，去除焊劑殘渣後，如 圖6所示，係於記憶晶片丨旁之電極襯墊4上安裝晶片電容 器7。例如於圖7中所示者，在晶片電容器7中，於長方形 之相對兩邊上係藉由電鍍形成電極2〇a、2〇b，故其内部係 夾持含鈦酸鋇（BaTi〇3)之高電介質21，薄片狀之Ni電極22 係互相不同地重合。就安裝晶片電容器7而言，於電極 20a、20b之表面上，預先以電鍍形成焊錫8，同時於封裝 基板2之電極襯墊4表面上，先以絲網印刷等塗布預備焊 錫，其次決定電極2〇a、20b於電極襯墊4上之位置後，將 焊錫8倒轉。焊錫8例如係由含3重量％Ag之Sn_Ag合金（熔 點爲221°C)所構成。又，於封裝基板2上安裝記憶晶片1與 晶片電容器7之順序亦可與上述相反。另外，決定安裝記 憶晶片1與晶片電容器7於電極襯墊4上之位置後，亦可同 時一併倒轉焊錫隆起物6與焊錫8。 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（21Q χ 297公董） II----„-------裝· — I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 498522 A7 __B7 五、發明說明（ /其’人，再度洗淨封裝基板2之主平面，去除焊劑殘渣 後，如圖8所示，將底層填料樹脂1〇供給至記憶晶片丨之外 園。例如可使分散器30沿著記憶晶片1之邊緣進行掃描， 並供給底層填料樹脂1〇 〇 田 其次’爲提鬲底層填料樹脂丨0之流動性，將封裝基板2 加，至約70°C。藉此方式，如圖9所示，底層填料樹脂⑺ 係藉由毛細管現象以填充於記憶晶片！及晶片電容器7各自 的底面。另外，當底層填料樹脂1〇之供給量適當時，晶片 私春备7係經底層％料樹脂1 〇所全面覆蓋。其後，將底層 填料樹脂10烘烤至約15〇°C，使其硬化。 以此方式’於$憶晶片1之底面填充底層填料樹脂1 〇 時，同時亦以底層填料樹脂1 〇全面覆蓋晶片電容器7，由 是可簡化步驟。 亦可使用底層填料樹脂10以外的塗覆材料，以塗覆晶片 %容态7。亦即，亦可如圖1 〇所示，於記憶晶片丨及晶片電 容器7之底面填充底層填料樹脂（第1密封樹脂）1〇，繼而以 另外準備的塗層樹脂（第2密封樹脂）14塗覆晶片電容器7 後’同時烘烤底層填料樹脂10及塗層樹脂14以使彼等硬 化。於此情況下，因底層填料樹脂1〇及塗層樹脂14係經一 骨豆化’故可提昇晶片電容器7與封裝基板2之連接強度。另 外，可使塗覆晶片電容器7之樹脂之厚度變薄。由於利用 毛細管現象以填充底層填料樹脂10，故係使用黏度低的樹 月旨，而塗層樹脂14係用以形成極薄的塗膜，較底層填料樹 脂10含較少的矽氧填料，且相較於底層填料樹脂1〇，係另 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ίτ--------φ·裝--- (請先閱讀背面之注意事項再填寫本頁) il· 498522 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（10 ) 行使用黏度低之彡衣氧樹脂、硬自同清漆等。 其次，如圖1 1所示，係使用未經圖示之分散器等，將熱 傳導材料（Ag糊）13供給至記憶晶片}之頂面上。爲吸收罩 盍11之尺寸客許誤差（腳部u a之高度偏差等），係供給較必 要量多些許的熱傳導材料13。另外，此時係將接著劑12供 給至封裝基板2主平面之周圍部份。 其次，如圖12及圖13所示，決定罩蓋n於封裝基板2上 之位置，加熱硬化熱傳導材料13及接著劑12，藉此將罩蓋 11固足於封裝基板2上。此時，熱傳導材料丨3之外緣雖到 達晶片電容器7之頂面，惟如前所述，因晶片電容器7係經 底層填料樹脂10所覆蓋，故並不會因熱傳導材料13而使晶 片電容器7之間產生短路、或使晶片電容器7與記憶晶片i 之間產生短路。 其後，將由低熔點之pb_Sn共晶合金所構成之焊錫孔穴 (未、、二圖示），供給至封裝基板2底面之電極襯塾5表面後， 知绛錫孔穴倒轉，於電極襯墊5之表面上形成焊錫隆起物 9由疋元成先削圖1至圖4所示之半導體裝置。 ^於本實施型態中，係針對在封裝基板2上僅安裝1個記憶 晶片、1之情況加以説明，惟亦可適用於安裝2個以上記憶晶 片1之情況。舉例而言，圖14爲於封裝基板2上安裝3個記 憶^片1之例示，而圖15爲安裝4個記憶晶片丨之例示。於 此等^ /兄下，亦要求縮短晶片電容器7與記憶晶片i之間的 配線(3)，故係將晶片電容器7極度地靠近記憶晶片丄配置， 准筹曰由以底層填料樹脂丨〇覆蓋晶片電容器7，可達成提昇 i.r. ^ — (請先閱讀背面之注意事項再填寫本頁) ·
A7 ---------- B7 —_ 五、發明說明（Η) 連接壽命、及防止短路不良之目的。 (實施型態2) I一^ — In-----1 ^ -11 (請先閱讀背面之注意事項再填寫本頁) 万、則述實她型怨！中’係針對適用於以罩蓋工i密封記憶 晶片1及晶片電容器7之封裝體之情況加以説明，惟本發明 亦可適用於例如於圖16所示之封裝體，其係於記憶晶片i 之I、面上，、纟k由熱傳導材料16以連接散熱片（熱匯座）15、 或平坦之放熱板。另外，亦可適用於熱傳導材料16例如係 由如B N (氮化硼）和鋁氧般熱傳導率高之絕緣性材料所構成 之情況。 於熱傳導材料16係由絕緣性材料所構成之情況下，雖不 會產生短路不良之問題，惟於將晶片電容器7配置在記憶 晶片1旁之情況下，會出現因記憶晶片丨之發熱而降低連接 哥命之問題。因此，於此情況下，如圖17所示，藉由於晶 片％卷益7之下方填充底層填料樹脂10，可提高晶片電容 器7與電極4之連接強度，並提昇晶片電容器7之連接壽 命。 經濟部智慧財產局員工消費合作社印製 另外，於本實施型態之封裝體中，在熱傳導材料16係由 .導電性材料所構成之情況下，亦會因熱傳導材料16供給量 之偏差而使熱傳導材料16溢出記憶晶片1之外側，而出現 短路不良之問題。因此，於此情況下，亦藉由以底層填料 樹脂10塗覆晶片電容器7，以防止經由溢出記憶晶片1外側 之熱傳導材料16使晶片電容器7之間產生短路、或使晶片 電容器7與記憶晶片1之間產生短路之不良現象。 以上係基於前述實施型態，以具體説明本發明之發明人 -14- 本紙枭八及週用中國國家標準（CNS)A4規格（210 X 297公一 ''〜-- A7N發明說明 所實行之本發明 未超出其要旨之範圍内：：：：：定於前述實施型態，於 於前述實施型態中， ^㊁地可進行各種的改變。 装體之情況加以；明：惟：對適用於安裝記憶晶片1之封 廣泛地適科在形成有限^此，—般而言，亦 旁配置晶片電容器之高之高迷⑶之半導體晶 發明置電阻元件等被‘動元件之封裝體 果簡二:::揭μ發明中’兹將以具代表性者所得 旁封，^ 片之古、、w 70牛不曰直接暴露於源自半導體晶 昇連故可抑制被動元件之連接可靠性降低，並提 傳I:料=充ί半導體晶片與罩蓋(抑或放熱板)間 r塗受t f “生材料所構成之情況下，藉由以密封樹 可防止被動元件之間產生短路、或使被 70人半導體晶片之間產生短路之不良現象。 可 片 效 片 之熱 封樹 ---·_----裝 i I (請先閱讀背面之注意事項再填寫本頁) 訂： 經濟部智慧財產局員工消費合作社印製 -15-

Claims (1)

  1. 498522 第090105543號專利申請案 中文申請專利範圍修正本(91年6月） A8 B8) C8, D8 攀 日倐正/f正/補览 々、申請專利範圍 1. 一種半導體裝置，其特徵為具有備置配線層之基板、面 朝下地安裝於該基板主平面上之半導體晶片、安裝於該 基板主平面上之被動元件、填充於該半導體晶片主平面 與該基板主平面之間隙内之密封樹脂、密封該半導體晶 片與該被動元件之罩蓋、以及填充於該罩蓋與該半導體 晶片間之熱傳導材料、其於該被動元件係配置於該密封 樹脂所附著之區域内，且至少其頂面係經該密封樹脂所 覆蓋。 2. —種半導體裝置，其特徵為具有備置配線層之基板、面 朝下地安裝於該基板主平面上之半導體晶片、安裝於該 基板主平面上之被動元件、填充於,該半導體晶片主平面 與該基板主平面之間隙内之密封樹脂、以及經由熱傳導 材料接合於該半導體晶片之頂面上之散熱體，其於該被 動元件係配置於該密封樹脂所附著之區域内，且至少其 頂面係經該密封樹脂所覆蓋。 3. 根據申請專利範圍第1或2項之半導體裝置，其中該熱傳 導材料為導電性材料。 4. 根據申請專利範圍第1或2項之半導體裝置，其中該熱傳 導材料為絕緣性材料。 5. 根據申請專利範圍第1或2項之半導體裝置，其中該被動 元件為晶片電容器。 一 6. 根據申請專利範圍第1或2項之半導體裝置，其中該半導 體晶片係經由隆起（bump)電極以安裝於該基板之主平面 上。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
    裝
    498522
    7.根據申請專利範圍第1或2項之半導體裝置，其中該基板 <王平面上係安裝數個半導體晶片，而該被動元件係配 置於該等數個半導體晶片之間隙内。 8·根據申請專利範圍第2項之半導體裝置，其中該密封樹 脂係填充於該被動元件與該基板主平面之間隙内。 9· 一種半導體裝置之製迤方法，其係具有下述步驟： (a) 於備置配線層之基板主平面上，面朝下地安裝半 導體晶片； (b) 於該基板主平面上安裝該半導體晶片之區域旁安 裝被動元件； (c) 於該半導體晶片主平面與該基板主平面之間隙内 填充密封樹脂，並以該密封樹脂塗覆該被動元件；以及 (d )於該半導體晶片之頂面，經由熱傳導材料以固定 用以密封該半導體晶片與該被動元件之罩蓋。 10. —種半導體裝置之製造方法，其係具有下述步驟： (a) 於備置配線層之基板主平面上，面朝下地安裝半 導體晶片； (b) 於該基板主平面上安裝該半導體晶片之區域旁安 裝被動元件； (c) 於該半導體晶片主平面與該基板主平面之間隙内 填充密封樹脂，並以該密封樹腊塗覆該被動元件；以及 (d) 於該半導體晶片之頂面上.，經由熱傳導材料以固 定教熱體。 11·根據申請專利範圍第9或10項之半導體裝置之製造方 -2- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 498522 8 8 8 8 A B c D t、申請專利範圍 法，其中該步騾（c)係具有下述步驟：於該半導體晶片主 平面與該基板主平面之間隙内填充第1密封樹脂；以及 以第2密封樹脂塗覆該被動元件。 12.根據申請專利範圍第1或2項之，半導體裝置，其中該半導 體晶片之主平面與相反側之背面並不為該密封樹脂所覆 蓋，而係與該熱傳導材料直接接觸。 -3- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
TW090105543A 2000-03-17 2001-03-09 Semiconductor device and its manufacture method TW498522B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000076709A JP2001267473A (ja) 2000-03-17 2000-03-17 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW498522B true TW498522B (en) 2002-08-11

Family

ID=18594407

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090105543A TW498522B (en) 2000-03-17 2001-03-09 Semiconductor device and its manufacture method

Country Status (4)

Country Link
US (1) US6433412B2 (zh)
JP (1) JP2001267473A (zh)
KR (1) KR20010091916A (zh)
TW (1) TW498522B (zh)

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19960246A1 (de) * 1999-12-14 2001-07-05 Infineon Technologies Ag Gehäuseanordnung eines Halbleiterbausteins
KR100779345B1 (ko) * 2001-08-17 2007-11-23 앰코 테크놀로지 코리아 주식회사 반도체패키지
US6573592B2 (en) * 2001-08-21 2003-06-03 Micron Technology, Inc. Semiconductor die packages with standard ball grid array footprint and method for assembling the same
KR100708045B1 (ko) * 2001-09-05 2007-04-16 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
KR100443399B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 보이드가 형성된 열 매개 물질을 갖는 반도체 패키지
US6882041B1 (en) * 2002-02-05 2005-04-19 Altera Corporation Thermally enhanced metal capped BGA package
US6680530B1 (en) * 2002-08-12 2004-01-20 International Business Machines Corporation Multi-step transmission line for multilayer packaging
DE10238523B4 (de) * 2002-08-22 2014-10-02 Epcos Ag Verkapseltes elektronisches Bauelement und Verfahren zur Herstellung
US6998532B2 (en) 2002-12-24 2006-02-14 Matsushita Electric Industrial Co., Ltd. Electronic component-built-in module
JP2004253738A (ja) * 2003-02-21 2004-09-09 Toshiba Corp パッケージ基板及びフリップチップ型半導体装置
KR20060079754A (ko) * 2003-06-25 2006-07-06 어드밴스드 인터커넥트 테크놀로지스 리미티드 반도체 패키지용 칩 패드가 라우트된 리드 프레임
US6888238B1 (en) * 2003-07-09 2005-05-03 Altera Corporation Low warpage flip chip package solution-channel heat spreader
TWI229928B (en) * 2003-08-19 2005-03-21 Advanced Semiconductor Eng Semiconductor package structure
JP3819901B2 (ja) * 2003-12-25 2006-09-13 松下電器産業株式会社 半導体装置及びそれを用いた電子機器
JP3809168B2 (ja) * 2004-02-03 2006-08-16 株式会社東芝 半導体モジュール
JP3999759B2 (ja) * 2004-04-02 2007-10-31 富士通株式会社 基板及び電子機器
DE102004020204A1 (de) * 2004-04-22 2005-11-10 Epcos Ag Verkapseltes elektrisches Bauelement und Verfahren zur Herstellung
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
DE102005008512B4 (de) 2005-02-24 2016-06-23 Epcos Ag Elektrisches Modul mit einem MEMS-Mikrofon
DE102005008511B4 (de) 2005-02-24 2019-09-12 Tdk Corporation MEMS-Mikrofon
US7746656B2 (en) * 2005-05-16 2010-06-29 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US7518224B2 (en) * 2005-05-16 2009-04-14 Stats Chippac Ltd. Offset integrated circuit package-on-package stacking system
US20060278170A1 (en) * 2005-06-10 2006-12-14 Wildlife Solutions, Inc. Method for removing unwanted animals and their attractants
KR20070016383A (ko) * 2005-08-03 2007-02-08 삼성전자주식회사 칩형 전기 소자 및 이를 포함하는 액정 표시 모듈
WO2007036994A1 (ja) * 2005-09-28 2007-04-05 Spansion Llc 半導体装置およびその製造方法並びにフィルムの製造方法
CN100373599C (zh) * 2005-09-29 2008-03-05 威盛电子股份有限公司 无凸块式芯片封装体
DE102005050398A1 (de) * 2005-10-20 2007-04-26 Epcos Ag Gehäuse mit Hohlraum für ein mechanisch empfindliches elektronisches Bauelement und Verfahren zur Herstellung
DE102005053765B4 (de) 2005-11-10 2016-04-14 Epcos Ag MEMS-Package und Verfahren zur Herstellung
DE102005053767B4 (de) 2005-11-10 2014-10-30 Epcos Ag MEMS-Mikrofon, Verfahren zur Herstellung und Verfahren zum Einbau
JP2007134540A (ja) * 2005-11-11 2007-05-31 Murata Mfg Co Ltd 半導体装置およびその製造方法
KR100718169B1 (ko) * 2006-01-12 2007-05-15 한국과학기술원 니켈 표면 처리된 전자부품과 무전해 니켈 표면 처리된전자부품의 접합방법
JP4874325B2 (ja) * 2006-02-24 2012-02-15 富士通株式会社 半導体装置
JP4691455B2 (ja) 2006-02-28 2011-06-01 富士通株式会社 半導体装置
US20080001282A1 (en) * 2006-06-30 2008-01-03 Mitul Modi Microelectronic assembly having a periphery seal around a thermal interface material
JP4963890B2 (ja) * 2006-06-30 2012-06-27 太陽誘電株式会社 樹脂封止回路装置
EP1914798A3 (en) * 2006-10-18 2009-07-29 Panasonic Corporation Semiconductor Mounting Substrate and Method for Manufacturing the Same
US8163600B2 (en) * 2006-12-28 2012-04-24 Stats Chippac Ltd. Bridge stack integrated circuit package-on-package system
KR100850897B1 (ko) * 2007-01-22 2008-08-07 주식회사 네패스 수동소자가 매립된 반도체 장치 및 그 제조 방법
KR101011199B1 (ko) 2007-11-01 2011-01-26 파나소닉 주식회사 실장 구조체
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置
JP4492695B2 (ja) * 2007-12-24 2010-06-30 株式会社デンソー 半導体モジュールの実装構造
US7906376B2 (en) * 2008-06-30 2011-03-15 Intel Corporation Magnetic particle-based composite materials for semiconductor packages
US8415809B2 (en) * 2008-07-02 2013-04-09 Altera Corporation Flip chip overmold package
JP4555369B2 (ja) * 2008-08-13 2010-09-29 富士通メディアデバイス株式会社 電子部品モジュール及びその製造方法
JP4560113B2 (ja) * 2008-09-30 2010-10-13 株式会社東芝 プリント回路板及びプリント回路板を備えた電子機器
JP4900432B2 (ja) * 2009-07-21 2012-03-21 株式会社村田製作所 樹脂封止型電子部品の製造方法及び樹脂封止型電子部品の集合体
JP5625340B2 (ja) 2009-12-07 2014-11-19 富士通セミコンダクター株式会社 半導体装置とその製造方法
GB2477492B (en) * 2010-01-27 2014-04-09 Thales Holdings Uk Plc Integrated circuit package
JP2011176112A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp 半導体集積回路及びその製造方法
US8217500B1 (en) * 2010-05-07 2012-07-10 Altera Corporation Semiconductor device package
TWI401773B (zh) * 2010-05-14 2013-07-11 Chipmos Technologies Inc 晶片封裝裝置及其製造方法
TW201225238A (en) * 2010-07-26 2012-06-16 Unisem Mauritius Holdings Ltd Lead frame routed chip pads for semiconductor packages
JP5573645B2 (ja) * 2010-12-15 2014-08-20 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US8624359B2 (en) * 2011-10-05 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package and method of manufacturing the same
JP5861580B2 (ja) * 2012-07-09 2016-02-16 株式会社ソシオネクスト 半導体装置及び半導体装置製造方法
US9287194B2 (en) * 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
DE102013106353B4 (de) * 2013-06-18 2018-06-28 Tdk Corporation Verfahren zum Aufbringen einer strukturierten Beschichtung auf ein Bauelement
US9355966B2 (en) * 2013-07-08 2016-05-31 Avago Technologies General Ip (Singapore) Pte. Ltd. Substrate warpage control using external frame stiffener
CN104575584B (zh) 2013-10-23 2018-11-30 钰创科技股份有限公司 具有嵌入式内存的系统级封装内存模块
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
CN204993854U (zh) * 2015-06-24 2016-01-20 瑞声声学科技(深圳)有限公司 Mems麦克风
JP6569375B2 (ja) * 2015-08-11 2019-09-04 株式会社ソシオネクスト 半導体装置、半導体装置の製造方法及び電子装置
FR3055943B1 (fr) * 2016-09-15 2020-10-02 Valeo Vision Cablage d'une source lumineuse de haute resolution
WO2018164160A1 (ja) * 2017-03-10 2018-09-13 株式会社村田製作所 モジュール
US10217649B2 (en) * 2017-06-09 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an underfill barrier
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
JP6645487B2 (ja) * 2017-10-30 2020-02-14 セイコーエプソン株式会社 プリント回路板
CN113574661A (zh) * 2019-02-04 2021-10-29 索尼互动娱乐股份有限公司 电子设备、半导体器件、绝缘片和半导体器件制造方法
KR20230041220A (ko) * 2021-09-17 2023-03-24 삼성전자주식회사 반도체 패키지
CN216749870U (zh) * 2021-12-10 2022-06-14 云南中宣液态金属科技有限公司 一种用于芯片散热的液态金属封装结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846098A (ja) 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JP3724979B2 (ja) * 1999-04-27 2005-12-07 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
KR20010091916A (ko) 2001-10-23
JP2001267473A (ja) 2001-09-28
US6433412B2 (en) 2002-08-13
US20010050428A1 (en) 2001-12-13

Similar Documents

Publication Publication Date Title
TW498522B (en) Semiconductor device and its manufacture method
TW392262B (en) Electric parts and semiconductor device and the manufacturing method thereof, and the assembled circuit board, and the electric device using the same
TWI236117B (en) Semiconductor package with a heat sink
US6518666B1 (en) Circuit board reducing a warp and a method of mounting an integrated circuit chip
US6734553B2 (en) Semiconductor device
JP3633559B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
TWI253701B (en) Bump-less chip package
TWI255532B (en) Flip-chip ball grid array semiconductor package with heat-dissipating device and method for fabricating the same
TWI379364B (en) Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
US6756668B2 (en) Semiconductor package having thermal interface material (TIM)
TWI237364B (en) Flip chip package with anti-floating mechanism
KR20020018133A (ko) 전자 장치 및 그 제조 방법
JP4899406B2 (ja) フリップチップ型半導体装置
TW201123371A (en) Semiconductor device and manufacturing method thereof
JP3891678B2 (ja) 半導体装置
JP3367554B2 (ja) フリップチップパッケージ
JP2001298115A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
CN102714195A (zh) 半导体装置
TW587325B (en) Semiconductor chip package and method for manufacturing the same
TW520559B (en) Flip chip assembly and method for producing the same
JPH11214448A (ja) 半導体装置および半導体装置の製造方法
US6291893B1 (en) Power semiconductor device for “flip-chip” connections
JPH0661368A (ja) フリップチップ型半導体装置
TW400587B (en) Multi-chip chip scale package
JP2000223627A (ja) フリップチップパッケージ

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees