US20010050428A1 - Semiconductor device and a method of manufacturing the same - Google Patents
Semiconductor device and a method of manufacturing the same Download PDFInfo
- Publication number
- US20010050428A1 US20010050428A1 US09/800,589 US80058901A US2001050428A1 US 20010050428 A1 US20010050428 A1 US 20010050428A1 US 80058901 A US80058901 A US 80058901A US 2001050428 A1 US2001050428 A1 US 2001050428A1
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- Prior art keywords
- main face
- chip
- substrate
- face
- semiconductor chip
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 65
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- 239000011347 resin Substances 0.000 claims abstract description 61
- 238000007789 sealing Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
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- 229910000679 solder Inorganic materials 0.000 description 21
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 4
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- 239000006185 dispersion Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
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- 238000004140 cleaning Methods 0.000 description 2
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- 230000004907 flux Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
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- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, particularly to a technology effectively applied to a semiconductor device having a package mounted with a semiconductor chip and a passive element on the same substrate.
- Japanese Patent Laid-Open No. 46098/1996 U.S. Pat. No. 5,533,256 discloses a package having a heat sink for radiating to outside, heat of a semiconductor chip formed with an integrated circuit (hereinafter, simply referred to as chip).
- a chip is mounted, by face down bonding, on a pad formed at an upper face of a module substrate via a solder ball.
- the pad and the solder ball are sealed by a seal member filled in a clearance between the module substrate and the chip.
- One or more of electronic devices such as a decoupling condenser is mounted along with the chip at the upper face of the module substrate. Further, a cap for sealing the chip and the electronic devices are fixedly attached to the upper face of the module substrate via the seal member and the heat sink is fixedly attached to an upper face of the cap via an adhering agent. A clearance between an upper face (rear face) of the chip and a lower face of the cap is filled with a heat conductive member and heat generated at the chip is transmitted to the heat sink via the heat conductive member and the cap.
- the heat sink is directly bonded to the upper face (rear face) of the chip via a both face pressure-sensitive heat-conductive adhering tape. According to the mode, a cap for sealing the chip and the electronic devices is eliminated and accordingly, heat of the chip is transmitted to the heat sink further efficiently.
- the condenser is arranged as proximate as possible to the chip to thereby shorten wirings connecting both.
- a heat generating amount of the chip formed with the high-speed LSI is large and accordingly, when the condenser is arranged at an extreme proximity of the chip, the condenser is exposed to an abrupt temperature change in operating the chip and a deterioration in connection reliability between the condenser and the substrate poses a problem.
- the condenser is not only exposed to radiation heat from the chip but is exposed to intense heat conducted from the heat conductive member and the deterioration of the connection reliability in connecting to the substrate poses further serious problem.
- the heat conductive member comprises an electricity conductive material such as an Ag paste, there also poses a problem that the chip and the condenser or the condensers are shortcircuited via the heat conductive member.
- a semiconductor device comprising a substrate having a wiring layer, a semiconductor chip mounted onto a main face of the substrate in face down bonding, a passive element mounted onto the main face of the substrate, a seal resin filled between a main face of the semiconductor chip and the main face of the substrate, a cap for sealing the semiconductor chip and the passive element, and a heat conductive member filled between the cap and the semiconductor chip, wherein the passive element is arranged in an area coated with the seal resin and at least a portion thereof is covered by the seal resin.
- FIG. 1 is a plane view of a semiconductor device according to an embodiment of the invention.
- FIG. 2 is a sectional view taken along a line II-II of FIG. 1;
- FIG. 3 is a sectional view enlarging essential portions of FIG. 2;
- FIG. 4 is a diagram showing a state of connecting a memory chip and chip condensers
- FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device constituting the one embodiment of the invention.
- FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 7A is a plane view of a chip condenser
- FIG. 7B is a sectional view taken along a line A-A of FIG. 7A;
- FIG. 8 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 9 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 11 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 12 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 13 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention.
- FIG. 14 is a plane view of a semiconductor apparatus according to other embodiment of the invention.
- FIG. 15 is a plane view of a semiconductor apparatus according to other embodiment of the invention.
- FIG. 16 is a plane view of a semiconductor apparatus according to other embodiment of the invention.
- FIG. 17 is a sectional view enlarging essential portions of a semiconductor apparatus constituting other embodiment of the invention.
- FIG. 1 is a plane view of a semiconductor device according to the embodiment
- FIG. 2 is a sectional view taken along a line II-II of FIG. 1
- FIG. 3 is a sectional view enlarging essential portions of FIG. 2.
- the semiconductor device is, for example, a package for mounting a memory chip 1 formed with a high-speed cash memory for a high-speed microprocessor (MPU: ultra small operation processing unit).
- MPU microprocessor
- a package substrate 2 of the semiconductor device is constituted by ceramic and at inside thereof, there are formed a plurality of layers of wirings 3 constituting a wiring for signal, a power source wiring and a ground wiring. Further, a main face (upper face) and a lower face of the package substrate 2 are formed with pluralities of electrode pads 4 and 5 electrically connected to the wirings 3 .
- the wiring 3 and the electrode pads 4 and 5 comprise W (tungsten) and surfaces of the electrode pads 4 and 5 are coated with a plating of Ni (nickel) and Au (gold).
- a central portion of the main face of the package substrate 2 is mounted with the memory chip 1 in face down bonding by a flip chip bonding system. That is, the memory chip 1 is electrically connected to the electrode pads 4 at the main face of the package substrate 2 via a plurality of solder bumps (bump electrodes) 6 connected to a main face (lower face) of the memory chip 1 .
- solder bumps bump electrodes
- a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1 .
- the chip condensers 7 are arranged along an outer periphery of the memory chip 1 and are electrically connected to the electrode pads 4 at the main face of the package substrate 2 via solder 8 .
- the chip condensers 7 are connected in parallel between the power source wiring and the ground wiring of the package substrate 2 and realizes high-speed operation by reducing noise caused in driving the memory chip 1 .
- the electrode pads 5 at the lower face of the package substrate 2 are connected with a plurality of solder bump 9 constituting outside connecting terminals of the semiconductor device (package).
- the solder bumps 9 comprise a solder material having a melting point lower than that of the solder bumps 6 connected to the main face of the memory chip 1 .
- the semiconductor device is mounted to a mother board of a computer via the solder bumps 9 .
- underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions for connecting the both and relaxation of thermal stress.
- the underfill resin 10 comprises, for example, an insulating material such as epoxy resin filled with silica.
- An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted to vicinities of the memory chip 1 . Further, portions of the underfill resin 10 are filled also to clearances between lower faces of the chip condensers 7 and the main face of the package substrate 2 . That is, the underfill resin 10 is filled in the clearances between the memory chip 1 and the respective lower faces of the condensers 7 and the main face of the package substrate 2 .
- the memory chip 1 and the chip condenser 7 mounted to the main face of the package substrate 2 are sealed by a cap 11 made of ceramic and covering a total of the main face of the package substrate 2 .
- Leg portions 11 a of the cap 11 are fixedly attached to the main face of the package substrate 2 via an adhering agent 12 .
- a clearance between a lower face of the cap 11 and the upper face of the memory chip 1 is filled with a heat conductive member 13 for radiating heat generated in driving the memory chip 1 to outside via the cap 11 .
- the heat conductive member 13 is constituted by an electricity conductive material having high heat conductivity such as Ag paste.
- the underfill resin 10 constituted by an insulating material is not only filled to the clearance between the memory chip 1 and the package substrate 2 but also covers entire faces of the chip condensers 7 and accordingly, there is no concern of shortcircuiting the chip condensers 7 and shortcircuiting the chip condensers 7 and the memory chip 1 via the electricity conductive heat conductive member 13 extruded to the outer side of the memory chip 1 .
- the chip condensers 7 arranged at vicinities of the memory chip 1 are covered by the underfill resin 10 and accordingly, connection strength in connecting the chip condenser 7 and the package substrate 2 is high. Thereby, a deterioration in connection reliability in connecting the chip condenser 7 and the electrodes 4 is restrained and accordingly, connection life of the chip condensers 7 is promoted.
- solder bumps 6 previously connected to the main face of the memory chip 1 are positioned on the electrode pads 4 at the main face of the package substrate 2 and thereafter, the solder bump 6 are made to reflow, thereby, the memory chip 1 is mounted to the central portion of the main face of the package substrate 2 by face down bonding.
- the solder bump 6 is constituted by a Pb—Sn alloy including, for example, 2 weight % of Sn (liquidus temperature: 320° C. through 325° C.).
- the chip condensers 7 are mounted on the electrode pads 4 at vicinities of the memory chip 1 .
- the chip condenser 7 is formed with electrodes 20 a and 20 b by plating at opposed two sides of a rectangle and at inside thereof, Ni electrodes 22 in thin pieces alternately overlap while sandwiching a high dielectric member 21 comprising barium titanate (BaTiO 3 ) thereamong.
- the solder 8 In mounting the chip condenser 7 , the solder 8 is previously formed on surfaces of the electrodes 20 a and 20 b by plating, preparatory solder is coated on surfaces of electrode pads 4 of the package substrate 2 by screen printing or the like, successively, the electrodes 20 a and 20 b are positioned on the electrode pads 4 and thereafter, the solder 8 is made to reflow.
- the solder 8 comprises, for example, an Sn—Ag alloy including 3 weight % of Ag (melting point: 221° C.). Further, an order of mounting the memory chip 1 and the chip condensers 7 on the package substrate 2 may be reverse to the above-described. Further, after positioning the memory chip 1 and the chip condensers 7 on the electrode pads 4 , the solder bumps 6 and the solder 8 may be made to reflow simultaneously and summarizingly.
- the underfill resin 10 is supplied to the outer periphery of the memory chip 1 .
- the underfill resin 10 is supplied by, for example, scanning a dispenser 30 along one side of the memory chip 1 .
- the package substrate 2 is heated to about 70° C.
- the underfill resin 10 is filled to the respective lower faces of the memory chip 1 and chip condensers 7 by the capillary phenomenon. Further, when the amount of supplying the underfill resin 10 is pertinent, the entire faces of the chip condensers 7 are covered by the underfill resin 10 . Thereafter, the underfill resin 10 is cured by baking at about 150° C.
- Covering of the chip condensers 7 may be carried out by using a covering material other than the underfill resin 10 . That is, as shown by FIG. 10, there may be constituted a procedure in which the underfill resin (first seal resin) 10 is filled to the lower faces of the memory chip 1 and the chip condensers 7 , successively, the chip condensers 7 are covered by separately prepared coating resin (second seal resin) 14 and thereafter, the underfill resin 10 and the coating resin 14 are simultaneously baked and cured. In this case, by integrating the underfill resin 10 and the coating resin 14 , connection strength in connecting the chip condensers 7 and the package substrate 2 can be promoted. Further, a thickness of the resin for covering the chip condensers 7 can be thinned.
- the coating resin 14 is for forming extremely thin coating and there is used epoxy resin or silicone varnish having a content of silica filler lower than that of the underfill resin 10 and having a viscosity lower than that of the under fill resin 10 .
- the heat conductive member (Ag paste) 13 is supplied to the upper face of the memory chip 1 by using a dispenser, not illustrated.
- the heat conductive member 13 is supplied by an amount slightly larger than a necessary amount in order to absorb the dimensional tolerance of the cap 11 (dispersion of height of leg portion 11 a ). Further, at this occasion, the adhering agent 12 is supplied to a peripheral portion of the main face of the package substrate 2 .
- the cap 11 is fixedly attached onto the package substrate 2 .
- the outer edge of the heat conductive member 13 may reach the upper faces of the chip condensers 7 , as described above, since the chip condensers 7 are covered by the underfill resin 10 , the chip condensers 7 are not shortcircuited or the chip condensers 7 and the memory chip 1 are not shortcircuited by the heat conductive member 13 .
- solder balls (not illustrated) constituted by a Pb—Sn eutectic alloy having a low melting point to the surfaces of the electrode pads 5 at the lower face of the package substrate 2 , the solder balls are made to reflow and the solder bumps 9 are formed on the surfaces of the electrode pads 5 thereby finishing the semiconductor device shown in FIG. 1 through FIG. 4.
- FIG. 14 shows an example of mounting three pieces of the memory chips 1 on the package substrate 2
- FIG. 15 shows an example of mounting four pieces of the memory chips 1 thereon.
- the chip condensers 7 are arranged at extreme vicinities of the memory chip 1 since the wirings 3 between the chip condensers 7 and the memory chip 1 are requested to be short, by covering the chip condensers 7 by the underfill resin 10 , promotion of connection life and prevention of shortcircuit failure can be achieved.
- the invention is also applicable to a package in which, for example, as shown by FIG. 16, heat radiating fins (heat sinks) 15 or a flat heat radiating plate is connected to the upper face of the memory chip 1 via a heat conductive member 16 .
- the invention is applicable also to a case in which the heat conductive member 16 comprises an insulating material having high heat conductivity such as BN (boron nitride) or alumina.
- the heat conductive member 16 comprises an insulating material
- the problem of the shortcircuit failure is not caused, however, when the chip condensers 7 are arranged at vicinities of the memory chip 1 , a deterioration in connection life caused by heat generation of the memory chip 1 poses a problem. Therefore, in this case, as shown by FIG. 17, by filling the underfill resin 10 below the chip condensers 7 , the connection strength in connecting the chip condensers 7 and the electrodes 4 is promoted and the connection life of the chip condensers 7 is promoted.
- the heat conductive member 16 when the heat conductive member 16 comprises an electricity conductive material, the heat conductive member 16 may be extruded to the outer side of the memory chip 1 by a dispersion in an amount of supplying the heat conductive member 16 and accordingly, the shortcircuit failure poses a problem. Therefore, also in this case, by covering the chip condensers 7 by the underfill resin 10 , there can be prevented the failure of shortcircuiting the chip condensers 7 and shortcircuiting the chip condensers 7 and the memory chip 1 via the electricity-conductive heat conductive member 16 extruded to the outer side of the memory chip 1 .
- the invention is not limited thereto but is generally applicable widely to a package arranged with chip condensers at vicinities of a semiconductor chip formed with high-speed LSI having a large heat generating amount.
- the invention is not limited to the chip condenser but is applicable widely to a package arranged with a passive element such as a resistor element at a vicinity of a semiconductor chip having a large heat generating amount.
- the passive element by covering a passive element arranged at a vicinity of a semiconductor chip by seal resin, the passive element is not directly exposed to high temperature of the semiconductor chip and accordingly, a deterioration in connection reliability of the passive element is restrained and connection life is promoted.
- a heat conductive member filled between a semiconductor chip and a cap comprises an electricity conductive material
- a cap or heat radiating plate
- an electricity conductive material by covering the passive element by the seal resin, there can be prevented a failure of shortcircuiting the passive elements and shortcircuiting the passive elements and the semiconductor chip.
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Abstract
Description
- The present invention relates to a semiconductor device and a method of manufacturing the same, particularly to a technology effectively applied to a semiconductor device having a package mounted with a semiconductor chip and a passive element on the same substrate.
- Japanese Patent Laid-Open No. 46098/1996 (U.S. Pat. No. 5,533,256) discloses a package having a heat sink for radiating to outside, heat of a semiconductor chip formed with an integrated circuit (hereinafter, simply referred to as chip).
- According to one mode of the package described in the publication, a chip is mounted, by face down bonding, on a pad formed at an upper face of a module substrate via a solder ball. The pad and the solder ball are sealed by a seal member filled in a clearance between the module substrate and the chip.
- One or more of electronic devices such as a decoupling condenser is mounted along with the chip at the upper face of the module substrate. Further, a cap for sealing the chip and the electronic devices are fixedly attached to the upper face of the module substrate via the seal member and the heat sink is fixedly attached to an upper face of the cap via an adhering agent. A clearance between an upper face (rear face) of the chip and a lower face of the cap is filled with a heat conductive member and heat generated at the chip is transmitted to the heat sink via the heat conductive member and the cap.
- According to other mode of the package described in the publication, the heat sink is directly bonded to the upper face (rear face) of the chip via a both face pressure-sensitive heat-conductive adhering tape. According to the mode, a cap for sealing the chip and the electronic devices is eliminated and accordingly, heat of the chip is transmitted to the heat sink further efficiently.
- According to a high-speed LSI in recent years, reduction of noise in driving thereof poses an important problem and as a countermeasure thereagainst, a small-sized large capacity chip condenser is mounted on a substrate mounted with a chip to thereby reduce noise in a middle frequency area.
- In this case, it is requested that the condenser is arranged as proximate as possible to the chip to thereby shorten wirings connecting both. However, a heat generating amount of the chip formed with the high-speed LSI is large and accordingly, when the condenser is arranged at an extreme proximity of the chip, the condenser is exposed to an abrupt temperature change in operating the chip and a deterioration in connection reliability between the condenser and the substrate poses a problem.
- Further, as in the package described in the publication, according to a package sealing the chip and the condenser mounted on the substrate by a cap, when a heat conductive member is filled between the chip and the cap in fabrication steps thereof, a large amount of the heat conductive member must be supplied with an object of absorbing dimensional tolerance of the cap and accordingly, when the condenser is arranged at the extreme proximity of the chip, the heat conductive member extruded from an end portion of the chip is brought into contact with the condenser.
- As a result, the condenser is not only exposed to radiation heat from the chip but is exposed to intense heat conducted from the heat conductive member and the deterioration of the connection reliability in connecting to the substrate poses further serious problem. Further, when the heat conductive member comprises an electricity conductive material such as an Ag paste, there also poses a problem that the chip and the condenser or the condensers are shortcircuited via the heat conductive member.
- It is an object of the invention to provide a technology for promoting connection reliability of a passive element mounted at a vicinity of a chip.
- It is other object of the invention to provide a technology to ensure electric reliability of a passive element mounted at a vicinity of a chip.
- The object and other object and a novel feature of the invention will become apparent from description and attached drawings of the specification.
- A simple explanation will be given of an outline of representative aspects of the invention disclosed in the application as follows.
- According to an aspect of the invention, there is provided a semiconductor device comprising a substrate having a wiring layer, a semiconductor chip mounted onto a main face of the substrate in face down bonding, a passive element mounted onto the main face of the substrate, a seal resin filled between a main face of the semiconductor chip and the main face of the substrate, a cap for sealing the semiconductor chip and the passive element, and a heat conductive member filled between the cap and the semiconductor chip, wherein the passive element is arranged in an area coated with the seal resin and at least a portion thereof is covered by the seal resin.
- According to other aspect of the invention, there is provided a method of manufacturing a semiconductor device comprising following steps:
- (a) a step of mounting a semiconductor chip onto a main face of a substrate having a wiring layer in face down bonding;
- (b) a step of mounting a passive element to a vicinity of an area mounted with the semiconductor chip on the main face of the substrate;
- (c) a step of filling a seal resin into a clearance between a main face of the semiconductor chip and the main face of the substrate and covering the passive element by the seal resin;
- (d) a step of supplying a heat conductive member on an upper face of the semiconductor chip; and
- (e) a step of fixedly attaching a cap for sealing the semiconductor chip and the passive element onto an upper face of the semiconductor chip via a heat conductive member.
- FIG. 1 is a plane view of a semiconductor device according to an embodiment of the invention;
- FIG. 2 is a sectional view taken along a line II-II of FIG. 1;
- FIG. 3 is a sectional view enlarging essential portions of FIG. 2;
- FIG. 4 is a diagram showing a state of connecting a memory chip and chip condensers;
- FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device constituting the one embodiment of the invention;
- FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 7A is a plane view of a chip condenser;
- FIG. 7B is a sectional view taken along a line A-A of FIG. 7A;
- FIG. 8 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 9 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 11 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 12 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 13 is a sectional view showing the method of manufacturing the semiconductor device constituting the one embodiment of the invention;
- FIG. 14 is a plane view of a semiconductor apparatus according to other embodiment of the invention;
- FIG. 15 is a plane view of a semiconductor apparatus according to other embodiment of the invention;
- FIG. 16 is a plane view of a semiconductor apparatus according to other embodiment of the invention; and
- FIG. 17 is a sectional view enlarging essential portions of a semiconductor apparatus constituting other embodiment of the invention.
- A detailed explanation will be given of embodiments of the invention in reference to the drawings as follows. Further, in all the drawings for explaining the embodiments, the same member is attached with the same notation and repetitive explanation thereof will be omitted.
- FIG. 1 is a plane view of a semiconductor device according to the embodiment, FIG. 2 is a sectional view taken along a line II-II of FIG. 1 and FIG. 3 is a sectional view enlarging essential portions of FIG. 2.
- The semiconductor device according to the embodiment is, for example, a package for mounting a
memory chip 1 formed with a high-speed cash memory for a high-speed microprocessor (MPU: ultra small operation processing unit). - A
package substrate 2 of the semiconductor device is constituted by ceramic and at inside thereof, there are formed a plurality of layers ofwirings 3 constituting a wiring for signal, a power source wiring and a ground wiring. Further, a main face (upper face) and a lower face of thepackage substrate 2 are formed with pluralities ofelectrode pads wirings 3. Thewiring 3 and theelectrode pads electrode pads - A central portion of the main face of the
package substrate 2 is mounted with thememory chip 1 in face down bonding by a flip chip bonding system. That is, thememory chip 1 is electrically connected to theelectrode pads 4 at the main face of thepackage substrate 2 via a plurality of solder bumps (bump electrodes) 6 connected to a main face (lower face) of thememory chip 1. - A plurality of
chip condensers 7 are mounted at vicinities of thememory chip 1. Thechip condensers 7 are arranged along an outer periphery of thememory chip 1 and are electrically connected to theelectrode pads 4 at the main face of thepackage substrate 2 viasolder 8. As shown by FIG. 4, thechip condensers 7 are connected in parallel between the power source wiring and the ground wiring of thepackage substrate 2 and realizes high-speed operation by reducing noise caused in driving thememory chip 1. - The
electrode pads 5 at the lower face of thepackage substrate 2 are connected with a plurality ofsolder bump 9 constituting outside connecting terminals of the semiconductor device (package). The solder bumps 9 comprise a solder material having a melting point lower than that of the solder bumps 6 connected to the main face of thememory chip 1. The semiconductor device is mounted to a mother board of a computer via the solder bumps 9. - A clearance between the main face (lower face) of the
memory chip 1 and the main face of thepackage substrate 2, is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions for connecting the both and relaxation of thermal stress. Theunderfill resin 10 comprises, for example, an insulating material such as epoxy resin filled with silica. - An outer edge of the
underfill resin 10 is extended to an outer side of thememory chip 1 and covers entire faces of thechip condensers 7 mounted to vicinities of thememory chip 1. Further, portions of theunderfill resin 10 are filled also to clearances between lower faces of thechip condensers 7 and the main face of thepackage substrate 2. That is, theunderfill resin 10 is filled in the clearances between thememory chip 1 and the respective lower faces of thecondensers 7 and the main face of thepackage substrate 2. - The
memory chip 1 and thechip condenser 7 mounted to the main face of thepackage substrate 2, are sealed by acap 11 made of ceramic and covering a total of the main face of thepackage substrate 2.Leg portions 11 a of thecap 11 are fixedly attached to the main face of thepackage substrate 2 via an adheringagent 12. - A clearance between a lower face of the
cap 11 and the upper face of thememory chip 1, is filled with a heatconductive member 13 for radiating heat generated in driving thememory chip 1 to outside via thecap 11. The heatconductive member 13 is constituted by an electricity conductive material having high heat conductivity such as Ag paste. - As described later, in a step of integrating the package, when the heat
conductive member 13 is filled between thememory chip 1 and thecap 11, in order to absorb a dimensional tolerance of the cap 11 (dispersion in height of theleg portion 11 a), a large amount of the heatconductive member 13 is supplied. For that purpose, an outer edge of the heatconductive member 13 is extended to an outer side of thememory chip 1 and portions thereof reach upper faces of thechip condensers 7 mounted at vicinities of thememory chip 1. - However, according to the semiconductor device of the embodiment, the
underfill resin 10 constituted by an insulating material is not only filled to the clearance between thememory chip 1 and thepackage substrate 2 but also covers entire faces of thechip condensers 7 and accordingly, there is no concern of shortcircuiting thechip condensers 7 and shortcircuiting thechip condensers 7 and thememory chip 1 via the electricity conductive heatconductive member 13 extruded to the outer side of thememory chip 1. - Further, according to the semiconductor device of the embodiment, the
chip condensers 7 arranged at vicinities of thememory chip 1 are covered by theunderfill resin 10 and accordingly, connection strength in connecting thechip condenser 7 and thepackage substrate 2 is high. Thereby, a deterioration in connection reliability in connecting thechip condenser 7 and theelectrodes 4 is restrained and accordingly, connection life of thechip condensers 7 is promoted. - Next, an explanation will be given of a method of manufacturing the semiconductor device according to the embodiment constituted as described above in an order of steps in reference to FIG. 5 through FIG. 13.
- In integrating the package, first, as shown by FIG. 5, the solder bumps6 previously connected to the main face of the
memory chip 1 are positioned on theelectrode pads 4 at the main face of thepackage substrate 2 and thereafter, thesolder bump 6 are made to reflow, thereby, thememory chip 1 is mounted to the central portion of the main face of thepackage substrate 2 by face down bonding. Thesolder bump 6 is constituted by a Pb—Sn alloy including, for example, 2 weight % of Sn (liquidus temperature: 320° C. through 325° C.). - Next, after removing flux residue by cleaning the main face of the
package substrate 2, as shown by FIG. 6, thechip condensers 7 are mounted on theelectrode pads 4 at vicinities of thememory chip 1. For example, as shown by FIGS. 7A and 7B, thechip condenser 7 is formed withelectrodes Ni electrodes 22 in thin pieces alternately overlap while sandwiching ahigh dielectric member 21 comprising barium titanate (BaTiO3) thereamong. In mounting thechip condenser 7, thesolder 8 is previously formed on surfaces of theelectrodes electrode pads 4 of thepackage substrate 2 by screen printing or the like, successively, theelectrodes electrode pads 4 and thereafter, thesolder 8 is made to reflow. Thesolder 8 comprises, for example, an Sn—Ag alloy including 3 weight % of Ag (melting point: 221° C.). Further, an order of mounting thememory chip 1 and thechip condensers 7 on thepackage substrate 2 may be reverse to the above-described. Further, after positioning thememory chip 1 and thechip condensers 7 on theelectrode pads 4, the solder bumps 6 and thesolder 8 may be made to reflow simultaneously and summarizingly. - Next, after cleaning again the main face of the
package substrate 2 to thereby remove flux residue, as shown by FIG. 8, theunderfill resin 10 is supplied to the outer periphery of thememory chip 1. Theunderfill resin 10 is supplied by, for example, scanning adispenser 30 along one side of thememory chip 1. - Next, in order to promote fluidity of the
underfill resin 10, thepackage substrate 2 is heated to about 70° C. Thereby, as shown by FIG. 9, theunderfill resin 10 is filled to the respective lower faces of thememory chip 1 andchip condensers 7 by the capillary phenomenon. Further, when the amount of supplying theunderfill resin 10 is pertinent, the entire faces of thechip condensers 7 are covered by theunderfill resin 10. Thereafter, theunderfill resin 10 is cured by baking at about 150° C. - In this way, in filling the
underfill resin 10 to the lower face of thememory chip 1, by simultaneously covering the entire faces of thechip condensers 7 by theunderfill resin 10, the step can be simplified. - Covering of the
chip condensers 7 may be carried out by using a covering material other than theunderfill resin 10. That is, as shown by FIG. 10, there may be constituted a procedure in which the underfill resin (first seal resin) 10 is filled to the lower faces of thememory chip 1 and thechip condensers 7, successively, thechip condensers 7 are covered by separately prepared coating resin (second seal resin) 14 and thereafter, theunderfill resin 10 and thecoating resin 14 are simultaneously baked and cured. In this case, by integrating theunderfill resin 10 and thecoating resin 14, connection strength in connecting thechip condensers 7 and thepackage substrate 2 can be promoted. Further, a thickness of the resin for covering thechip condensers 7 can be thinned. Although resin having low viscosity is used for theunderfill resin 10 since the resin is filled by utilizing the capillary phenomenon, thecoating resin 14 is for forming extremely thin coating and there is used epoxy resin or silicone varnish having a content of silica filler lower than that of theunderfill resin 10 and having a viscosity lower than that of theunder fill resin 10. - Next, as shown in FIG. 11, the heat conductive member (Ag paste)13 is supplied to the upper face of the
memory chip 1 by using a dispenser, not illustrated. The heatconductive member 13 is supplied by an amount slightly larger than a necessary amount in order to absorb the dimensional tolerance of the cap 11 (dispersion of height ofleg portion 11 a). Further, at this occasion, the adheringagent 12 is supplied to a peripheral portion of the main face of thepackage substrate 2. - Next, as shown by FIG. 12 and FIG. 13, by positioning the
cap 11 on thepackage substrate 2 and heating and curing the heatconductive member 13 and the adheringagent 12, thecap 11 is fixedly attached onto thepackage substrate 2. At this occasion, although the outer edge of the heatconductive member 13 may reach the upper faces of thechip condensers 7, as described above, since thechip condensers 7 are covered by theunderfill resin 10, thechip condensers 7 are not shortcircuited or thechip condensers 7 and thememory chip 1 are not shortcircuited by the heatconductive member 13. - Thereafter, after supplying solder balls (not illustrated) constituted by a Pb—Sn eutectic alloy having a low melting point to the surfaces of the
electrode pads 5 at the lower face of thepackage substrate 2, the solder balls are made to reflow and the solder bumps 9 are formed on the surfaces of theelectrode pads 5 thereby finishing the semiconductor device shown in FIG. 1 through FIG. 4. - Although according to the embodiment, an explanation has been given of the case in which only a single piece of the
memory chip 1 is mounted on thepackage substrate 2, the embodiment is applicable also to a case of mounting two pieces or more of thememory chips 1. For example, FIG. 14 shows an example of mounting three pieces of thememory chips 1 on thepackage substrate 2 and FIG. 15 shows an example of mounting four pieces of thememory chips 1 thereon. Although in these cases, thechip condensers 7 are arranged at extreme vicinities of thememory chip 1 since thewirings 3 between thechip condensers 7 and thememory chip 1 are requested to be short, by covering thechip condensers 7 by theunderfill resin 10, promotion of connection life and prevention of shortcircuit failure can be achieved. - Although in
Embodiment 1, described above, an explanation has been given of the case in which thememory chip 1 and thechip condensers 7 are applied to the package sealed by thecap 11, the invention is also applicable to a package in which, for example, as shown by FIG. 16, heat radiating fins (heat sinks) 15 or a flat heat radiating plate is connected to the upper face of thememory chip 1 via a heatconductive member 16. Further, the invention is applicable also to a case in which the heatconductive member 16 comprises an insulating material having high heat conductivity such as BN (boron nitride) or alumina. - When the heat
conductive member 16 comprises an insulating material, the problem of the shortcircuit failure is not caused, however, when thechip condensers 7 are arranged at vicinities of thememory chip 1, a deterioration in connection life caused by heat generation of thememory chip 1 poses a problem. Therefore, in this case, as shown by FIG. 17, by filling theunderfill resin 10 below thechip condensers 7, the connection strength in connecting thechip condensers 7 and theelectrodes 4 is promoted and the connection life of thechip condensers 7 is promoted. - Further, also in the case of the package according to the embodiment, when the heat
conductive member 16 comprises an electricity conductive material, the heatconductive member 16 may be extruded to the outer side of thememory chip 1 by a dispersion in an amount of supplying the heatconductive member 16 and accordingly, the shortcircuit failure poses a problem. Therefore, also in this case, by covering thechip condensers 7 by theunderfill resin 10, there can be prevented the failure of shortcircuiting thechip condensers 7 and shortcircuiting thechip condensers 7 and thememory chip 1 via the electricity-conductive heatconductive member 16 extruded to the outer side of thememory chip 1. - Although as described above, a specific explanation has been given of the invention which has been carried out by the inventors based on the above-described embodiments, the invention is not limited to the embodiments and can naturally be modified variously within a range not deviated from gist thereof.
- Although according to the embodiments, an explanation has been given of the case in which the invention is applied to the package mounted with the high-speed memory chip, the invention is not limited thereto but is generally applicable widely to a package arranged with chip condensers at vicinities of a semiconductor chip formed with high-speed LSI having a large heat generating amount.
- Further, the invention is not limited to the chip condenser but is applicable widely to a package arranged with a passive element such as a resistor element at a vicinity of a semiconductor chip having a large heat generating amount.
- A simple explanation will be given of an effect achieved by representative aspects of the invention disclosed in the application as follows.
- According to the invention, by covering a passive element arranged at a vicinity of a semiconductor chip by seal resin, the passive element is not directly exposed to high temperature of the semiconductor chip and accordingly, a deterioration in connection reliability of the passive element is restrained and connection life is promoted.
- Further, when a heat conductive member filled between a semiconductor chip and a cap (or heat radiating plate) comprises an electricity conductive material, by covering the passive element by the seal resin, there can be prevented a failure of shortcircuiting the passive elements and shortcircuiting the passive elements and the semiconductor chip.
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000076709A JP2001267473A (en) | 2000-03-17 | 2000-03-17 | Semiconductor device and its manufacturing method |
JP2000-076709 | 2000-03-17 |
Publications (2)
Publication Number | Publication Date |
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US20010050428A1 true US20010050428A1 (en) | 2001-12-13 |
US6433412B2 US6433412B2 (en) | 2002-08-13 |
Family
ID=18594407
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Application Number | Title | Priority Date | Filing Date |
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US09/800,589 Expired - Fee Related US6433412B2 (en) | 2000-03-17 | 2001-03-08 | Semiconductor device and a method of manufacturing the same |
Country Status (4)
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US (1) | US6433412B2 (en) |
JP (1) | JP2001267473A (en) |
KR (1) | KR20010091916A (en) |
TW (1) | TW498522B (en) |
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Also Published As
Publication number | Publication date |
---|---|
KR20010091916A (en) | 2001-10-23 |
US6433412B2 (en) | 2002-08-13 |
TW498522B (en) | 2002-08-11 |
JP2001267473A (en) | 2001-09-28 |
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