TW493262B - Vertical conduction flip-chip device with bump contacts on single surface - Google Patents
Vertical conduction flip-chip device with bump contacts on single surface Download PDFInfo
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- TW493262B TW493262B TW090102979A TW90102979A TW493262B TW 493262 B TW493262 B TW 493262B TW 090102979 A TW090102979 A TW 090102979A TW 90102979 A TW90102979 A TW 90102979A TW 493262 B TW493262 B TW 493262B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H01L2924/01078—Platinum [Pt]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
五、發明說明(1 ) 、本發明係有關於半導體裝置封裝體及製造該封裝體的 方法一而特別有關於一晶片規格的封裝體及其製造方法。 半導體裝置封裝體係習知被用來包覆及保護晶片,並 曰曰片的I極提供輸出之連結者。通常,該半導體晶片 大母曰曰元所切分,其中該晶片的擴散與金屬化會被 Y傳、充的曰曰兀處理设備來完成。該等晶片可能為二極體、 場效應電晶體、石夕控整流器及類似物等。該晶片係易碎的, 故其表面必須被保護以隔絕外部環境。又,適當的導線必 須被連=於該晶片的電極,俾將該晶片連接於電的迴路中。 通常,該等晶片會被例如切蘇而由晶元分開,且該晶 片的底部會破固定在並連結於一電路板的一部份上,該電 2板具有對應的部位可容裝各晶片。㈣晶片頂部的電極 f會被起接線至該電路板的其它部份,俾可供連接外 亥等線路接點因十分纖細精密,故會減慢其固裝程序。 且匕們亦會开> 成相對較高的電阻及電感。 因此在許多場合中乃期能使該等封裝的半導體裝置, 可由該封裝體的-面來裝接,俾能將其快速而可靠地固裝 在一電路板上,以及低阻抗地連結。 本發明係提供-種新穎的半導體晶片封裝體,其包含 有覆晶而可利用該晶片的一面,來固裝在一電路板或 其它的電子界面上。特別是’該封裝體所有接點,例如閘 極、源極、汲極電極之接點(指M0SFET)等,皆設在該封 裝體的同-側面’並可藉在該晶片之該表面上形成谭球接 點而來固接’料接點係分別對應於該電路板上之各 493262
-經濟部智慧財產局員工消r合作社印製 的閘極、源極、汲極接點等。 對該晶片的源極連接係藉在該晶片之源電極上的谭球 ^完成’料焊球會被定位成使它mi與在電路板上之適 當的源極電接點銜接。該封裝料被製成使該汲電極位於 同一表面上。 在只施例中,该等激活接面係設在一相對較低的載 體濃度(例如Ρ·)之膜層中,位於源極電極下方而在-基材 上方,該基材具有同型(例如Ρ+)之相對較高的載體濃度。 至少有-沒極電極設在該相同表面上,而位於—與該源極 電極分開的區域。有一擴散區或“下沉,,部會由頂面的汲電 極延伸肖了,穿過該較低載體濃度層而至該基材處。該擴 政區係與该基材具有相同的載體濃度及類型(例如ρ+)。 故,乃可形成一電的流路,即由該源電極通過該等激活構 件,嗣進入該基材再通過該擴散區,而達到頂部的汲電極。 如所述,該汲電極係與該等源極及閘極電極設在同一 平面上,故亦可使用焊球來裝接於電路板,該等焊球係對 應於該〉及極外部接點的適當位置者。 在另一實施例中,取代該汲極接點底下的擴散區,該 較低載體濃度層乃可被蝕刻至該基材處,而填滿該汲電極 材料。其係能夠例如在一垂直傳導之溝道式裝置的溝道蝕 刻步驟中,同時來完成。 於本發明之又另一實施例中,兩個垂直傳導的 MOSFE 丁裝置可被設在一共同的晶片中,而使它們的源極 區被橫向地間次叉交並具有一共同的汲極基材。此構件會 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ^--------1---------線 (請先閱讀背面之注意事項再填寫本頁) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 493262 五、發明說明( 形成一雙向開關。其所有的接點皆可設在頂部表面上,而 該等接觸球可沿各直排來列設,並沿一矩形之對角線來對 稱地設置,而能簡化地連接於一電路板。該晶片的底部可 設有一厚金屬層,俾在相鄰的裝置之間以共用的汲極提供 一低電阻的電流路徑。其在當晶片以頂面對設於一印刷電 路板時,亦可改善熱傳導。 本發明之其它特徵與優點,將可由以下本發明的描述 參考所附圖式而更清楚瞭解。 圖式之簡單說明 第1圖係為本發明第一實施例的立體圖。 第2圖為第1圖之裝置在設置接觸凸體之前,其金屬化 物圖案的頂視圖。 第3圖為第2圖之晶元在形成焊球之後的頂視圖。 第4圖為沿第2圖之截線4_4所採之一小區域的剖視 圖’乃示出該源極與汲極等頂部金屬化物。 第5圖乃示出第丨、3圖之接觸球的尺寸及間距。 第6圖係沿第2圖之截線6_6橫過閘匯流線的剖視圖。 第7圖表不使用一 p+下沉擴散部來將汲極金屬之一頂 部接點連接於該P+基材。 ' 第8圖示出修正的接點結構可將第4圖之頂面沒極觸 接於該P+基材。 第9圖為本發明另一實施例之金屬化頂面的頂視圖。 第1〇圖示出第9圖之裝置具有多排的接觸球於其定位。 第11圖係為第9圖之一截面圖,為可取代第4圖之溝道 ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁)
493262 A7 .11濟部智慧財產局員工消費合作社t制π 五、發明說明(4 ) 結構的平面接合圖案。 第12圖為本發明又另一實施例的剖視圖,其乃類似於 第4圖但係在一共同晶片中使用兩個m〇SF]Et,而形成一雙 向傳導的裝置,且係為第14圖沿12_12截線所採的剖視圖。 第13圖係為第12圖之裝置的電路圖。 第Η圖係為第12及13圖之裝置的頂視圖。 第15圖係為第14圖之裝置的前視圖。 第16至19圖示出第Η圖之裝置的其它變化實施例。 第1至6圖係示出本發明之第一實施例,其乃為一覆晶 電源MOSFET(金屬氧化物半導體場效應電晶體)的形式, 』而其所有的電極皆設在一平面上,並具有接觸凸體等可觸 接於一例如印刷電路板等支撐構件的執線或其它的電導體 上。該要被描述的裝置亦可為任何種類的裝置,例如一 P/N,或Schottky二極體,一 IGB 丁,一矽控整流器,一具有 許多構件的積體電路晶片等等。又,第⑴圖所示的裝置 係為-P通道之裝置。其傳導類型亦可顛倒而形成一崎道 裝置。X,第1至6圖所示的裝置係為一溝道式裝置,但其 亦可為一平面穿孔的或條紋式結構,如將於後所述者。 該完成後的裝置,當準備要固裝時,乃如第〗圖所示, 其含有一石夕晶片30,頂部具有源電極金屬化物3ι(一般為鋁 而有骑米厚),汲電極金屬化物32,及間電極金屬辉點 33(見第2圖),及閘匯流線34等。 該晶片係被製成晶元形式,而部份地如第2、3圖所示。 接觸球會被設在該晶元上,如第1、 , 乐1 j 4圖所不,即源極接 本纸張尺度適用申國國家標準(CNS)A4規格χ 297公爱i ^ ^---------線 (請先閱讀背面之注意事項再填寫本頁) 7
493262 五、發明說明(5 ) 觸球4〇設在祕金屬31上’㈣接觸糾與a設在沒極金 屬32上,而閘極接觸球43設在閘極烊點金屬耻。嗣在該 晶元中的晶片會被分開’並準備被組袭在_電路板或類似 物上。 第4及6圖乃示出第丨、3圖之裝置的溝道式電源 MOSFET之構造。即,就一 p通道裝置而言’一 p+矽基材5〇 將會被使用’且-低濃度的P型之接面容納層对被蟲晶 地生成在該P+基材50上。有一N型基極或通道擴散層52(第 4、5圖)嗣會被形成。 然後,利用習知技術,許多平行的溝道6〇、61(見第4 圖)或一交叉溝道的陣列會形成隔離的台面區域。一薄的絕 緣層,例如二氧化矽會被生成在各溝道6〇至64的壁上,分 別如所示之閘絕緣層70至74。一導電的聚矽閘75嗣會被沈 積於各溝道中,並覆蓋該等閘氧化層,然後會被蝕刻掉而 僅在5亥等溝道與閘匯流線及焊點區域留下聚石夕。之後,有 一丁EOS(四正矽酸乙酯)層80會被沈積而製成圖案,留下絕 、’彖76與77(其可為TE0S)來覆蓋在溝道6〇與61中的聚石夕 75之頂部(見第4圖)。 一 Ρ+之源極擴散層53會被形成於該ν擴散層52的頂 部’其會被蝕刻貫通該二層52與53。接觸孔81與82等(見第 4圖)嗣會被蝕刻穿過該Ρ+源極層53而進入通道層52,而Ν+ 接觸擴散層會被設在該等開孔81與82的底部。該介電材料 ㈣會被橫向地蝕刻而曝現該晶片表面上之源極區域的部份 以供接觸。一連續的鋁層嗣會被沈積在該裝置的表面上, 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) ---:!11‘——·----裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 493262
置濟部智慧財產局員工消費合作社Α製
而使該銘層接觸P+源極區53及N型通道區52。藉著钱刻, 該鋁層會被分成源極接點31、汲極接點32及閘極焊點33。 第5圖乃示出接觸球4〇、41等之新穎構造。該等焊球係 以習知的方法使用鎳金電鍍,再將焊劑模印並使其流動而 形成焊球。故’該等焊球或凸體會形成〇.8mni的中心距, 此係為一比習用者更寬的間距。藉使用〇.8mm或更大的間 距,本叙明的覆晶構件乃可模擬習用之晶片規格的封裝體 使用習知的表面固接技術,來與具有傳統執線的電路板固 接。該等焊球4〇、41會被以習用的熱聲波來熔接於一表面 上,但具有比先前所使用者更大的直徑,例如2〇〇“或者更 大而相對於;^準的150//。藉著使用更大的直徑,乃可增 進熱傳導而且對熱疲乏的阻抗亦可改善。 在第4圖中’該汲極金屬32乃被示出接觸該?+基材 之一向上延伸的部份。此僅為一概略的表示,而在實際上, 該表面汲極32與P+基材5〇的接觸係如第7或8圖所示。即, 在第7圖中,有一p+的“下沉,,擴散部90會被用來造成該接 觸。在第8圖中,有一溝道91會被形成,即當在製成該激活 區域的溝道之蝕刻程序時一起製成,並被填滿金屬或導電 聚發92。 第1至8圖之裝置的操作將為專業人士所易知。即,啟 動該裝置’再以適當的電壓施於源電極31與汲電極32,施 加於間75的閘電壓將會使鄰近該閘氧化層70至74之N型矽 轉凌成P型,而構成一電路,即由源電極3丨通過源極區53, 再通過轉換區至P區域5丨及p+基材5〇,然後側向地經由p+ 本紙張尺度適用中關冢標準(CNS)A4規格^·χ 297公髮---- t--------^---I------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 493262 五、發明說明( 基材50向上(經由9〇或92區域)通至汲電極32。 第1至8圖之新穎裝置可使該裝置準備固接的尺寸減至 隶小’即疋,減至該晶片的大小。使用一垂向構造的孔溝 技術’該晶片本身會有極低的RDSON。 舉例而g ’該設計可使用每平方σ寸超過1 1 Q χ 1 〇6單元。 然而,不像標準的溝道FET設計,其汲極接點係被設於該 曰曰片的正面或頂面。故不須要在晶片底面作背部研磨,或 將金屬沉積在該晶片的底面上。因不必背部研磨,故該較 厚的Ρ+基材乃對汲極電流能有較低的側向阻抗。最好是, 遺aa片底部係能粗糙而不能拋光,以增加其表面積而有助 於由該晶片除熱。 在金屬,一氮化矽(或其它的介電質)鈍化層被沉積之 後。該氮化矽鈍化層會被形成圖案而在每個晶片上留下四 個開孔,乃具有例如〇.8mm的間距。該晶片的尺寸典型係 約0.060,,><0.060,,。而0.123,\0.123,,的較大裝置亦屬常見。 該矽係被設計成一 2.0v的P通道裝置,其在4·5ν的電壓時具 有 46.8 ohm-mm2的 R*A。 雖並不須有一金屬層設在該基材5〇的底面上,但仍可 利用此一金屬層作為電流導體或用來接觸於一散熱體。 其它具有更多數目焊球而具更高電流容量的表面構造 亦可被使用。即,如第9及10圖所示,有一較大的晶片1〇〇 可被δ又计成使其頂面具有一源電極1 Q卜二沒電極1 與1 供於該晶片100的相反邊緣,及一閘焊點104具有線路或匯 流線105、106等。如第10圖所示,該各汲電極1〇2與1〇3皆 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 10 五、發明說明(8 ) 谷納五個焊球對齊於各排,而源極101容納八個焊球亦對齊 於平行的各排。有一單獨的焊球會被連接於該閘焊點1。 籍者將該等焊球對齊於平行的各排,則在承接該裝置的印 刷電路板上之各導電執線等,將可被佈設成簡單的直線。 第11圖乃示出第9圖的裝置如何以平面技術來完成,而 形如一N通道裝置。即,在第u圖中,晶片1〇〇係由一 n+ 基材110,以及一N型磊晶(epi)層Hi所形成,而具有間隔 的多邊形p通道擴散部112、113、114等。該各擴散部112、 113、114等乃分別容納一矿源極擴散部115、116、ιΐ7,及 一 P+接觸擴散部118、U9、120等。一適當的間極結構,包 括一聚矽閘格121覆蓋一習知的閘氧化物,並被一絕緣層 122所覆蓋,而使該閘格與上層覆設的源電極ι〇ι絕緣,該 源電極以普通的方式接觸該等源極區與通道區。有一矿下 沉部形成一由該N+基材至該汲電極1〇3的導電路徑。 經濟部智慧財產局員工消費合作社印製 亦可將該晶片製成具有雙向導接的特性,其係將兩組 連接的m〇SFET整合在一單獨的晶片上。gp,如第12圖所 示,該晶片可用第1至8圖的方法來被製成一 p通道溝孔實 施例。故,使用在第丨至8圖令的編號構件,第12圖的雙向 晶片130即可將二該等裝置整合在一單獨的晶片上。該二裝 置乃被以第4圖的編號,分別附加“a”及“B,,而來桿示,但 具有一共用的基材50。二個別的閘構件亦將會被設置,其 各具有第5及6圖的結構。一基材金屬化物131亦被示出。 該雙向裝置的電路圖乃示於第13圖中,其含有二 M〇SFET 14G與⑷等,具有各自的源極端子§1與=問極
493262 A7 五、發明說明(9 ) 部 智 慧 員 工 消 費 印 端子〇1與〇2,及一共同的汲極50、131,而形成該雙向傳 V電路。MOSFET U〇與hi係為垂向傳導的裝置,而具有 各自的二極體(未示於第13圖中),其在另_M〇SFET啟動 時將會導通。 第14與15圖係示出第12圖之晶片13〇的頂視與前視 圖。該晶片130可具有底部的導電汲電極131(見第15圖), 亚會設置各自的閘極球電極<31與(}2,其乃各自具有閘匯流 線142與143。没電極131係可為一厚的低電阻金屬層(相較 於傳統的源電極厚度)。該底部導體131若該p+基材50之高 度具有足夠的導電性,則亦可被略除,但其可被當作一散 熱體使用。 該各FETM0與141的源電極皆具有二個或更多的電極 凸體S#S2,如第14圖所示。在、凸體與…凸體之間的 離,及S2凸體與G2&體之間的距離乃是相同的。 依據本《月之另-愁樣,該晶片}30的長度係大於其 度。即’其乃呈非正方形的細長矩形。又,該等晶片凸 S1、S2、G1、G2係沿該晶片130的對角斜線來對稱佈設_ 第μ圖之虛線所示的對角線15〇。故,不論該晶片之上/下 源極與閘極電極皆會在相同位置。由於該晶片 而二:二故“皮固裝於一表面時並不須要標示記號 而間早的圖案辨識裝置即可衫該晶片的方向或定位。 ^二所f ’依據本發明,該等源極焊球S〗係成排列 ^" “開平行於成排的源極辉球S2等。 弟17 18圖乃不出第13、14、l5iFE]n(刚)及 訂 距 寬 體 如 具 線 本纸張尺度_中關家標準 493262 A7 —------------------B7 __ 五、發明說明(10 ) . FET2(141)的變化例等,其中相同的編號代表相同的構件。 第16至19圖中之石夕晶片乃可具有大的〇·120,,χ〇·ι20”的面 積。而在該等例子中,源極焊球S1與S2係被列設於垂向而 - 平行的各排中,故可藉在一印刷電路板上之直線金屬條紋 - 或直線金屬化線路作為直線導體,而來容易地將之平行連 接。又該等FET 140與141的源極在第17、18、19圖中被整 合,而可增加其連接的面積。第19圖的裝置係特別地有利, 因為其可將電流在該基材上運行的距離減至最小,而將該 二組源極金屬凸體保持在一起。以此方式,其基材與金屬 的電阻皆非常的低,且在板間的連結十分容易。 雖本發明已以其特殊實施例來詳細說明,但仍有許多 其它的變化和修飾及用途可被專業人士容易得知。因此, 本發明表好不以前揭說明來限制,而僅由申請專利範圍來 界定。 --------------裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 丨線 •經濟部智慧財產局員工消費^作社印制衣 13 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 493262 A7 B7_ 五、發明說明(11 ) 元件標號對照 經濟部智慧財產局員工消費合作社印製 30··· 矽晶片 91…溝道 31··· 源電極金屬化物 92…金屬 32··· 沒電極金屬化物 100···晶片 33··· 閘電極金屬焊點 101···源電極 34·.· 閘匯流線 102、103···汲電極 40··· 源極接觸球 104···閘焊點 41、 42·.·汲極接觸球 105、106···匯流線 43··· 閘極接觸球 110…基材 50··· P+矽基材 111···磊晶層 5 1··· 接面容納層 112、113 · 114···Ρ通道擴散部 52··. 通道擴散層 115、116、117··•源極擴散部 53··· 源極擴散層 118、119、120···接觸擴散部 60〜 6 1…溝道 121···聚矽閘格 Ί0、 7 1 ·. ·閘絕緣層 122…絕緣層 75··· 聚矽閘 130···雙向晶片 Ί6、 77.··絕緣蓋 131…基材金屬化物 80"-TE〇S 層 140、141".M〇SFET 81、 8 2…接觸孔 142、143···閘匯流線 90… P+下沉擴散部 150···對角線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格m〇 X 297公釐) 14
Claims (1)
- 493262 A8 B8 C8 D8 申請專利範圍 經¾部智慧財產局員工消費合作社印製 •一種覆晶半導體裝置,包含一石夕晶元具有平行的第一與 第二主平面;在該晶元中至少有一 p區域及至少_^^區 域會接合於該石夕晶圓的PN接面;第一與第二共平面而 側向分隔的金屬化區域乃被設在該第一主平面上而互 相絕緣,並分別連接於該P區域與N區域;該第二主平 面會被刻意粗糙化以形成一擴伸區域來改善該半導體 裝置的對流冷卻。 2. —種覆晶半導體裝置,包含一矽晶元具有平行的第一與 第一主平面;在該晶元中至少有一P區域及至少一 N區 域會被接合於該矽晶圓的PN接面;第一與第二共平 而側向分隔的金屬化區域乃被設在該第一主平面上 互相絕緣’並分別連接於該P區域與N區域;而有一 部的金屬化層延伸遍佈該第二主平面。 3. 如申請專利範圍第!項之裝置,更包括一第三金屬化層 設在該第一主平面上,其與該第一及第二金屬化層共平 面亚側向分隔;該第一、第二及第三金屬化層係分別 含一 MOS閘裝置的源極、汲極與閘極電極等。 (如申請專利範圍第2項之裝置,更包含一第三金屬化層 設在該第一主平面上,其與該第一及第二金屬化層共平 面亚側向分隔;該第一、第二及第三金屬化層係分別 含一 MOS間裝置的源極、汲極與閘極電極等。 5·如申請專利範圍第旧之裝置,更包含有至少一接觸 體連接於該各金屬化層。 6.如申請專利範圍第2項之裝置,更包含有至少—接觸凸 面 而 底 包 包 凸 1 I I* 1· I —夺I I I I I I · n I n n n ϋ n n n I n 1 I I I (請先閱讀背面之注意事項再填寫本頁) 15 493262 更包含有至少一接觸凸 更包含有至少一接觸凸 其中該底部的金屬化層 A8 B8 C8 D8 申請專利範圍 體連接於該各金屬化層。 7·如申請專利範圍第3項之裝置 體連接於該各金屬化層。 8·如申請專利範圍第4項之裝置 體連接於該各金屬化層。 9·如申請專利範圍第2項之裝置 係比該等第一與第二金屬化層皆更厚 10. 如申請專利範圍第4項之裝置,其中該底部的金屬化層 係比該等第一與第二金屬化層皆更厚。 11. 如申請專利範圍第6項之裝置,其中該底部的金屬化層 係比該等第一與第二金屬化層皆更厚。 12. 如申請專利範圍第8項之裝置,其中該底部的金屬化層 係比该等第一與第二金屬化層皆更厚。 13. 如申請專利範圍第5項之裝置,其中有多數接觸凸體係 被連接於該各第一與第二金屬化層;該等連接於第一金 屬化層的接觸凸體係被沿一第一直排來對齊列設;而該 等連接於第二金屬化層的接觸凸體則被沿一第二直排 來對齊列設。 14·如申請專利範圍第13項之裝置,其中該第一與第二直排 係互相平朽·。 15·如申請專利範圍第6項之裝置,其中有多數接觸凸體係 被連接於該各第一與第二金屬化層;該等連接於第一金 屬化層的接觸凸體係被沿一第一直排來對齊列設;而該 等連接於第二金屬化層的接觸凸體則被沿一第二直排 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公釐) ----I------I----------訂·-------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費^一作社印剩衣 16 493262申請專利範圍 經濟部智慧財產局員工消費合作社印制衣 來對齊列設。 16·如中請專利第15項之農置,其巾㈣— 係互相平行。 /、弟一直排 17·如申請專利範圍第13項之裝置,更包括n屬化層 设在該第一主平面上’其與該第一及第二金屬化層丘平 面並側向分隔;該第-、第二及第三金屬化層係分:包 含一 MOS閘裝置的源極、沒極與閘極電極等。 18·如申請專利範圍第14項之裝置,更包括-第三金屬化層 設在該第-主平面上,其與該第—及第二金屬化層丘平 面並側向分隔;該第-、第二及第三金屬化層係分別包 含一MOS閘裝置的源極、汲極與閘極電極等。 19·:種覆晶半導體裝置,包含一矽晶元具有平行的第一與 第一主平面;在該晶元中至少有一p區域及至少一 N區 域會接合於該矽晶圓的PN接面;第一與第二共平面而 側向分隔的金屬化區域乃被設在該第一主平面上而互 相絕緣,並分別連接於該p區域與N區域;且有多數的 接觸凸體被連接於該各第一與第二金屬化層;該等連接 於第一金屬化層的接觸凸體係被沿一第一直排來對齊 列設;而該等連接於第二金屬化層的接觸凸體則被沿一 第二直排來對齊列設。 20·如申請專利範圍第19項之裝置,更包括一第三金屬化層 設在該第一主平面上,其與該第一及第二金屬化層共平 面並側向分隔;該第一、第二及第三金屬化層係分別包 含一 MOS閘裝置的源極、汲極與閘極電極等。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -----------^ · ’丨線· 17 4^3262 六 . * - - * . ‘ ·-經濟部智慧財產局員工消費合作社印製 §88 C8 — D8 申請專利範圍 21·如申請專利範圍第19項之裝置,並有—底部的金屬化層 延伸遍佈該第二主平面。 2 2 .如申請專利範111第1 9項之裝置,其中該底部的金屬化層 係比該等第一與第二金屬化層皆更厚。 23. 如申請專利範圍第_之裝置,其中該第一與第二直排 係互相平行。 24. 如申請專利範圍第19項之裝置,其中該石夕晶元係為一矩 形晶兀,而具有由一特定長度與寬度所形成的區域;該 長度ίτ大於該寬度;且該第一與第二排的凸體係互相平 行,並沿穿過該晶元之對角線形成對稱。 25·如申請專利範圍第24項之裝置,更包括一第三金屬化層 。又在4第一主平面上,其與該第一及第二金屬化層共平 面亚側向分隔;該第一、第二及第三金屬化層係分別包 含一 MOS閘裝置的源極、汲極與閘極電極等。 26. 如申請專利範圍第21項之裝置噙中該石夕晶元係為一矩 形晶元,而具有由一特定長度與寬度所形成的區域;該 長度係大於該寬度,·且該第一與第二排的凸體係互相平 行’並沿穿過該晶元之對角線形成對稱。 27. 如申請專利範圍第19項之裝置,更包含有一底部的金屬 化層延伸遍佈該第二主平面。 28. —種雙向傳導的覆晶裝置,包含一矽晶元具有第一與第 一平行主平面,有第一與第二側向分開的M〇s閘裝置 設在該矽晶元上;該等第一與第二M〇s閘裝置乃包含 一第一及一第二源極區具有一種導電性,而分別設在該 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 493262 經 濟 部 智 慧 財 產 局 員 工 消 費 合 η 社 印 製 A8 B8 C8 D8 申請專利範圍 第一主平面上之一第一與一第二側向分隔的區域中,一 第一與一第二通道區具有第二種導電性,而分別容納該 第一與第二源極區,一共同的沒極區容納該第一與第二 通道區而延伸至第二主平面,及一第一與第二閘構件分 別設在該第一主平面上,而可操作來轉換該第一與第二 通道區的對應部份,使其能分別由該第一與第二源極區 傳導至該汲極區;第一與第二側向分隔的源極金屬化層 設在該第一主平面上,而分別連接於第一與第二源極 區;及第一與第二側向分隔的閘極金屬化層設在該第一 主平面上,而分別連接於該第一與第二閘構件。 29. 如申請專利範圍第28項之裝置,更包含至少一接觸凸體 連接於該各源極及閘極金屬化層。 30. 如申請專利範圍第29項之裝置,更包含有多數的接觸凸 體連接於該各源極金屬化層;該等接觸凸體係被以互相 平行分隔的直排來列設。 31. 如申請專利範圍第28項之裝置,其中該第一與第二源極 區係被以互相橫向間次叉交的關係來設置。 32. 如申請專利範圍第30項之裝置,其中該第一與第二源極 區係被以互相橫向間次叉交的關係來設置。 33. 如申請專利範圍第28項之裝置,更包含有—金屬層設在 該弟二主平面上。 34. —種半導體裝置,包含一矽晶片具有第一與第二平行表 面;有一具一種導電性的區域由該第一表面伸入該晶片 本體内;一設於所述裝置中之接面圖荦合 U木曰由多數側向分 本紙張尺度適用中國國家標準(CNS)A4規格(2JLQ X 297公爱 ---;-7--*-------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 493262•經濟部智慧財產局員工消費合作社印製隔之另種導電性的擴散部伸入前述_種導電性區域中 而來形成;一第一傳導電極被設在該第一表面上,並接 觸該等第-擴散部,·-第二傳導電極亦設在該第一表面 上—而與第一傳導電極共平面地側向分隔並絕緣,且接 觸前述一種導電性的區域;又至少有—焊球接點分別設 在該各第-與第二傳導電極上;由該第—傳導電極至第 2傳導電極的電流路徑具有一垂向部份大致垂直於該 第一表面。 π如申請專利範㈣34項之裝置,其中該裝置包含一電源 _閘裝置;而該第—與第二電極包含該裝置的主電 源電才虽。 %·如申請專㈣圍第35項之裝置,其中該裝置包含一聚石夕 閘極=構鄰設於料擴散部,並可#作來啟閉該裝置, 及-第三傳導電極設在第_表面上,而與該第_與第二 傳導電極共平面地側向分隔並絕緣,且連接於該聚石夕閑 極結構;及-焊球接點連接㈣第三料電極;而所有 的該等焊球接點皆互相共平面。 37·如申請專利範圍第36項之裝置,其中該裝置係為-覆晶 電源 MOSFET。 請專利範圍第34項之褒置,其中該—種導電性係為 如申=月專利圍第36項之裝置,其中該—種導電性係為 P型 40_如申請專利範圍第34項之裝置,其中該一種導電性的 區 Μ--------^---------^ (請先閱讀背面之注意事項再填寫本頁)本紙準⑵。 X 297公釐) 20 493262 經濟部智慧財產局員工消費合作社印製 晶 覆 A8 B8 C8 D8 六、申請專利範圍 域包括一相對較低濃度之磊晶矽形成的頂層,及一較高 /辰度之非蠢晶矽形成的底層。 41·如:請專利範圍第%項之裝置,其中該一種導電性的區 域包括一相對較低濃度之磊晶矽形成的頂層,及一較高 〉辰度之非磊晶矽形成的底層。 42·如申料利範圍第4〇項之裝置,更包含一相對較高濃度 之下沉擴散部由該第二電極延伸而連接於該區域的底 層。 -如申料利範圍第41項之裝置,更包含—相對較高濃度 之下,儿擴散部由該第二電極延伸而連接於該區域的底 層。 一 -如申請專利範圍㈣項之裝置,更包含—溝道延伸穿過 該:種導電性的區域之頂層,及—導電材料至少被列設 在该溝道的側壁上。 A如申料利範圍㈣項之裝置,其中該裝置包含— ΓΓΙΓ該等擴散部’並可操作來啟閉該裝:, 弟二傳V電極設在第—表面上,而與該第—盘第二 傳導電極共平面_向分隔並絕緣,且連接於 極結構;及-焊球接點連接於該第三傳導電極;: 的泫等焊球接點皆互相共平面。 有 饭如申請專利範圍第43項之裝置,其中該裝置 電源MOSFET。 為 後 47.如申請專利範圍第45項之裝置,其中該裝置 電源MOSFET。 … 國家標準(CNS)A4規格⑵0 x ---Γ-Γ--f------- --------訂· —-------線 (請先閱讀背面之注意事項再填寫本頁) 21 493262 A8 B8 C8 D8 申請專利範圍 料.如申請專利範圍第46項之裝置,其中該—種導電性係為 49. 如申請專利範圍第47項之裝置’其令該—種導電性係為 P型。 50. 如申請專利範圍第36項之裝置,其中該第二表面會被粗 链化以形成擴伸的面積來改善該裝置的冷卻。 51. 如申請專利範圍第36項之裝置,更包含有_金屬層固設 於該第二表面並延伸遍佈其上。 5 2 ·如申請專利範圍第3 4項之裝置,其中該裝置係選自下列 組群·· MOSFET,Schottky二極體,雙極電晶體,及p/N 二極體。 53.如申請專利範圍第34項之裝置,其中該等焊球係以大於 〇.8mm的間距來列設,並具有大於2〇〇//的直徑。 54·如申請專利範圍第52項之裝置,其中該等焊球係以大於 〇.8mm的間距來列設,並具有大於2〇〇#的直徑。 ------------I --------^ --------各 (請先閱讀背面之注意事項再填寫本頁) 濟 部 智 慧 対 產 局 員 工 消 費 合* 社 印 製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 22
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2007
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Publication number | Publication date |
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WO2001059842A1 (en) | 2001-08-16 |
JP4646284B2 (ja) | 2011-03-09 |
JP2007235150A (ja) | 2007-09-13 |
KR20070010188A (ko) | 2007-01-22 |
KR100699552B1 (ko) | 2007-03-26 |
US20040021233A1 (en) | 2004-02-05 |
CN1315195C (zh) | 2007-05-09 |
EP1258040A1 (en) | 2002-11-20 |
KR20020073547A (ko) | 2002-09-26 |
EP1258040A4 (en) | 2009-07-01 |
AU2001238081A1 (en) | 2001-08-20 |
US20010045635A1 (en) | 2001-11-29 |
US6653740B2 (en) | 2003-11-25 |
KR100721139B1 (ko) | 2007-05-25 |
JP2004502293A (ja) | 2004-01-22 |
CN1401141A (zh) | 2003-03-05 |
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