JP6131114B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP6131114B2 JP6131114B2 JP2013124656A JP2013124656A JP6131114B2 JP 6131114 B2 JP6131114 B2 JP 6131114B2 JP 2013124656 A JP2013124656 A JP 2013124656A JP 2013124656 A JP2013124656 A JP 2013124656A JP 6131114 B2 JP6131114 B2 JP 6131114B2
- Authority
- JP
- Japan
- Prior art keywords
- drain
- external
- terminal
- source
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 203
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 96
- 238000000034 method Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 53
- 229910052710 silicon Inorganic materials 0.000 description 53
- 239000010703 silicon Substances 0.000 description 53
- 239000010410 layer Substances 0.000 description 36
- 238000009792 diffusion process Methods 0.000 description 24
- 230000000052 comparative effect Effects 0.000 description 22
- 239000011229 interlayer Substances 0.000 description 22
- 230000002093 peripheral effect Effects 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000000926 separation method Methods 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 12
- 238000000605 extraction Methods 0.000 description 12
- 238000004088 simulation Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 239000010936 titanium Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum silicon copper Chemical compound 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウト(外部端子のレイアウト)が2行×3列の半導体装置の一例である。
ソース電極部14a〜14cの領域がアクティブセル領域70であり、ソースセル領域50でもある。本実施の形態では、ソース電極14、ソースセル領域50、アクティブセル領域70は、上面視で略同一、すなわち、位置、形状、面積が略同じであるものとし、後述するその他の半導体装置の例においても同様である。
ソース電極14またはアクティブセル領域70を含むソースセル領域50と、ドレイン電極15またはドレインコンタクト領域24を含むドレイン引き出し領域51とが、ソース電極14またはドレイン電極15を囲む3つの対向辺151a〜151c(直線領域)を介して離間対向している。また、アクティブセル領域70とドレインコンタクト領域24とが3つの対向辺151a〜151cを介して対向しているともいえる。図15のような構成により、ドレイン領域(ドレイン引き出し領域51)とソース領域(ソースセル領域50)の境界部分が増えるため、実効的に裏面抵抗を低減し、オン抵抗を低減することができる。
Rds(on)=R(source_chip)+R(back)+R(drain_connect) ・・・(式1)
Rds(on)=R(source_Al)+R(source_chip)+R(back)+R(drain_connect)+R(drain_Al) ・・・(式2)
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウトが2行×3列の半導体装置のその他の例である。
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウトが2行×4列の半導体装置の一例である。
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウトが2行×4列の半導体装置のその他の例である。
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウトが3行×3列の半導体装置の一例である。
図36は、比較例2、本実施の形態の図33及び図34の半導体装置におけるオン抵抗のシミュレーション結果を示している。図36に示すように、比較例2では、裏面抵抗が約0.4mΩとなり、裏面抵抗を含むオン抵抗は約2.3mΩとなった。本実施の形態の図33及び図34は、裏面抵抗が約0.2mΩとなり、裏面抵抗を含むオン抵抗は約1.9〜2.1mΩとなった。本実施の形態では、比較例2と比べて、裏面抵抗を約0.2mΩ低くすることができ、オン抵抗をさらに低減することができた。
以下、図面を参照して本実施の形態について説明する。本実施の形態は、パッドレイアウトが2行×5列の半導体装置の一例である。
また、上記の実施の形態に係る半導体装置では、半導体基板、半導体層、拡散層(拡散領域)などの導電型(p型もしくはn型)を反転させた構成としてもよい。例えば、n型、及びp型の一方の導電型を第1の導電型とし、他方の導電型を第2の導電型とした場合、第1の導電型をp型、第2の導電型をn型としてもよいし、反対に第1の導電型をn型、第2の導電型をp型としてもよい。
2、2a〜2e 外部ソース端子
3、3a〜3e 外部ドレイン端子
4 外部ゲート端子
5 ゲート配線
7 ベース拡散領域
8 ソース拡散領域
9 ベースコンタクト領域
11 ゲート電極
12 ゲート絶縁膜
13 層間絶縁膜
14 ソース電極
14a〜14e ソース電極部
15 ドレイン電極
15a、15b、15d〜15f ドレイン電極部
15c EQR電極
16 ゲートトレンチ
21 エピタキシャル層
24 ドレインコンタクト領域
25 第1のドレインコンタクト領域
26 第2のドレインコンタクト領域
27 バリアメタル
30 ドレインコンタクトトレンチ
31 ドレインプラグ
32 ベースコンタクトトレンチ
33 ベースプラグ
40 ゲートパッド
44 ゲートコンタクトトレンチ
45 ゲートプラグ
48 カバー絶縁膜
49 UBM
50 ソースセル領域
51 ドレイン引き出し領域
52 離間領域
53 外周領域
60 裏面電極
61 Ti層
62 Ni層
63 Ag層
70 アクティブセル領域
71 アクティブセル
100 半導体装置
140 対抗辺
151、151a〜151d 対向辺
152a〜152d 対向辺
153a〜153d 対向辺
154a〜154d 対向辺
200 実装基板
201a〜201c 実装端子
202a〜202d 実装端子
203 実装端子
204〜206 配線
Claims (18)
- 半導体基板表面に形成され、縦型トランジスタを含むアクティブセル領域と、
前記半導体基板表面の上に形成され、前記半導体基板裏面側から前記縦型トランジスタのドレインを引き出すドレイン電極と、
前記ドレイン電極上に形成された外部ドレイン端子と、
前記アクティブセル領域上に前記外部ドレイン端子の周囲の少なくとも3辺で前記ドレイン電極と対向するように形成され、前記縦型トランジスタのソースに接続されるソース電極と、
前記ソース電極上に形成された外部ソース端子と、を備え、
前記外部ドレイン端子と前記外部ソース端子は、隣り合って配置され、
前記外部ドレイン端子と前記外部ソース端子のいずれか一方の端子は、他方の端子を挟み込んで配置されている、
半導体装置。 - 前記ソース電極は、前記ドレイン電極の周囲全体を囲むように形成されている、
請求項1に記載の半導体装置。 - 前記半導体表面に形成され、前記縦型トランジスタのドレインに接続されるドレインコンタクト領域を備え、
前記外部ドレイン端子は、前記ドレインコンタクト領域の上に形成されている、
請求項1に記載の半導体装置。 - 前記アクティブセル領域と前記ドレインコンタクト領域とは、前記少なくとも3辺で対向している、
請求項3に記載の半導体装置。 - 前記アクティブセル領域は、前記ドレインコンタクト領域よりも面積が大きい、
請求項3に記載の半導体装置。 - 前記アクティブセル領域と前記ドレインコンタクト領域の面積比は、約3:2である、
請求項5に記載の半導体装置。 - 前記ソース電極は、前記ドレイン電極よりも面積が大きい、
請求項1に記載の半導体装置。 - 前記ソース電極と前記ドレイン電極の面積比は、約3:2である、
請求項7に記載の半導体装置。 - 半導体基板表面に形成され、縦型トランジスタを含むアクティブセル領域と、
前記半導体基板表面の上に形成され、前記半導体基板裏面側から前記縦型トランジスタのドレインを引き出すドレイン電極と、
前記ドレイン電極上に形成された外部ドレイン端子と、
前記アクティブセル領域上に前記外部ドレイン端子の周囲の少なくとも3辺で前記ドレイン電極と対向するように形成され、前記縦型トランジスタのソースに接続されるソース電極と、
前記ソース電極上に形成された外部ソース端子と、を備え、
前記外部ドレイン端子と前記外部ソース端子は、隣り合って配置され、
さらに、前記半導体基板上に形成され、前記縦型トランジスタのゲートに接続される外部ゲート端子を備え、
前記外部ドレイン端子、前記外部ソース端子及び前記外部ゲート端子は、少なくとも2行×3列のパッドレイアウトで配置されている、
半導体装置。 - 前記外部ドレイン端子を含む列と、前記外部ソース端子を含む列とが、交互に並んで配置されている、
請求項9に記載の半導体装置。 - 前記外部ドレイン端子が複数形成された前記ドレイン電極は、前記外部ドレイン端子の周囲で前記ソース電極により分離されている、
請求項9に記載の半導体装置。 - 前記半導体基板上の第1行目に、前記外部ゲート端子、前記外部ドレイン端子、前記外部ソース端子の順に並んで配置され、
前記半導体基板上の第2行目に、前記外部ソース端子、前記外部ドレイン端子、前記外部ソース端子の順に並んで配置されている、
請求項9に記載の半導体装置。 - 前記半導体基板上の第1行目に、前記外部ゲート端子、前記外部ソース端子、前記外部ドレイン端子の順に並んで配置され、
前記半導体基板上の第2行目に、前記外部ドレイン端子、前記外部ソース端子、前記外部ドレイン端子の順に並んで配置されている、
請求項9に記載の半導体装置。 - 前記外部ソース端子の数は、前記外部ドレイン端子の数よりも多い、
請求項1に記載の半導体装置。 - 前記ドレイン電極と前記ソース電極との間の領域に前記少なくとも3辺に沿って形成され、前記縦型トランジスタのゲートに接続されるゲート配線を備える、
請求項1に記載の半導体装置。 - 前記半導体基板の外周を囲むように形成され、前記ドレイン電極に接続された等電位リング電極を備える、
請求項1に記載の半導体装置。 - 半導体基板表面に、縦型トランジスタを含むアクティブセル領域を形成し、
前記半導体基板表面に、前記半導体基板裏面側から前記縦型トランジスタのドレインを引き出すドレインコンタクト領域を形成し、
前記ドレインコンタクト領域上に、外部ドレイン端子を配置するためのドレイン電極を形成し、
前記アクティブセル領域上に、前記外部ドレイン端子の配置位置の周囲の少なくとも3辺で前記ドレイン電極と対向するように、前記縦型トランジスタのソースに接続されるソース電極を形成し、
前記ドレイン電極上に前記外部ドレイン端子を形成し、
前記ソース電極上に外部ソース端子を形成し、
前記外部ドレイン端子と前記外部ソース端子は、隣り合って配置され、
前記外部ドレイン端子と前記外部ソース端子のいずれか一方の端子は、他方の端子を挟み込んで配置されている、
半導体装置の製造方法。 - 半導体基板表面に、縦型トランジスタを含むアクティブセル領域を形成し、
前記半導体基板表面に、前記半導体基板裏面側から前記縦型トランジスタのドレインを引き出すドレインコンタクト領域を形成し、
前記ドレインコンタクト領域上に、外部ドレイン端子を配置するためのドレイン電極を形成し、
前記アクティブセル領域上に、前記外部ドレイン端子の配置位置の周囲の少なくとも3辺で前記ドレイン電極と対向するように、前記縦型トランジスタのソースに接続されるソース電極を形成し、
前記ドレイン電極上に前記外部ドレイン端子を形成し、
前記ソース電極上に外部ソース端子を形成し、
前記半導体基板上に、前記縦型トランジスタのゲートに接続される外部ゲート端子を形成し、
前記外部ドレイン端子と前記外部ソース端子は、隣り合って配置され、
前記外部ドレイン端子、前記外部ソース端子及び前記外部ゲート端子は、少なくとも2行×3列のパッドレイアウトで配置されている、
半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013124656A JP6131114B2 (ja) | 2013-06-13 | 2013-06-13 | 半導体装置及びその製造方法 |
US14/282,863 US9431491B2 (en) | 2013-06-13 | 2014-05-20 | Semiconductor device and method of manufacturing the same |
CN201410260734.3A CN104241207B (zh) | 2013-06-13 | 2014-06-12 | 半导体及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013124656A JP6131114B2 (ja) | 2013-06-13 | 2013-06-13 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015002197A JP2015002197A (ja) | 2015-01-05 |
JP6131114B2 true JP6131114B2 (ja) | 2017-05-17 |
Family
ID=52018491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013124656A Active JP6131114B2 (ja) | 2013-06-13 | 2013-06-13 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9431491B2 (ja) |
JP (1) | JP6131114B2 (ja) |
CN (1) | CN104241207B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9690379B2 (en) | 1995-11-30 | 2017-06-27 | Immersion Corporation | Tactile feedback interface device |
US11769829B1 (en) | 2021-10-15 | 2023-09-26 | Nuvoton Technology Corporation Japan | Semiconductor device |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015153760A (ja) * | 2014-02-10 | 2015-08-24 | 株式会社東芝 | 半導体装置 |
JP2016164962A (ja) * | 2015-02-26 | 2016-09-08 | ルネサスエレクトロニクス株式会社 | 半導体チップおよび半導体装置並びに電池パック |
US10164447B2 (en) * | 2015-02-26 | 2018-12-25 | Renesas Electronics Corporation | Semiconductor chip, semiconductor device and battery pack |
TWI690083B (zh) | 2015-04-15 | 2020-04-01 | 杰力科技股份有限公司 | 功率金氧半導體場效電晶體及其製作方法 |
US10692863B2 (en) | 2016-09-30 | 2020-06-23 | Rohm Co., Ltd. | Semiconductor device and semiconductor package |
JP6941502B2 (ja) * | 2016-09-30 | 2021-09-29 | ローム株式会社 | 半導体装置および半導体パッケージ |
KR102699046B1 (ko) | 2016-12-15 | 2024-08-27 | 삼성전자주식회사 | 수직형 트랜지스터를 구비하는 집적 회로 및 이를 포함하는 반도체 장치 |
US11164813B2 (en) * | 2019-04-11 | 2021-11-02 | Cree, Inc. | Transistor semiconductor die with increased active area |
US12074079B2 (en) | 2019-04-11 | 2024-08-27 | Wolfspeed, Inc. | Wide bandgap semiconductor device with sensor element |
US11662371B2 (en) | 2020-12-08 | 2023-05-30 | Wolfspeed, Inc. | Semiconductor devices for improved measurements and related methods |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6653740B2 (en) | 2000-02-10 | 2003-11-25 | International Rectifier Corporation | Vertical conduction flip-chip device with bump contacts on single surface |
JP2002353452A (ja) | 2001-05-25 | 2002-12-06 | Toshiba Corp | 電力用半導体素子 |
TW200711131A (en) * | 2005-08-15 | 2007-03-16 | Fwu-Iuan Hshieh | High density trench MOSFET with low gate resistance and reduced source contact space |
CN100573909C (zh) * | 2005-12-06 | 2009-12-23 | 三洋电机株式会社 | 半导体装置及其制造方法 |
US8159024B2 (en) * | 2007-04-20 | 2012-04-17 | Rensselaer Polytechnic Institute | High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance |
JP5132977B2 (ja) * | 2007-04-26 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2009088004A (ja) * | 2007-09-27 | 2009-04-23 | Sanyo Electric Co Ltd | 半導体装置 |
US9306056B2 (en) * | 2009-10-30 | 2016-04-05 | Vishay-Siliconix | Semiconductor device with trench-like feed-throughs |
US8502314B2 (en) * | 2011-04-21 | 2013-08-06 | Fairchild Semiconductor Corporation | Multi-level options for power MOSFETS |
-
2013
- 2013-06-13 JP JP2013124656A patent/JP6131114B2/ja active Active
-
2014
- 2014-05-20 US US14/282,863 patent/US9431491B2/en active Active
- 2014-06-12 CN CN201410260734.3A patent/CN104241207B/zh active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9690379B2 (en) | 1995-11-30 | 2017-06-27 | Immersion Corporation | Tactile feedback interface device |
US11769829B1 (en) | 2021-10-15 | 2023-09-26 | Nuvoton Technology Corporation Japan | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
CN104241207B (zh) | 2019-08-20 |
JP2015002197A (ja) | 2015-01-05 |
CN104241207A (zh) | 2014-12-24 |
US9431491B2 (en) | 2016-08-30 |
US20140367770A1 (en) | 2014-12-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6131114B2 (ja) | 半導体装置及びその製造方法 | |
US11367738B2 (en) | Semiconductor device | |
WO2014163058A1 (ja) | 半導体装置 | |
WO2022201903A1 (ja) | 半導体装置 | |
CN104347719B (zh) | 半导体装置 | |
CN111033720B (zh) | 半导体集成电路装置 | |
JP2021184443A (ja) | 半導体装置 | |
JP6177300B2 (ja) | 半導体装置 | |
JP2012089701A (ja) | 半導体装置 | |
JP2012216578A (ja) | 絶縁ゲート型半導体装置 | |
JP5061443B2 (ja) | 横型絶縁ゲートバイポーラトランジスタ | |
JP2012028380A (ja) | 半導体装置 | |
JP5841693B2 (ja) | 半導体装置 | |
JP2022144775A (ja) | 半導体装置 | |
KR101366228B1 (ko) | 전력 반도체 소자 | |
JP2020150031A (ja) | 半導体装置 | |
JP2017168755A (ja) | 半導体装置およびそれを用いたインバータ回路 | |
JP2012134522A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160210 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161220 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170126 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170328 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170417 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6131114 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |