TW473882B - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
TW473882B
TW473882B TW088110698A TW88110698A TW473882B TW 473882 B TW473882 B TW 473882B TW 088110698 A TW088110698 A TW 088110698A TW 88110698 A TW88110698 A TW 88110698A TW 473882 B TW473882 B TW 473882B
Authority
TW
Taiwan
Prior art keywords
electrode
semiconductor wafer
aforementioned
input
output
Prior art date
Application number
TW088110698A
Other languages
English (en)
Inventor
Iwamichi Kohjiro
Sakae Kikuchi
Yasuhiro Nunogawa
Shizuo Kondo
Tetsuaki Adachi
Original Assignee
Hitachi Ltd
Hitachi Tobu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP19080998A external-priority patent/JP3946874B2/ja
Priority claimed from JP04104599A external-priority patent/JP3667136B2/ja
Application filed by Hitachi Ltd, Hitachi Tobu Semiconductor Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW473882B publication Critical patent/TW473882B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • H01L23/49844Geometry or layout for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56Modifications of input or output impedances, not otherwise provided for
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602Combinations of several amplifiers
    • H03F3/604Combinations of several amplifiers using FET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6611Wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6627Waveguides, e.g. microstrip line, strip line, coplanar line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
    • H01L2223/6655Matching arrangements, e.g. arrangement of inductive and capacitive components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45669Platinum (Pt) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801Structure
    • H01L2224/48011Length
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494Connecting portions
    • H01L2224/4943Connecting portions the connecting portions being staggered
    • H01L2224/49433Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01021Scandium [Sc]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1016Shape being a cuboid
    • H01L2924/10161Shape being a cuboid with a rectangular active surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15173Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1903Structure including wave guides
    • H01L2924/19032Structure including wave guides being a microstrip line type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/12A bias circuit for some stages being shown using transmission lines
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/168Two amplifying stages are coupled by means of a filter circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/222A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/255Amplifier input adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/318A matching circuit being used as coupling element between two amplifying stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/387A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/408Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/411Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/423Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/451Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/543A transmission line being used as coupling element between two amplifying stages
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38Impedance-matching networks
    • H03H7/383Impedance-matching networks comprising distributed impedance elements together with lumped impedance elements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Amplifiers (AREA)
  • Wire Bonding (AREA)
  • Microwave Amplifiers (AREA)

Description

— — — — — — — — — — · 1111 (請先閱讀背面之注意事項再广烏本頁) · --線· 經濟部智慧財產局員工消費合作社印製 473382 A7
發明之背景 本發明係關於一種半導體裝置,尤其是關於一種適用於 多級式放大電路構成之半導體裝置的有效技術。 作爲半導體裝置’有組裝於PDC( Personal Digital Cellular :個人數位細胞)方式之汽車電話及行動電話、或 P H S ( Personal Handyphone System :個人手機系統)方式之 行動電話等的攜帶式通訊機器内的高頻功率放大器(高頻功 率模組)。此高頻功率放大器,·係爲連接多級複數個放大裝 置的多級式放大電路構成。 前述高頻功率放大器,係將其一主面上形成有放大裝置 之半導體晶片搭載於配線基板之一主面側,且利用導電性 <金屬線電氣連接形成於半導體晶片之一主面上的電極和 形成於配線基板之-主面上的電極。放大裝置,係爲電氣 連接例如複數個場效電晶體之各個的構成,而放大裝置之 閘極端子(輸入部)係與形成於半導體晶片之一主面上的晶 片側輸入用電極電氣連接’而放大裝置之没極端子(輸出^ ,與形成於半導體晶片之一主面上的晶片側輸出用電極電 乱連接。晶片侧輸入用電極係配置於半導體晶片之一邊 侧,而晶片側輸出用電極係配置於與半導體晶片之一逢相 ,的另it側。放大裝置之源極端子係與形成於與半導體 :片,一主面相對之另-面(背面)的背面電極電氣連接, 係將其電位固定於基準電位。晶片側輸入用 i和^形成與半導體晶片之一邊相對且介以輸入用金屬 /成於配線基板之-主面上的基板側輸人用電極電氣
本紙張尺^ X 297公釐)
經濟部智慧財產局員工消費合作社印制衣 連接’而印片侧輸出用電極,係形成與半導體晶片之另一 邊相對且;丨以輸出用金屬線與形成於配線基板之一主面上 的基板側輸出用電極電氣連接。 然而’在W述高頻功率放大器中,爲了謀求小型化及低 h 2化’雖%成在一個半導體晶片上形成複數個放大裝置 ’ Μ例如’在一個半導體晶片上形成二個放大裝 置時’由於前級之放大裝置和後級孓放大裝置的輸入輸出 爲相反所以輸入用金屬線和輸出用金屬線很接近,而有 因此金屬線間之互感作用而使高頻特性惡化的問題。此問 題,在流動之功率差較大的前級輸入用金屬線和後級之輸 出用金屬線之間尤爲顯著。 因此,用以防止因金屬線間之互感作用而使高頻特性惡 化的技術,例如已·記載於日本專利特開平9-260412號公報 中此技術,係在晶片側輸入用電極和晶片側輸出用電極 之間形成晶片側搭接用電極,而在基板側輸入用電極和基 板側輸出用電極之間形成基板侧搭接用電極,並利用金屬 線電氣連接於此搭接用電極間,且將晶片側搭接用電極或 基板側搭接用電極之電位固定在基準電位,藉以防止因輸 入用金屬線和輸出用金屬線之互感作用而使高頻特性厗 化。 ' 心 又’使用電晶體之高頻功率放大器模組—種係 PDC(Personal Digital Cellular :個人數位細胞)方式、gsm (Grobal System for mobile communications :蔣氣、s、 π初遮訊全球 系統)方式等的移動體通信之行動電話的關鍵元件, . Μ--------^----------^ (請先閱讀背面之注意事項再产:本頁) -5-
473332 A7 B7 經濟部智慧財產局員工消費合作社印製 3五、發明說明() 其需求已急速發展著。又,其規格,相對於移動體通訊係 除了高頻特性之外,還被要求小型化及低價格化。 響應此要求之一個方法係記載於日本專利特許公報第 2755250號(特開平9-260412號)中。如圖21之平面圖及圖 22之斜視圖所示,藉由在一個半導體晶片1〇〇〇上接近配置 二個電晶體2000、3000,就可使之小型化及低價格化。 又,初級電晶體2000之搭接用輸入電極2000b和配線基板 之搭接用電極7000d係利用輸入搭接金屬線9000d予以連 接。第二級電晶體3000之搭接用輸出電極3000c和配件基 板6000之搭接用電極7000a係利用輸出搭接金屬線9000 a予 以連接。半導體晶片1000上之搭接用電極10000a和配線基 板6000上之搭接用電極12000a係利用遮蔽用搭接金屬線 13000a予以連接。遮蔽(shield)用搭接金屬線13000a係設在 輸入搭接金屬線9000d和輸出搭接金屬線9000a之間,且其 兩端之搭接用電極10000a和12000a係經由各自形成於半導 體晶片1000及配線基板上的連絡窗(Via Hole(未圖示))而 高頻接地。藉由設置此遮蔽用搭接金屬線13000a,就可減 低因輸入搭接金屬線9000d和輸出搭接金屬線9000a之間的 互感結合而可改善高頻輸出入端子間的隔離(isolation)惡 化,且可提高高頻波特性。 輸入搭接金屬線9000d和輸出搭接金屬線9000a之間之互 感耦合的問題,係因初級電晶體2000和第二級電晶體3000 相反並設在輸出入之位置上,所以會發生兩者接近的結 果。此問題在初級電晶體2000之輸入搭接金屬線9000d和 -6- -------------裝--------訂---------線 (請先閱讀背面之注意事項再ri本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 473832 經濟部智慧財產局員工消費合作社印製 A7 B7 4 五、發明說明() 第二級電晶體3000之輸出搭接金屬線9000a之間尤爲顯 著。此與輸入於初級電晶體2000内之高頻信號功率相較, 係以由第二級電晶體3000輸出之高頻信號功率較大20dB〜 30dB(100〜1000倍),且依從輸出至輸入之正反饋之動作情 形而定。另一方面,初級電晶體2000之輸出搭接金屬線 9000c和第二級電晶體3000之輸入搭接金屬線9000b雖也接 近,但是流至兩者的高頻信號功率之比會小於0 d B ( 1倍)以 下,故不會發生高頻特性惡化的問題。 另夕卜,在圖21、圖22中,2000a、3000a係電晶體的本體 部分,2000d、3000d係電晶體的源極電極,2000c係初級 電晶體2000的搭接用輸出電極,3000b係第二級電晶體 3000的搭接用輸入電極,4000係接地電極、7000b、7000c 係配線基板6000的搭接用電極,8000a〜8000d係引線電 極,104 爲鑄孔(cavity)。 發明之概述 然而,本發明人等在檢討前述技術後的結果,發現以下 問題點。 基板側搭接用電極,係配置於基板側輸入用電極和基板 侧輸出用電極之間。亦即,基板側輸入用電極、基板側搭 接用電極、基板側輸出用電極之各個,係沿著半導體晶片 之一邊而配置在一直線上。 基板側電極,由於一般係依網狀印刷法形成,所以其佔 有面積會大於依光蚀刻技術所形成的晶片側電極之佔有面 積。又,爲了縮短傳輸路徑而可在基板侧電極之正下方形 -7- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------裝--------訂---------線 (請先閱讀背面之注意事項再v鸟本頁)
經濟部智慧財產局員工消費合作社印製 473332 五、發明說明() 成貫穿孔。此貫穿孔配線之平面方向的面積(外形尺寸)由 於爲了謀求低電阻化而必須做某種程度加大,所以並基板 側電極之佔有面積會變大。更且,由於貫穿孔之加I精度 本身也低,户斤以其基板側電極之佔有面積會變大。因而, 在將基板側輸人用電極、基板側搭接用電極、基板侧輸出 用電-極之各個沿著半導體晶片之一邊而配置在一直線上 時,該等的電極排列就會變長,且晶片側輸入用電極和基 板侧輸入用電極會變成不相對.,同時晶片侧輸出用電極和 基板側輸出用電極也會變成不相對,所以輸入用金屬線及 輸出用金屬線之長度會變長。當輸入用金屬線及輸出用金 屬線之長度變長時,由於電感會增加,高頻特性會惡化, 所以就必須加寬前級放大裝置和後級放大裝置之間隔來縮 短金屬線長度,而半導體晶片之佔有面積會增加,而成爲 阻礙高頻功率放大器之小型化的主要因素。 又’利用圖1 5説明上述習知技術之遮蔽用搭接金屬線 13000a之效果。圖15係相對於長度i mm(接近實物的長度) 之平行的二條輸出入搭接金屬線之搭接部的間隔d,而算 出放大器之輸出入搭接金屬線間的耦合係數(互感(單位: nH))者。在此,表示耦合係數012之部位的虛線,係顯示 當搞合係數爲0.12以下時放大器會穩定動作的情形。此所 謂0· 12的値’係從顯示耦合係數和放大器之穩定係數之關 係的圖1 6中求出。穩定係數爲1以上放大器就..會穩定動 作。在此,搭接部之間隔d,係以最接近之二個搭接金屬 線之搭接部之中心間的距離來加以定義。 -8- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------^----------------- (請先閱讀背面之注意事項再本頁) 473SS2 經濟部智慧財產局員工消費合作社印製 A7 _______B7_________ 五、發明說明() 如圖15所示,在施行所謂設置遮蔽用搭接金屬線之對策 的上述習知技術之情況,與非此對策之情況(圖中,表示爲 ”、、對裘」)相較,搞合係數會變小,而高頻特性會提高。 又,耦合係數爲〇· 12以下之搭接部之間隔d的範圍會擴大, 而設計之自由度會增大。再者,由於可將搭接部之間隔d 縮小至0.55 mm,所以可縮小晶片面積,且可使模組小型 化及減低成本。 但是,在現實上,由於係在·遮蔽用搭接金屬線13〇⑽&之 兩端•聯增加連絡窗的電感,所以在上述習知技術中無法 獲得充分的高頻特性提高。 本發明I目的係在於提供一種可謀求半導體裝置之小型 化的技術。 土 本發明I目的係在於提供_種可提高高頻特性的高頻功 率放大器模組。 " 本發明之前述目的及其他目的與新特徵,依本説明書之 記載及附圖應可更加明白。 曰 若要簡單説明本發明中所揭示之發明中代表性的概要, 則可如下所述。 -種半導體m具有:半導^片,其平面係以方 形狀㈣成;配線基板,於其一主面側搭載有前述半導體 晶片;第一電極,形成於前述半導體晶片之一主面的第一 區域上,且配置在前述半導體晶片之一邊側上第—罘 裝置,形成於前述半導體晶片之一主面的第_區== 其輸入部與前述第一電極電氣連接;第-+ 吊一电極,形成於前 ---------------------訂--------- (請先閱讀背面之注意事項再"塔寫本頁) -9-
473382 A7 五、發明說明(1 述半導體晶片之一主面的第二區域上,且配冒 體晶片之—邊側上;第二放大裝置,形成於i述 f之一主面的第二區域上,丑其輸出部與前述第二 軋連接;弟二電極m前述半導體晶片之 域和第二區域之間的第三區域上;第四電極一:: 與前-述半導體晶片之-邊相對而形成於前述配線基=成 王面上,且介以卜金屬線與前述第—電極電氣 五電極,設置成與前述半導體·晶片之一目 罘 述,之一主面一第二金屬邊:^^ 極%乳連接;以及第六電極,設置成與前述半導, 一邊相對而形成於前述配線基板之_主面上,且 位被固定在基準電位的第三金屬線與前述第三電極電氣 其中W述第六電極,係配置在比前述第五電極離 可述半導體晶片之-邊的位置上。前述第四電極,係配置 在自前述半導體晶片之-邊起之距離大致與前述第五電二 相同的位置上’或纽置在比前述第六電極還遠離前述半 導體晶片之一邊的位置上。 若依據上述之手段,則由於可縮小相當於第六電極之佔 有面積的部分’即縮小第四電極和第五電極之間隔,所以 可縮小半導體晶片之第一區域和第二區域之間隔。結果, 由於可縮小半導體晶片之佔有面積,所以可謀求半;體裝 置之小型化。 又’上述目的,藉由下述之手段設計高頻功率放大器模 ㈣可達H在以電介質材料爲基體之配線基板上設 -----^--- (請先閱讀背面之注咅?事項再产丨本頁) .. --線. 經濟部智慧財產局員工消費合作社印制农 -10
473382 A7 五、發明說明(8 ) 置半導體晶片的高頻功率放大器模組中,在半導體晶片 上’設置二級以上的放大級電晶體;對該等放大級電晶體 輸入高頻功率用的搭接用輸入電極;以及從該等放大級電 阳體以輸出高頻功率用的搭接用輸出電極,而將第一輔助 ”泉和第一輔助線所成的角度設在7 2〜180度之範圍内,且將 搭接-用輸入電極和搭接用輸入電極之搭接部的間隔設在〇 3 以下〇.8mm以下之範圍内,其中第一輔助線係用以連 …輸入搭接金屬線之兩端的搭、接部彼此之間,而輸入搭接 金屬線係用以連接對應於某一個放大級電晶體之搭接用輸 入私極和配線基板者,又,第二輔助線係用以連結輸出搭 接金屬線 < 兩端的搭接部(其中心部)彼此之間,而輸出搭 接金屬線係用以連接對應於位在該第一放大級電晶體之次 級的放大級電晶體之搭接用輸出電極和配線基板者。 在此,無關於所謂〇·3 mm以下〇·8 mm以下之搭接部間隔 的條件,、只要在上述二個放大級電晶體之穩定係數成幻 以上的乃式下設計高頻功率放大器模組的話即可達成目 的。 星_式之簡單説明 圖1顯示本發明之實施形態」之高頻功率放大器之外觀構 成的斜視圖。 圖2爲前述鬲頻功率放大器的等效電路圖。 圖3爲與圖2所示之一點鏈線所包圍之部分相對應的配線 基板之主要部位平面圖。 -11 ϋ狀財賴家鮮(CNS)A4規格(21G x 297i i--------^---------^ (請先閱讀背面之注咅?事項再F“本頁) 473882 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明() 圖4爲圖3之主要部位斜視圖。 圖5爲圖3之主要部位擴大平面圖。 圖6爲組裝於前述高頻功率放大器内之半導體晶片之電晶 體形成區域中的主要部位截面圖。 圖7爲前述半導體晶片之隔離區域中的主要部位截面圖。 圖8爲本發明之實施形態2之高頻功率放大器之配線基板 的主要部位平面圖。 圖9爲本發明之實施形態3之·高頻功率放大器之配線基板 的主要部位平面圖。 圖1 0爲本發明之實施形態4之高頻功率放大器之配線基 板的主要部位平面圖。 圖1 1爲本發明之實施形態5之二級功率放大器模組的主 要邵位平面圖。 圖1 2爲本發明之實施形態5之二級功率放大器模組的等 效電路圖。 圖13顯示本發明之實施形態5之二級功率放大器模組之 外觀構成的平面圖。 圖1 4馬本發明之實施形態5之二級功率放大器模組的主 要邵位斜視圖。 人圖15顯示本發明及習知技術之輸出入搭接金屬線間之輕 合係數和搭接部間隔的關係圖。 圖16顯示本發明人所檢討之輸出人搭接金屬線間之核合 係數和放大器之穩定係數的關係圖。 口 圖17顯示本發明人所檢討之輸出人搭接金屬線間之镇合 本紙張尺度適用Tiiii^(CNS)A4規格⑽χ ---------------------訂·--------線 (請先閱讀背面之注意事項再νλ本頁) -12- 47388; 經濟部智慧財產局員工消費合作社印製 1A凹部 2 A、2 D基板側輸入用電極 2 C、2 F基板側搭接用電極 4 基準電位用外部端子 5A第一區域 5C第三區域(隔離區域) 6 B、6 D晶片側輸出用電極 7A、7E輸入用金屬線 7 C、7 F金屬線 „ R1〜R4電阻元件 PW1、PW2、PW3放大裝置 2000 初級電晶體 2000b 搭接用輸入電極 A7 B7 10 - -- 五、發明說明() 係數和角度的關係圖。 圖18爲本發明之實施形態6之三級功率放大器模組的主 要部位平面圖。 圖1 9爲本發明之實施形態7之三級功率放大器模組的主 要部位平面圖。 圖2 0爲本發明之實施形態8之二級功率放大器模組的主 要部位平面圖。 圖2 1爲習知技術之二級功率放大器模組的平面圖。 圖2 2爲習知技術之二級功率放大器模組的斜視圖。 元件編號之説明 1 配線基板 1B導電板 2 B、2 E基板側輸出用電極 3 貫穿孔配線 5 半導體晶片 5 B弟二區域 6 A、6 E晶片侧輸入用電極 6 C、6 F晶片側搭接用電極 7B、7D輸出用金屬線 C1〜C11電容元件 STL1〜STL3微波導片線路 1000 半導體晶片 2000a電晶體之本體部分 -13- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 裝--------訂---------線 (請先閱讀背面之注意事項再<寫本頁) 47383 經濟部智慧財產局員工消費合作社印製 A7 B7 11 一 五、發明說明() 2000c 搭接用輸出電極 2000d 源極電極 3000 第二級電晶體 3000a 電晶體之本體部分 3000b 搭接用輸入電極 3000c 搭接用輸出電極 3000d 源極電極 4000 接地電極 6000 7000a- 配線基板 JOOOd配線基板6000之搭接用電極 8000a〜8000d引線電極 9000a 輸出搭接金屬線 9000b 輸入搭接金屬線 9000c 輸出搭接金屬線 9000d 輸入搭接金屬線 10000a、10000b搭接用電極 12000a 13000a l、12000b 搭接用電極 l、13000b 遮蔽用搭接用電極 101 碎晶片 102初級電晶體 102a 閘極(輸入電極) 102b 汲極電極(輸出電極) 103 第二級電晶體 103a 閘極(輸入電極) 103b 没極電極(輸出電極) 104鑄孔 105 輸入搭接金屬線 106輸出搭接金屬線 107 輸入搭接金屬線 108輸出搭接金屬線 109 輸入搭接金屬線 110輸出搭接金屬線 113 配線基板 114輸出級電晶體 〃 114a 閘極電極(輸入電極) 114b 汲極電極(輸出電極) 121 輸入匹配電路之端部 122級間匹配電路之端部 122 級間匹配電路之端部 124輸出匹配電路之端部 125 輸入匹配電路 126級間匹配電路 127 輸出匹配電路 Pin高頻信號輸入端子 -14- -------------裝--------訂---------線 (請先閱讀背面之注意事項再W鳥本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 473SS. 經濟部智慧財產局員工消費合作社印製 A7 B7 12 -------- 五、發明說明()
Pout咼頻號輸出端子 Vgg閘極電壓施加端子
Vdd汲極電壓施加端子 201遮蔽用搭接金屬線 202電極 203連絡窗 204 遮蔽配線 較佳實施形態之説明_ 以T,係就本發明之構成,同時就本發明適用於組裝在 汽車電話、行動電話等攜帶式通信機器内的高頻功率放大 器(高頻功率模組)之實施形態加以説明。 實施形態1 圖1顯示本發明之實施形態丨之高頻功率放大器之外觀構 成的斜視圖;圖2爲前述高頻功率放大器的等效電路圖; 圖J爲與圖2所tf之-點鏈線所包圍之部分相對應的配線基 板之主要部位平面圖;圖4爲圖3之主要部位斜視圖,·圖5 爲圖3之主要部位擴大平面圖;圖6爲組裝於前述高頻功率 放大器内之半導體晶片之電晶體形成區域中的主要部位截 面圖;圖7爲前述半導體晶片之隔離區域中的主要部位截 面圖。 如圖1所示,本實施形態之高頻功率放大器,係 配線基板1之一主面上重疊有蓋8,外觀上係形成扁平的矩 形體構造。配線基板丨,係由多層配線構造的陶瓷基板所 形成,而其平面係由方形狀(本實施形態中爲長方形狀)形 成。蓋8,係由導電性之金屬材料所形成,而其平面係由 方形狀(本實施形態中爲長方形狀)形成。此蓋8,爲了使之 保持遮蔽效果而將其電位固定在基準電位(例如〇[v])上。 --------------裝--------訂---------線 (請先閱讀背面之注意事項再球寫本頁) 15- 47338, 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明() 如圖2所示,前述高頻功率放大器,係由多級式放大電路 所構成。此多級式放大電路,只要係由電容元件 C1〜C11、電阻元件R1〜R4、微波導片(micr〇strip)線路 STL1〜STL3、放大裝置PW1〜放大裝置Pw3等所構成。 、放大裝置PW1、PW2、PW3之各個,係形成電氣並聯連 接複數個場效電晶體之各個的構成。放大裝置p w丨,係以 閘極之總延伸長度爲4000[ " m]程度所形成,放大裝置 PW2,係以閘極之總延伸長度爲32〇〇[jUm]程度所形成, 放大裝置PW3,係以閘極之總延伸長度爲8〇〇〇卜叫程度 所形成。 、 放大裝置PW 1之閘極端子(輸入部)係與施加有高頻功率 (例如l[mW])的輸入用外部端子Pin電氣連接,放大裝置 pw汲極端子(輸出部)係與後級之放大裝置pw2的閘極 端子(輸入部)及微波導片線路STL1之一端側電氣連接。放 大裝置PW2之汲極端子(輸出部)係與後級之放大裝置pw3 的閘極端子(輸入部)及微波導片線路81112之一端側電氣連 接。放大裝置PW3之汲極端子(輸出部)係與輸出用外部端 子Pout電氣連接。 放大裝置PW1、PW2、PW3之各個的罈極端子,係與其 電位被固定在基準電位(例如〇[v])的基準電位外部端子電 氣連接。微波導片線路STL1、STL2、STU之各個的另一 端側,係與施加有電源電位(例如3·5[ν])的電源/電位用外 部端子vDD電氣連接。另外,放大裝置pwi、pw2、pw3 之各個的閘極端子上電氣連接有外部端子,而在此外部 -16- 本紙張尺度適用中國國家標準(CNS〉A4規格(210 X 297公爱) ---------------------訂·-------- (請先閱讀背面之注意事項再#寫本頁) 473332 A7
經濟部智慧財產局員工消費合作社印製 =子VG上施加有用以調整輸出功率的電壓(AP 率自動控制信號)。 刀 放大裝置PW1、PW2(各個,係形成於如圖3所示 =體晶片5上,放大裝置PW3雖未圖示,但是其係形成於 與半導體晶片5不同的其他半導體晶片上。半導體晶片5係 搭載在形成於配線基板1之一古 、 ·、 之王面上的凹邵1A内,其他的 導植晶片係搭載在形成於配線基板丨之一主面上的其他 凹部内。、亦即’形成有放大裝.置的半導體晶片係搭载:配 泉基板1之主面上。半導體晶片5、其他的半導體晶片之 各個平面係由方形狀(本實施形態中爲長方形狀)所形成。 另外,關於形成有放大裝置PW3的其他半導體晶片 以後之説明。 如圖4所示,搭載有半導體晶片5之凹部1A的底面形成有 導電板1B。導電板1B,係介以在其正下方所形成的貫穿 孔配線3,與形成於與配線基板丨之一主面相對的另一主面 (背面)上的基準電位用外部端子4電氣連接。此基準電位用 外邵端子4之電位係固定在例如〇[v]電位上。另外,前述 輸入用外部端子Pin、輸出用外部端子p〇ut、電源電位 部端子VDD、外部端子Vg之各個也是形成於配線基板丨之 背面。 如圖5所示,放大裝置PW1係形成於半導體晶片5之_主 面的第一區域5A上。放大裝置PW1之閘極端子,係形成半 導體晶片5之一主面的第一區域5A上,且與配置於半導體 晶片5 1 —邊5 X側(本實施形態中爲一長邊側)的晶片側輸 -17 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I n n n n I n n t— n ϋ n I · I n n n I n n 一 0, · n - j 1· n ϋ I f請先閱讀背面之注意事項再/贫爲本頁) 473382
發明說明( 經濟部智慧財產局員工消費合作社印製 入用電極6A電氣連接。 采成车填姊日又放大裝置pwi之汲極端子,係 %成半導月豆叩片5之一 士 ·7Γ·上人^ , 面的罘一區域5Α上,且與配置於 與半導體晶片5之一邊 建5Χ相對的另一邊5 γ側(本實施形態 中爲另一長邊側)的晶片側輸出用電極6D電氣連接。 放大裝置PW2係形成於半導體晶片5之一主面的第二區 域5&上放;^裝置PW2〈;及極端丨,係形成於半導體晶片 5(-王自的第二區域5β±,且與配置於半導體晶片$之一 邊5X側的晶片側輸出用電極6,B電氣連接。又,放大裝置 PW2之閘極端子,係形成於半導體晶片5之—主面的第二 區域5B上’ JL與配置於半導體晶片5之另一邊⑺則的晶片 側輸入用電極6E電氣連接。 放大裝置PW1、PW2之各個的源極端子,雖在後面有詳 細說明,但是其係與形成於與半導體晶片5之一主面相對 的另一主面(背面)上的背面電極電氣連接。 在半導體晶片5之一主面的第一區域5 a和第二區域56之 間,形成有用以電氣隔離該等區域間的第三區域(隔離區 域)5C。此第三區域5C上,形成有配置於半導體晶片5之 一邊5X側的晶片側搭接用電極6C及配置於半導體晶片5之 另一邊5 Y側的晶片側搭接用電極6 ρ。 晶片側輸入用電極6 A,係介以輸入用金屬線7 a與設置 成與半導體晶片5之一邊5X相對而形成於配線基板1之一主 面上的基板側輸入用電極2A電氣連接。基板側輸入用電極 2 A ’係介以其正下方所形成的貫穿孔配線3及内部配線, 與形成於配線基板1之背面的輸入用外部端子(Pin)電氣連 -18 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------^--------- (請先閱讀背面之注意事項再<為本頁) 473382 A7 B7 五、發明說明( 16 經濟部智慧財產局員工消費合作社印製 接。 印片側輸出用電極6 β,係介以輸出用金屬線7 B與設置成 與半導體晶片5之一邊5χ相對而形成於配線基板〗之一主面 上的基板侧輸出用電極2]8電氣連接。基板側輸出用電極 2 Β,係介以其正下方所形成的貫穿孔配線3及内部配線, 與設置成與形成有放大裝置pw3之其他半導體晶片之一邊 相對而形成於配線基板丨之一主面的基板輸入用電極電氣 連接。 . 曰口片側搭接用電極6 C,係介以金屬線7 C與設置成與半導 體晶片5之一邊5 X相對而形成於配線基板丨之一主面上的基 板側搭接用電極2 C電氣連接。基板側搭接用電極2 c,係 J以其正下方所形成的貫穿孔配線3及内部配線,與形成 於配線基板1之背面的基準電位用外部端子4電氣連接。亦 即’金屬線7 C之電位被固定在基準電位上。 晶片侧輸出用電極6D,係介以輸出用金屬線7D與設置 成與半導體晶片5之另一邊5Y相對而形成於配線基板丨之一 主面上的基板側輸出用電極2D電氣連接。基板側輸出用電 極2 D,係於其正下方形成有貫穿孔配線3。 晶片側輸入用電極6 E,係介以輸入用金屬線7 e與設置成 與半導體晶片5之另一邊5 Y相對而形成於配線基板丨之一主 面上的基板側輸入用電極2E電氣連接。基板侧輸入用電極 2E,係介以貫穿孔配線3及内部配線,與基板側/輸出用電 極2 D電氣連接。 晶片側搭接用電極6 F,係介以金屬線7 F與設置成與半導 (請先閱讀背面之注意事項再r寫本頁) 裝 · -線. -19- 473382 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明() 體晶片5之一邊5 X相對而形成於配線基板i之一主面上的基 板側搭接用電極2F電氣連接。基板側搭接用電極2F,係介 以其正下方所形成的貫穿孔配線3及内部配線,與形成於 配線基板1之背面的基準電位用外部端子4電氣連接。亦 即,金屬绛7F之電位被固定在基準電位上。 晶片側輸出用電極6D和半導體晶片5之另一邊5¥的距 離,係短於晶片側輸入用電極6A和半導體晶片5之一邊5χ 的距離。又,晶片側輸出用電,極6Β和半導體晶片5之一邊 5 X的距離係短於晶片側輸入用電極6 Ε和半導體晶片5之另 一邊5 Υ的距離。此係用以縮短輸出用金屬線之長度,且降 低輸出電阻者。 在半導體晶片5之一主面的第一區域5八上,形成有與放 大裝置pwi之源極端子電氣連接的源極電極6S。此源極電 極6 S,係配置在比晶片側輸入用電極6 a還靠近半導體晶 片5之一邊5X側。又,在半導體晶片5之一主面的第二區域 5B上,形成有與放大裝置pW2之源極端子電氣連接的源椏 電極6S。該等的源極電極6S係在進行探針檢查時使用。 在本實施形態之高頻功率放大器中,輸入用金屬線7 A係 接近輸出用金屬線7B而配置。由於輸入用金屬線7A係電 氣連接至前級之放大裝置p w 1的閘極端子(輸入部)上,輸 出用金屬線7B係電氣連接至後級之放大裝置PW2的汲極端 子(輸出部)上,所以流至輸入用金屬線7 A的功率和流至輸 出用金屬線7 B的功率之差雖然很大,但是電位被固定在基 準電位的金屬線7C因係配置在輸入用金屬線7A和輸出用 -20- 本紙張尺度適用中國國家標準(CNS)A4規格(2】〇 x 297公釐) ---------------------訂--------- <請先閱讀背面之注意事項再本頁) 五 、發明說明( 18 A7 B7 經濟部智慧財產局員工消費合作社印製 至屬線7B之間,所以可防止因輸入用金屬線7八和輸出用 金屬線7B之間的互感作用所造成的高頻特性惡化。 又,輸出用金屬線7D係接近輸入用金屬線7E而配置。由 於輸出用金屬線7D係與前級放大裝置PW1之汲極端子(輸 出邵)電氣連接,輸入用金屬線7E係與後級放大裝置pw2 之閘極端子(輸入部)電氣連接,所以流至輸出用金屬線7D 之功率和流至輸入用金屬線7E之功率大致爲相同,因該金 屬線間之互感作用所造成的高頻特性惡化雖然很小,但是 電位被固定在基準電位的金屬線7F由於係配置在輸出用金 屬線7 D和輸入用金屬線7 E之間,所以可防止因輸出用金 屬線7D和輸入用金屬線7E之間的互感作用所造成的高頻 特性惡化。 基板側搭接用電極2 C,係配置在比基板側輸出用電極2 B ▲返难半導體晶片5之*邊5 X的位置上。基板側輸入用電 極2A,係配置在自半導體晶片5之一邊5χ起之距離大致與 基板側輸出用電極2 B相同的位置上。亦即,基板側搭接用 電極2 C,不配置在基板侧輸入用電極2 A和基板側輸出用 電極2 B之間,而配置在比基板側輸入用電極2 A及基板側 輸出用電極2B還遠離半導體晶片5之一邊5X的位置上。因 而,可縮小相當於基板側搭接用電極2 C之佔有面積的部 分,即縮小基板側輸入用電極2 A和基板側輸出用電極2 B 之間隔,且依此也可縮小半導體晶片5之第一區域5 A和第 二區域5 B之間隔,所以可縮小半導體晶片5之佔有面積。
基板側搭接用電極2 F,係配置在比基板侧輸出用電極2 D •21 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------裝---I----訂---------線 (請先閱讀背面之注音?事項再iri本頁) 473382 經濟部智慧財產局員工消費合作社印製 A7 B7 ^ 19 五、發明說明() ,遠離半導體晶片5之另一邊5 γ的位置上。基板側輸入用 笔極2£係配置在自半導體晶片5之另一邊5Y起之距離大 致與基板側輸出用電極2D相同的位置上。亦即,基板側搭 接用私極2 F ’不配置在基板側輸入用電極2 e和基板側輸出 用電極2D之間,而配置在比基板侧輸入用電極2E及基板 側輸出用電極2D還遠離半導體晶片5之另一邊5丫的位置 上。因而’可縮小相當於基板側搭接用電極2 F之佔有面積 的部分,即縮小基板側輸入用電極2E和基板侧輸出用電極 2D之間隔,且依此也可縮小半導體晶片5之第一區域$ a和 罘一區域5 B之間隔,所以可縮小半導體晶片5之佔有面 積。 如圖6所示,半導體晶片5,係形成以例如在單晶矽所構 成之p +型半導體基板1〇A之一主面上形成有卜型磊晶層 10B的半導體基體1〇爲主體的構成。 轉構成放大裝置PW1及PW2的場效電晶體,係形成於半導 月迁基1 0之一主面的電晶體形成區域上。此場效電晶體, 主要係由作爲通道形成區域之?型井區域12、閘極絕緣膜 14、閘極15、作爲源極區域及汲極區域之一對卜型半導體 區域16及一對n +型半導體區域17所構成。 在作爲汲極區域之n+型半導體區域17上,經由形成於層 間絕緣膜U之連接孔,而電氣連接形成於第一層之配線^ 上的配線19A。在作爲源極區域之n +型半導體區,域”上: 經由形成於層間絕緣膜18之連接孔,而電氣連接形成於第 一層之配線層的配線19B。配線19B,係經由形成於層間 -22- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 χ 297公釐) ---------------------^--------- (請先閱讀背面之注意事項再^^本頁) 473382
經濟部智慧財產局員工消費合作社印製 树膜18之連接孔,而電氣連接在形成於p_型蟲晶層^上 的P+型半導體區域13上。p +型半導體區域13係電氣連接 在P +型半導體基板10A上。在閉極15上,雖無詳細圖示, 但,經由形成於層間綠緣膜18之連接孔,而電氣連接形成 於第一層之配線層的配線1 9 c。 在配線19A上’係經由形成於層間絕緣膜2〇之連接孔, 而電氣連接形成於第二層之配線層的配線21人。在此配線 2 1 Ai -邵分中,形成有晶片側輸出用電極6d及晶片側輸 出用電極6B。在配線198±,係經由形成於層間絕緣膜2〇 (連接孔’而電氣連接形成於第二層之配線層的配線 21B。在此配線21B之一部分中,形成有探針檢查用的電 極。在配線19C上,雖未圖示,但是係經由形成於層間絕 緣膜20之連接孔’而電氣連接形成於第二層之配線層的配 線。在此配線之—部分中,形成有晶片側輸人用電極6A及 晶片側輸入用電極6 E。 在半導體晶片5之第三區域5C中,如圖7所示,在遮蔽絕 緣膜η上,形成有形成於第一層之配線層的配線19〇。此 配線19D,係朝與半導體晶片5之—邊5Xj£交的方向而延 伸者。在配線19D上,係,㈣形成於相絕緣膜2G之連接 孔,而形成有形成於第二層之配線層的配線21D。此配線 21D,係與配線19D同樣,朝與半導體晶片5之—邊5乂正 交的方向而延伸著。在此配線21D之—部分中形,成有晶片 側搭接用電極6 C及6 F。 在與半導體基體1〇之一主面相對的另—主面(背面)上形
本紙張尺度適用中國國家標準(CNS)A4規格(210 X 裝--------訂---------線 (請先閱讀背面之注意事項再V寫本頁) -23- 473SS, 經濟部智慧財產局員工消費合作社印製 A7 B7 21 --- 五、發明說明() 成有背面電極2 1。此背面電極21,係介有導電性之黏著材 料,而與形成於配線基板丨之凹部1A底面的導電板iB及電 氣及機械連接。亦即,放大裝置pwi、請2之各個的源極 端子之電位會固定在基準電位上。 在本實施形態之高頻功率放大器中,在半導體晶片5之第 區減5A和第二區域5B之間的第三區域(隔離區域)5(: 上,有黾位被固定在基準電位的配線丨9 D及配線2 1 D朝與 半導體晶片5之一邊5χ正交的方向而延伸著。又,在第三 區域5C上,有電位被固定在基準電位的p +型半導體區域 13朝與半導體晶片5之一邊5X正交的方向而延伸著,而且 半導體基體10之電位被固定在基準電位上。因而,在半導 月豆卵片5中由於係形成抑制磁束干擾的構成,所以高頻特 性不會惡化。 如此若依據本實施形態,則可獲得以下之效果。 (1)由於基板側搭接用電極2 c,係配置在比基板側輸入 用電極2A及基板側輸出用電極2B還遠離半導體晶片5之一 邊5 X的位置上,而基板側搭接用電極2 f,係配置在比基 板側輸入用電極2E及基板側輸出用電極2D還遠離半導體 晶片5之另一邊5 Y的位置上,所以可縮小相當於基板側搭 接用電極2 C之佔有面積的部分,即縮小基板側輸入用電極 2 A和基板侧輸出用電極2 B之間隔,且可縮小相當於基板 側搭接用電極2 F之佔有面積的部分,即縮小基板側輸入用 電極2 E和基板側輸出用電極2 D之間隔,所以可縮小半導 體晶片5之第一區域5A和第二區域5B之間隔。結果,由於 -24- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------^---------線 (請先閱讀背面之注意事項本頁) 經濟部智慧財產局員工消費合作社印製 473SS2 A7 B7 22-- 五、發明說明() 可縮小半導體晶片5之佔有面積,所以可謀求高頻功率放 大器之小型化。 (2 )由於基板側輸入用電極2 a,係配置於自丰導體晶片5 之一邊5 X起的距離大致與基板側輸出用電極2 b相同的位 置上,而基板側搭接用電極2(:,係配置在比基板侧輸入用 電極2A及基板側輸出用電極2B還遠離半導體晶片5之一邊 5X的位置上,而電位被固定在基準電位的金屬線7(:係橫 牙於基板側輸入用電極2 A和基板側輸出用電極2 b之間, 所以與在基板側輸入用電極2 a和基板側輸出用電極2 B之 間配置基板侧搭接用電極2 c之情況相較,就可更控制磁束 之干擾。 另外,在本實施形態中,雖係就配置電位被固定在基準 電位的金屬線7 C及金屬線7F的例子加以説明,但是由於流 至輸入用金屬線7E的功率和流至輸出用金屬線7D的功率 大致相同,所以亦可不必在連接於前級放大裝置p w丨之汲 極端子(輸出邵)的輸出用金屬線7 D和後級放大裝置P W 2之 閘極端子(輸入部)的輸入用金屬線7E之間,特別配置電位 固定在基準電位的金屬線。此情況,就可不需要晶片側搭 接用電極6 F及基板側搭接用電極2 F。 又’在本實施形態中,雖係就將基板側輸入用電極2 a配 置在自半導體晶片5之一邊5X起的距離大致與基板側輸出 用電極2 B相同的位置上,但是基板侧輸入用電極2 a亦可 配置在比基板側搭接用電極2C還遠離半導體晶片5之一邊 5X的位置上。在此情況中,雖亦可獲得與前述實施形態相 -25- 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) I-----------------線 (請先閱讀背面之注意事項再〆.¾本頁) 473382 A7 B7 經濟部智慧財產局員工消費合作社印製 23 五、發明說明() 同的效果,但是由於輸入用金屬線7A之長度會變長, 高頻特性會惡化若干。 實施形態2 圖8爲本發明之實施形態2之高頻功率放大器之配線基板 的主要部位平面圖。 本^施形態之高頻功率放大器,|本上係形《於前述實 施形態1相同的構成,而以下之構成則不同。 亦即,如圖8所7JT,在基板側搭接用電極2 c上電氣且機 械連接有延伸於半導體晶片5之第三區域5C上的金屬線7g 之一端側,而在基板側搭接用電極2F上電氣且機械連接有 金屬線7G之另一端側。基板側搭接用電極2C及基板側搭 接用電極2F由於係與基準電位用外部端子4電氣連接,所 以金屬線7G之電位可固定在基準電位上。 如此藉由在基板側搭接用電極2C上連接金屬線7G之一 端側,而在基板側搭接用電極2F上連接金屬線7G之另一 知側,就可防止因輸入用金屬線7A和輸出用金屬線7:6之 間的互感作用所造成的高頻特性惡化,及因輸出用金屬線 7D和輸入用金屬線7E之間的互感作用所造成的高頻特性 惡化。 實施形熊3 圖9爲本發明之實施形態3之高頻功率放大器之配線基板 的主要部位平面圖。 / 本實施形態之高頻功率放大器,基本上係形成與前述實 施形態1相同的構成,而以下之構成則不同。 -26- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) -------------裝--------訂·--------線 (請先閱讀背面之注咅?事項再·本頁) 473382 A7 B7 24 五、發明說明( 亦即,如圖9所示,放大裝置PW1、PW2及pW3係形成 於一個半導體晶片5上。P W 3係形成於半導體晶片5之一主 面的第四區域5D上。 放大裝置PW3之閘極端子(輸入部),係形成於半導體晶 片5之一主面的第四區域5D上,且與配置於半導體晶片5之 一邊-5 X侧(本實施形態中爲一長邊側)的晶片側輸入用電極 6H電氣連接。又,放大裝置PW3之汲極端子(輸出部),係 形成於半導體晶片5之一主面的第四區域上,且與配置 於與半導體晶片5之一邊5 X相對之另一邊5 γ側(本實施形 態中爲另一長邊側)的晶片側輸出用電極6κ電氣連接。 又’放大裝置P W 3之源極端子,係與放大裝置p w丨相同, 與形成於半導體晶片5之背面的背面電極2i電氣連接。 在半導體晶片5之一主面的第二區域5B和第四區域5 D之 間,形成有用以電氣隔離該等區域間的第五區域形成有用 以電氣隔離該等區域間的第五區域(隔離區域)5£。 晶片側輸入用電極6H,係介以輸入用金屬線7H與設置 成與半導體晶片5之一邊5 X相對而形成於配線基板i之一主 面的基板側輸入用電極211電氣連接。基板側輸入用電極 2 Η,係介以其正下方所形成的貫穿孔配線3及内部配線, 與基板側輸出用電極2 Β電氣連接。 晶片側輸入用電極6 κ,係介以輸出用金屬線7 Κ與設置 成與半導體晶片5之另一邊5 Υ相對而形成於配線·基板丨之_ 王面的基板側輸出用電極2Κ電氣連接。基板側輸出用電極 2 Κ ’係介以其正下方所形成的貫穿孔配線3及内部配線, •27- :297公釐) --------------裝--------訂---------線 (請先閱讀背面之注意事項再/¾本頁) 經濟部智慧財產局員工消費合作社印製 473882 經濟部智慧財產局員工消費合作社印製 Α7 Β7 25 ----- 五、發明說明() 與形成於配線基板丨之背面的輸出用外部端子電氣連接。 在配線基板1之-主面上,係在設置成與半導體晶片5之 一邊5X相對之下形成有基板側搭接用電極2j,而在設置成 與半導體晶片5之[邊5Y相對之下形成有基板側搭接用 電極2L。基板侧搭接用電極2;及2;1,係與基板側搭接用 私極2 C相同,與形成於配線基板丨之背面的基準電位用端 子4電氣連接。 基板側搭接用電極2J,係配·置於自半導體晶片5之一邊 5X起的距離大致與基板側搭接用電極2(:相同的位置上, 而基板側搭接用電極2L,係配置於自半導體晶片5之另一 邊5 Y起的距離大致與基板侧搭接用電極2f相同的位置 上0 在基板側搭接用電極2 J上,電氣且機械連接延伸於半導 體晶片5之第五區域5E上的金屬線7;1之一端側,而在基板 側搭接用電極2L上,電氣且機械連接延伸於半金屬線7L之 另一端側。 在本實施形態之高頻功率放大器中,配置在二條金屬線 7 L。流至輸入用金屬線7 £的功率和流至輸出用金屬線7 κ 的功率之差,係大於流至輸入用金屬線7八的功率和流至輸 出用金屬線7 Β的功率之差。因而,如本實施形態所示,藉 由按照功率差而增加電位固定在基準電位的金屬線之條 數,就可在更穩定之狀態下防止因輸入用金屬線和輸出用 金屬線之互感作用所造成的高頻特性惡化。 實施形態4 -28- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) --------^---------線 (請先閱讀背面之注意事項再妒寫本頁) A7 B7
473382 五、發明說明() 圖10爲本發明之實施形態4之高頻功率放大器之配線基 板的主要部位平面圖。 本實施形態之高頻功率放大器,基本上係形成與前述實 施形態1相同的構成,而以下之構成則不同。 、 亦即,如圖10所示,基板側輸出用電極2B係配置於與半 導體馮片5之一邊5X相對的位置上,而基板側輸入用電極 2A係配置於與半導體晶片5之一邊5χ爲不同的另一邊5?相 對的位置上。 如此藉由將基板側輸出用電極2 Β配置於與半導體晶片5 之邊5 X相對的位置上,而將基板側輸入用電極2 a配置 於與半導體晶片5之一邊5X爲不同的另一邊5p相對的位置 上,由於輸入用金屬線7A由於輸入用金屬線7八和輸出用 金屬線7 B之磁束呈爲正叉的狀態,所以可抑制該金屬線間 的互感作用。 又,由於沒有必要設置用以連接電位固定在基準電位之 金屬線的基板側搭接用電極,所以可縮窄半導體晶片5之 第一區域5 A和第二區域5 B的間隔,且可縮小半導體晶片5 之佔有面積。結果,可謀求高頻功率放大器之小型化。 實施形態5 r 如圖15所示,本發明之情況其耦合係數因比上述習知技 術之情況小,故可提高高頻特性。又,耦合係數爲〇12以 下(穩足係數爲1以上)之搭接部的間隔d範圍也更廣,故可 增大設計之自由度。再者,由於可將搭接部之間隔縮小至 0.3 mm,所以更可縮小晶片面積,更可使模組小型化及減 -29- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) » ϋ n n n n ϋ· m —i n I « ·ϋ n n ϋ n n I · n ϋ —>i n n n ·ϋ I (請先閱讀背面之注意事項再¥寫本頁) 經濟部智慧財產局員工消費合作社印制衣 47333 〇 經濟部智慧財產局員工消費合作社印製 A7 B7 27 ------- 五、發明說明() 低成本。 又,圖15雖顯示輸出入搭接金屬線所形成的角度必爲9〇 度的情況,但是如圖7所示,此角度0只要在72〜18〇度之 範^内即可。而且可知角度0爲14〇度時耦合係數就會變 成最小,且存在極小點。 在進行本發明之高頻功率放大器模組之具體的設計時, 可沿襲以上之方式,選擇搭接部間隔d和角度0。 再者,從以上之説明中即可明白,本發明不會將角度必 如習知般地設爲〇度乃爲其基礎。因而,亦可在角度0在 72〜180度之範圍内,且對應於輸出入搭接金屬線之二個放 大級電晶體的穩定係數成爲1以上的情形下設計高頻功率 放大器模組。 依圖1 1至圖1 4説明本發明之實施形態5之二級功率放大 器模組。 圖11爲主要邵位平面圖;圖12爲等效電路圖;圖13顯示 外觀構成的平面圖;圖1 4爲主要部位斜視圖。 如圖1 1所示,將由初級和第二級之MOSFET所構成的電 晶體102、103接近一個矽晶片1 〇 1上而形成之。該等電晶 體係在從初級電晶體102之閘極102a至汲極電極l〇2b之高 頻信號的流向、和從第二級電晶體103之閘極l〇3a至汲極 電極103b之高頻信號的流向成爲相反的方式下設置者。 作爲高頻輸入端子的閘極102a,係藉由一條輸入搭接金 屬線105,連接在配線基板113上之輸入匹配電路125的端 部121上。作爲高頻輸出端子的汲極電極l〇3b,係藉由四 -30- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) -------------裝--------訂---------線 (請先間讀背面之注意事項再束寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 28 五、發明說明() 條輸出搭接金屬線108,連接在配線基板113上之輸入匹配 電路127的端部124上。閘極i〇2a係沿著矽晶片ιοί之左側 的一邊而配置,汲極電極103b係沿著矽晶片】〇1之上側的 一邊而配置。輸入搭接金屬線105和輸出搭接金屬線1〇8所 成的角度係約設爲90度。搭接金屬線106、107,係將汲極 電極-102b、閘極l〇3a個別連接在配線基板113上之級間匹 配電路126的兩端邵122及123上。初級電晶體1〇2之閘極 l〇2a(搭接用輸入電極)和第二級電晶體1〇3之汲極電極 103b (搭接用輸出電極)之搭接部的間隔d係約設爲〇 6 mm ° 石夕晶片101係搭載在形成於配線基板113之鑄孔1〇4之 中。在矽晶片101之背面,係被覆金屬膜以作爲初級電晶 體102之源極電極及第二級電晶體1〇3之源極電極,並介以 麵孔104内的配·線連接在接地電位上。配線基板113之材 料’係使用玻璃陶瓷或鋁等的電介質基板。又,在其配線 上使用銅或銀、銀鉑等。 圖12及圖13中,符號Pin、Pout、Vgg、Vdd係分別爲高 頻化唬輸入端子、高頻信號輸出端子、閘極電壓施加端 子、汲極電壓施加端子,該等皆爲功率放大器模組之外部 連接端子。圖1 3中,以輔助線表示輸入匹配電路125、級 間匹配電路126及輸出匹配電路127之區域的境界。又,圖 1 4係顯示鑄孔104近旁的立體樣態。 — 在本實施形態中,雖係將輸入搭接金屬線1〇5和輸出搭接 金屬線108所成的角度設爲約9〇度,但是此角度係可在 -31 - 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) -------------裝--------訂---------線 (請先閱讀背面之注意事項再i'寫本頁) 473SS2 A7 B7 29 五、發明說明( 72〜180度之範圍内做選擇。 實施形態6 依圖1 8之主要部位平面圖説明本發明之實施形態6的三 級功率放大器模組。將由初級、第二級、輸出級之 MOSFET所構成的電晶體1〇2、103、114接近形成於一個矽 晶片-101上。該等電晶體係在從初級電晶體1〇2之閘極l〇2a 至汲極電極102b之高頻信號的流向、和從第二級電晶體 103之閘極l〇3a至汲極電極103b之高頻信號的流向成爲相 反的方式下設置者。又,輸出級電晶體Π4在從其閘極 114a至没極電極114b之高頻信號的流向成爲與第二級電晶 體103相反的方向之方式下配置者。 與實施形態5不同處係在於如下之點。即,初級電晶體 102之輸入搭接金屬線1〇5和第二級電晶體1〇3之輸出搭接 金屬線108所成的角度設爲約140度之點;以及將輸出級電 晶體114設在同一晶片上,將此電晶體之輸出搭接金屬線 110和第二級電晶體103之輸入搭接金屬線1〇7所成的角度 設爲約90度,將第二級電晶體103之閘極i〇3a(搭接用輸入 電極)和輸出級電晶體114之汲極電極114b(搭接用輸出電
極)之搭接部的間隔d設爲約0.7 mm,在此也適用本發明Z 點。 若依據本實施形態,則如圖17所示,可將初級和第二級 之輸出入搭接金屬線間的耦合係數設在最小,更可改呈隔 離效果。又,由於適用本發明,所以在第二級和輪出級輸 出入搭接金屬線間也可確保充分的隔離效果。因而,爲了 -32 本紙張尺度適財國國家標準(CNS)A4規格(210 X 297公爱 -------------^--------^---------線 (請先閱讀背面之注意事項再rk·本頁) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 社 印 製 經濟部智慧財產局員工消費合作社印製 Α7 Β7 30 --------- 立、發明說明() 縮小半導f豆卵片面積而在同一晶片上形成三級電晶體的本 只施形悲’且不拘該等電晶體間的距離是否變短,亦可改 善南頻特性。 重施形態7 依圖19之主要部位平面圖説明本發明之實施形態7的三 級功率放大器模組。與實施形態6不同處係在於,在第二 級電晶體103和輸出級電晶體114之間,應用遮蔽技術,設 置遮蔽用搭接金屬線201和遮蔽配線204 ,且將該等的兩端 介以配線基板上的電極202及連絡窗2〇3連接在接地電位之 點。 在本實施形態中,雖係在初級和第二級之間適用作爲習 知技術之遮蔽技術,但是因該等的電晶體區域原先面積很 廣,故可改善高頻特性。 實施形態8 依圖20之主要邵位平面圖説明本發明之實施形態$的二 級功率放大器模組。 與實施形態5之不同處係在於將初級電晶體丨〇2本身之方 向旋轉90度之點。 本實施形態’由於可將初級和第二級之輸出入搭接金屬 線之搭接邵的位置移動至晶片之邊的中央部,所以可更加 增寬搭接邵間隔(實施形態5中曾爲0·6 mm者乃變成爲〇 75 mm ),可更加改善輸出入間的隔離效果。 , 以上’雖疋以實施形態爲基礎而說明本發明,但是本發 明並不限定於上述實施形態,而是只要電晶體之電極數、 -33- 尺度適用中國國家標準(CNS)A4規格(21G X 297公爱:Γ --- ---------------------訂--------- (請先閱讀背面之注意事項再¥寫本頁) 47388,
發明說明( «接金屬線(條數等在未脱離其主旨之範圍内則皆可作各 種的變更。又’電晶體並不限於MOSFET亦可爲其他的場 效電晶體、異質接合雙载子電晶體(ΗΒΤ)等的電晶體。 --------------裝· (請先閱讀背面之注意事項再<寫本頁) 線 經濟部智慧財產局員工消費合作社印製 34- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)

Claims (1)

  1. 473382 經濟部中央標準局員工消費合作社印製 六 第88110698號專利申請案 Α8 中文申請專利範圍修正本(9〇年2月)§ 申請專利範圍 一種半導體裝置,其特徵為··具有, 半導體晶片’其平面係以方形狀所 二線於其一主面側搭載有前述半導體晶片; 弟一 “,料於前述半導體^之_主面的第—區 或上’且配置在可述半導體晶片之—邊側上; 放大裝置’形成於前述半導體晶片之一主面的第 '區域且其輸人部與前述第-電極電氣連接; 亟’形成於前述半導體晶片之一主面的第二區 或上,且配置在前述半導體晶片之一邊側上· 第二放大裝置,形成於前述半導體晶片之一主面的第 區域上,且其輸出部與前述第二電極電氣連接; 第三電極,形成於前述半導體晶片之一主面之第一區 域和第二區域之間的第三區域上; 第四電極’設置成與前述半導體晶片之一邊相對而形 成於前述配«板之-主面上,且介以第_金屬、線與前 述第一電極電氣連接; 第五電極,設置成與前述半導體晶片之一邊相對而形 成=前述配«板之-主面上,且介”二金屬線與前 述第二電極電氣連接;以及 第六電極,設置成與前述半導體晶片纟一邊相對而形 成於前述配線基板之-主面上,且介以其電位被固定在 基:電位的第三金屬線與前述第三電極電氣連接,並中 前述第六電極,係配置在比前述第五電極還遠離前述 半導體晶片之一邊的位置上。 本紙張尺度適用(CNS ) ( 210X297公$ ' --- _ϋ>— m^i ml ·1>11 ιϋ·ν m-il mu lil_l— I m ml —an·— mu m mi ^ J. -¾ (請先閲讀背面之注意事項再填寫本頁) 47338 A8 B8 C8 D8
    申請專利範圍 5. 2·如申請專利範圍第卜員之半導體裝置,纟中前述第四電 配置在自前述半導體晶片之一邊起之距離大致: W述第五電極相同的位置上,或是配置在比前述第六電 極還遠離前述半導體晶片之一邊的位置上。 ^私 3·如申請專利範圍第丨或2項之半導體裝置,其巾前述第二 ,大裝置之輸入部,係與前述第一放大裝置之輸出部電 氣連接。 % 4.如申清專利範圍第!或2嚷之半導體裝置,其中前述第四 電極,係與前述第五電極 -種半導體裝置,其特徵為=, 半導體晶片,其平面係以方形狀所形成; ,線基板’於其-主面側搭載有前述半導體晶片; 、第一電極,形成於前述半導體晶片之一主面的第一區 域上,且配置在前述半導體晶片之一邊側上; 第-放大裝置,形成於前述半導體晶片之一主面的第 -,域上,且其輸人部與前述第—電極電氣連接; 弟-電極’形成於前述半導體晶片之_^面的第二區 域上,且配置在前述半導體晶片之一邊側上; 第二放大裝置,形成於前述半導體晶片之一主面的第 一區域上,且其輸出部與前述第二電極電氣連接; 第亡電極,設置成與前述半導體晶片之一邊相對而形 =則輕«板之-主面上,且介以第―金屬線與前 述罘一電極電氣連接; 第四電極,設置成與前述半導體晶片之一邊相對而形 表紙張尺度適用中國國家標準(CNS )八4祕(21〇χ297^^ ----^------- 装------訂 (請先閲讀背面之注意事項再填寫本頁} 經濟部中央標準局員工消費合作社印製 473SS2 A8 B8
    且介以第二金屬線與爾 於兩述配線基板之_主面上 述第二電極電氣連接; 二五電極’形成於前述半導體晶片之—主面的第一层 側’且配f在與前述半導體晶片之—邊相對的另1 =與則述第-放大裝置之輸出部電氣連接; π電極’形成於前述半導體晶片之—主面的第q …且配置在前述半導體晶片之另—邊側上,而與另 处罘一放大裝置之輸入部電氣連接; W電極’設置成與前述半導體 形成於前述配線基板之一主面上邊相❼ 前述第五電《氣連接; 且介◎三金屬⑹ ^八電極’設置成與前述半導體晶片之另—邊相對Θ 2^前述配線基板之_主面上,且介以第四金屬線岁 :…電極電氣連接’更進一步與前述第七 連接; 第九電極’設置成與前述半導體晶片之—邊相對而汽 泛於則述配線基板主面上’並延伸於前述半導體g 之王面的第一區域和第二區域之間的第三區域上,j 連接有其電位被固定在基準電位的第五金屬線之4 側;以及 第十電極,設置成與前述半導體晶片之另一邊_ ^成於前㈣縣板之-主面上,且連接有前述第五4 屬線之另一端側,其中 前述第九電極’係配置在比前述第四電極還遠離前过 ,装 、1τ (請先閲讀背面之注意事項再填寫本頁) 經濟部中夬標準局員工消費合作社印製 -3 -
    47338 A8 B8 C8 D8 申清專利範圍 半導體晶片之一邊的位置上,而 两述第十電極,係配置在比前述第七電極及前述第八 兒極還遠離前述半導體晶片之另一邊的位置上。 6·如申晴專利範圍第5項之半導體裝置,其中前述第三電 極’係配置在自前述半導體晶片之一邊起之距離大致與 則逑第四電極相同的位置上,或是配置在比前述第九電 極還遠離前述半導體晶片之一邊的位置上,而 兒 峰:逑第七電極及前述第八電極,係配置在自前述半導 月立日日片之另一邊起之距離大致為相同的位置上。 7· 一種半導體裝置,其特徵為:具有, 半導體晶片,其平面係以方形狀所形成; =線基板’於其-主面側搭載有前述半導體晶片; 、第一電極,形成於前述半導體晶片之一主面的第一 域土,且配置在前述半導體晶片之一邊側上,· 抑 罘一放大裝置,形成於前述半導體晶片之一主 '區域上,且其輸入部與前述第一電極電氣連接;、 電極’形成於前述半導體晶片之_主 域土:且配置在前述半導體晶片之—邊倒上; S 放大裝置,形成於前述半導體晶片之 二區域上,且其輸出部與前述第二電 面的矛 弟三電極,形成於前述配線基 ,連接, 第一金屬線與前述第一電極電氣連接.i丨,且介以 第四電極’設置成與前述半.導 成於前述配線基板之一幸 ^阳片又一達相對而形 且介以第二金屬線與前 國國家m (cm I I 1 - I - -1 j i -- = :1 ; - - il f J衣 - - I 1-i - - - - I —! --、l"^ (請先閎讀背面之注意事項再填寫本頁) 經 濟 中 央 標 準 Ά ^73382 A8 B8 C8 D8 申請專利範圍 述第二電極電氣連接;其中 請 I 先I 閲 I 讀 背I 面 | 之1 I j 事I 項 I 再! 填 頁I 雨述第四電極,係配置與前述半導體晶片之-邊相對 的位置上,而 ? 月)述第一包極,係配置在與前述半導體晶片之一邊為 不同之另一邊相對的位置上。 8.如-申請專利範圍第7項之半導體裝置,其中前述第二放 ^裝置之輸人部,係與前述第-放大裝置之輸出部電氣 連接。 9·如申請專:範圍第!項之半導體裝置,其中前述第一放 大裝置及罘二放大裝置,係形成電氣並聯連接複數個場 效電晶體之各個的構成。 訂 10·:種高頻功率放大器模組,係具有將電介質材料作為基 月豆之配線基板;以;^@ 士二、 p又置在该配線基板上的半導體晶 片,其特徵為: 在上述半導體晶片卜,泌+ 士 口片上形成有二級以上的放大級電晶 體;對該放大級電晶體輸入高頻功率用的搭接用輸入電 極,以及從該放大級電晶體以輸出高頻功率用的搭接用 輸出電極’而將第一輔助線和第二輔助線所成的角度設 經濟部中央標準局員工消費合作社印製 在72〜180度之範圍内,且將前述搭接用輸入電極和前述 搭接用輸入電極之搭接部的間隔設在0.3 mm以上〇.8mm 以下之範圍内,其中前述第一辅助線係用以連結輸入柊 接金屬線之兩端的搭接部彼此之間,而前述輸人搭接金 屬線個以連接對應於—個前.述放大級電晶體之前述搭 接用輸入電極和前述配線基板者,又,前述第二輔助線 i紙張尺度適用中國國家標準(CNS)八4祕
    六、申請專利範圍 濟 部 中 係用以連結輸出搭接金屬線之兩端的搭接部彼此之間, 而前述輸出搭接金屬線係用以連接對應於位在該一放大 級電晶體之次級的前述放大級電晶體之前述搭接用輸出 電極和前述配線基板者。 11. 一種高頻功率放大器模組,係具有將電介質材料作為基 體之配線基板;以及設置在該配線基板上的半導體= 片,其特徵為: W 在上述半導體晶片上,形成有二級以上的放大級電晶 體,對Μ放大級電晶體輸入高頻功率用的搭接用輸入電 極;以及從該放大級電晶體讀出高頻功率用白勺搭接2 輸出電極,而將第一輔助線和第二輔助線所成的角度設 在72〜180度之範圍内,且前述一個放大級電晶體及前述 次級放大級電晶體之穩定係數為丨以上,其中前述第一 輔助線係:以連結輸入搭接金屬線之兩端的搭接部彼此 之間,而前述輸人搭接金屬線係用以連接對應於一個前 述放大級U體之前述搭接用輸人電極和前述配線基板 者,又,前述第二輔助、㈣用以連結輸出搭接金屬線之 兩端的搭接部彼此之間,而前述輸出搭接金屬線係用以 連接對應f位在该_放大級電晶體之次級的前述放犬級 電晶體之前述搭接用輸出電極和前述配線基板者。 12·如申請專利㈣第1項之高頻功率放大器模組,並 ^述第一輔助線和前述第二辅助線所成的角,度係约為 13·如中請專利範圍第12項之高頻功率放大ϋ模組,其中前 |______ - 6 %紙張尺度適用中國國家標隼( 袈-- (請先閲讀背面之注意事項再填寫本頁) I— II . • i I If · .1- I m • I....... —II* 47333 ABCD
    經濟部中央榡準局員工消費合作社印製 述半導體晶片為四邊形,其在前述半導體晶片之第一邊 側上,配置其連接有對應於前述次級放大級電晶體之複 數么1·、別述輸出搭接金屬線的前述搭接用輸出電極,而在 與岫述半導體晶片之前述第一邊相對的第二邊側上,配 置有對應於前述次級放大級電晶體之搭接用輸入電極及 對—應於前述一個放大級電晶體之搭接用輸出電極,在前 述半導體晶片之前述第一、第二邊以外之第三邊側上, 配置其連接有對應於前述一個放大級電晶體之一條前述 輸入搭接金屬線的前述搭接用輸入電極。 14·如申請專利範圍第13項之高頻功率放大器模組,其中前 述放大級電晶體之級數有三級,其中前述一個放大級電 晶體為初級放大級電晶體,前述次級放大級電晶體為^ 、’及放大級%印體’其第三輔助線和第四輔助線所成的 角度係設在72〜180度之範圍内,而前述第三辅助線係用 以連結輸入搭接金屬線之兩端的搭接部彼此之間,而前 述輸入搭接金屬線係用以連接對應於前述第二級放大2 包印體之搭接用輸入電極和前述配線基板者,又,前述 第四輔助線係用以連結輸出搭接金屬線之兩端的搭= 彼此之間,而前述輸出搭接金屬線❹以連接對應於前 述第三級放大級電晶體之搭接用輸出電極和前述配線基 板者。 土 15.如^請專利範圍第14項之高頻功率放大器模組,其中前 述第三輔助線和前述第四輔助線所成的角度係約、為^ (請先閲讀背面之注意事項再填寫本頁) 裝 、1T
    裝-- (請先閲讀背面之注意事項再填寫本頁) 16·如申請專利範圍第i 5項之高頻功率放大器模組,其中第 三輔助線和第四輔助線所成的角度係約為〇度,前述第 二輔助線係用以連結輸入搭接金屬線之兩端的搭接部彼 此之間,而前述輸入搭接金屬線係用以連接對應於前述 第二級放大級電晶體之搭接用輸入電極和前述配線基板 者’又,前述第四輔助線係用以連結輸出搭接金屬線之 兩端的搭接邵彼此之間,而前述輸出搭接金屬線係用以 連接對應於前述第三級放大級電晶體之搭接用輸出電極 和前述配線基板者,而在前述第三辅助線和前述第四輔 助線之間設有遮蔽用搭接金屬線,而該遮蔽用搭接金屬 線之兩端係高頻接地。 經濟部中夬標隼局員工消費合作社印製 17.如申請專利範圍第1 6項之高頻功率放大器模組,其中前 述配線基板具有:具有四個邊的錡孔;形成於該鎮孔之 第一邊側的第一匹配電路:形成於與前述鑄孔之第一邊 相對之第二邊側的第二匹配電路:以及形成於前述鏵孔 之前述第一、第二邊以外之第三邊側的第三匹配電路, 而前述第一匹配電路係與前述次級放大級電晶體之輸出 搭接金屬線電氣連接,前述第二匹配電路係電氣連接於 觔述一個放大級電晶體之輸出側和前述次級放大器電晶 體之輸入側之間’前述第三匹配電路,係與前述一個放 大級電晶體之輸入搭接金屬線電氣連接。 18· —種半導體裝置,其特徵為:具有, , 具有一主面之基板; 四角形之半導體晶片,裝載於前述基板之一主面上, 8- 4 0C S S 3 ABCD 經濟部中央標隼局員工消費合作社印製 六、申請專利範圍 且具有延伸於第一方向之一組第一邊,及延伸於約略與 前述第一方向正交之第二方向之一組第二邊; 第一電極,形成於前述半導體晶片主面之第一區域 上,且配置在沿著前述半導體晶片一組第一邊之一者; 第一放大裝置,形成於前述半導體晶片主面之第一區 域上,且其輸入部與前述第一電極電氣連接; 第二電極,形成於與前述第一區域不同之前述半導體 晶片主面之弟二區域上’且配置在沿奢前述半導體晶片 一組第一邊之一者; 第二放大裝置’形成於前述半導體晶片主面之弟二區 域上,且其輸出部與前述第二電極電氣連接; 第三電極,形成於前述第一區域與前述第二區域間之 前述半導體晶片主面之第三區域上,且配置在沿著前述 半導體晶片一組第一邊之一者; 第四電極,設置成與前述半導體晶片一組之第一邊相 對而形成於前述基板之一主面上,且介以第一金屬線而 與前述第一電極電氣連接; 第五電極,設置成與前述半導體晶片一組之第一邊相 對而形成於前述基板之一主面上,且介以第二金屬線而 與前述第二電極電氣連接;以及 第六電極,設置成與前述半導體晶片一組之第一邊相 對而形成於前述基板之一主面上,且介以第三金屬線與 前述第三電極電氣連接; 前述第三電極、前述第六電極以及前述第三金屬線, -9- ml tm ·1111 1_111 ml flm Ham am— I im_l (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 473382 ABCD 經濟部中央標隼局員工消費合作社印製 夂、申請專利範圍 係被固定於基準電位; 蓟述第二金屬線,於前述之第一方向,被配置於前述 第一金屬線與第二金屬線之間; 前述第一金屬線、前述第二金屬線以及前述第三金屬 線’係沿著前述第二方向而彼此約略平行地延伸。 19.如申請專利範圍第丨8項之半導體裝置,其中前述第一放 大裝置以及第二放大裝置,係形成於前述半導體晶片上 第區域及第二區域之第一場效電晶體及第二場效電晶 體。 2〇.如申請專利範圍第1 9項之半導體裝置,其中前述第一放 大裝置之輸入部,對應於前述第一場效電晶體之閘極, 前述第二場效電晶體之輸出部,對應於前述第二場效電 晶體之沒極。 21·如申請專利範圍第2 〇項之半導體裝置,其中前述第六電 極’被配置於較之前述第四電極及第五電極,離前述半 導體晶片一組第一邊之一者為遠之位置。 22· —種半導體裝置,其特徵為:具有, 具有一主面之基板; 四角形之半導體晶片,裝載於前述基板之一主面上, 且具有延伸於第一方向之一組第一邊,及延伸於約略與 月述第一方向正交之第二方向之一組第二邊; 形成於前述半導體晶片主面上之場效電晶體勺 第一電極,形成於前述半導體晶片之主面上,沿著前 述半導體晶片一組之第一邊之一者而配置,被用作為前 -10 - 本紙張尺度· 標準(CNS ) (—210X297公爱) ^------1T (請先閲讀背面之注意事項再填寫本頁) 473382
    申請專利範圍 形 經濟部中央標準局貞工消費合作社印製 述場效電晶體之輪入部; J;f:t片形f於!述半導體晶片之主面上,沿著前 、千竽把日日片一組又第一邊之另一 前述場效電晶體之輸出部; _ ^用作為 第二電極,與前述半導體曰 般'地被配置於前述基板之-主面之::相對 與前述第-電極電氣連接; …-金屬線而 第四電極,與前述半導體晶片組 對般地被配置於前述基板之_主面上\=另-者相 而與前述第二電極電氣連接; a “―金屬線 :述:二方向中之前述第二電極與前述一者組 二:間之距離’較之前述第二方向中之前述第一 组第-邊之-者間之距離為小; 成前述第二金屬線’較之前㈣—金屬線為短般地 23·Γ申料#咖第22項之半導體裝置,其巾前述第一 極係對應於前述第一場效電晶體之閘極,前述第二备 係對應於前述場效電晶體之汲極。 % 24. 如申請專利範圍第23項之半㈣裝置,其+前 向中前j第三電極與前述—組第一邊之—者間之距^ 大致與Μ 4第二纟肖中前述第冑冑極與前述_組第一 之另一者間之距離相同。 25. 如申請專利範圍第22項之半導體裝置,其中前述第二 屬線,較前述第一金屬線為短般地形成以減低 極 万 邊 二金 電 -11 - 冗張尺度適财關) Α4— ( 210X29^7 473332 A8 B8 .C8 D8 申請專利範圍 阻 (請先閎讀背面之注意事項再填寫本頁) 衮· 訂 經濟部中央標隼局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐)
TW088110698A 1998-07-06 1999-06-25 Semiconductor device TW473882B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP19080998A JP3946874B2 (ja) 1998-07-06 1998-07-06 半導体装置
JP04104599A JP3667136B2 (ja) 1999-02-19 1999-02-19 高周波電力増幅器モジュール

Publications (1)

Publication Number Publication Date
TW473882B true TW473882B (en) 2002-01-21

Family

ID=26380568

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088110698A TW473882B (en) 1998-07-06 1999-06-25 Semiconductor device

Country Status (4)

Country Link
US (5) US6330165B1 (zh)
EP (2) EP1770777A3 (zh)
DE (1) DE69935182T2 (zh)
TW (1) TW473882B (zh)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100441287B1 (ko) * 1999-03-24 2004-07-21 롬 가부시키가이샤 충전전지의 보호회로 모듈 및 그 제조방법
US6463267B1 (en) 1999-04-21 2002-10-08 Hitachi, Ltd. High frequency power amplifying apparatus having amplifying stages with gain control signals of lower amplitudes applied to earlier preceding stages
EP1168604A4 (en) * 2000-02-08 2005-07-06 Mitsubishi Electric Corp MULTI-STAGE AMPLIFIER
JP2001308265A (ja) * 2000-04-21 2001-11-02 Toyota Industries Corp 半導体装置
TW483233B (en) * 2000-05-30 2002-04-11 Alps Electric Co Ltd Electronic circuit unit
US6856006B2 (en) * 2002-03-28 2005-02-15 Siliconix Taiwan Ltd Encapsulation method and leadframe for leadless semiconductor packages
JP4530494B2 (ja) * 2000-06-30 2010-08-25 三菱電機株式会社 高周波用複合素子
JP2002111415A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 高周波電力増幅装置及び無線通信機
TW575949B (en) * 2001-02-06 2004-02-11 Hitachi Ltd Mixed integrated circuit device, its manufacturing method and electronic apparatus
TW546819B (en) * 2001-05-30 2003-08-11 Sharp Kk Semiconductor device, manufacturing method thereof, and monolithic microwave integrated circuit
KR100404904B1 (ko) * 2001-06-09 2003-11-07 전자부품연구원 차동 용량형 압력센서 및 그 제조방법
TW594888B (en) 2001-09-05 2004-06-21 Hitachi Ltd Semiconductor device and manufacturing method thereof and wireless communication device
JP4066644B2 (ja) * 2001-11-26 2008-03-26 株式会社豊田自動織機 半導体装置、半導体装置の配線方法
CN100352317C (zh) * 2002-06-07 2007-11-28 松下电器产业株式会社 电子元件安装板、电子元件模块、制造电子元件安装板的方法及通信设备
TW200518345A (en) * 2003-08-08 2005-06-01 Renesas Tech Corp Semiconductor device
US20050134410A1 (en) * 2003-12-18 2005-06-23 Intel Corporation Power addition apparatus, systems, and methods
US7215204B2 (en) * 2004-12-29 2007-05-08 Agere Systems Inc. Intelligent high-power amplifier module
US7433192B2 (en) * 2004-12-29 2008-10-07 Agere Systems Inc. Packaging for electronic modules
DE112006001414A5 (de) 2005-05-30 2008-03-06 Osram Opto Semiconductors Gmbh Gehäusekörper und Verfahren zu dessen Herstellung
US9093359B2 (en) * 2005-07-01 2015-07-28 Vishay-Siliconix Complete power management system implemented in a single surface mount package
CN101292349B (zh) * 2005-10-19 2011-09-28 Nxp股份有限公司 包括具有与接线耦接的电极的元件的器件
US7719112B2 (en) * 2006-08-07 2010-05-18 University Of Central Florida Research Foundation, Inc. On-chip magnetic components
JP4777295B2 (ja) * 2007-04-27 2011-09-21 株式会社豊田中央研究所 半導体チップ実装基板
US9545009B2 (en) * 2007-05-23 2017-01-10 Spectra Logic, Corporation Passive alterable electrical component
US8035994B2 (en) * 2008-05-12 2011-10-11 Mitsubishi Electric Corporation High frequency storing case and high frequency module
US9123663B2 (en) * 2008-06-10 2015-09-01 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer grounded through metal pillars formed in peripheral region of the semiconductor
EP3598484B1 (en) * 2008-09-05 2021-05-05 Mitsubishi Electric Corporation High-frequency circuit package and sensor module
JP5586866B2 (ja) * 2008-09-29 2014-09-10 株式会社日立産機システム 電力変換装置
KR100950511B1 (ko) 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
KR100935854B1 (ko) * 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
JP5631607B2 (ja) * 2009-08-21 2014-11-26 株式会社東芝 マルチチップモジュール構造を有する高周波回路
CN102666320B (zh) 2009-12-16 2015-04-15 鲍勃斯脱梅克斯股份有限公司 定位在切割装置下游的用于将预切基片分离的装置
MY163694A (en) 2010-06-02 2017-10-13 Semiconductor Components Ind Llc Semiconductor component and method of manufacture
US9252767B1 (en) * 2010-06-28 2016-02-02 Hittite Microwave Corporation Integrated switch module
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US9059191B2 (en) * 2011-10-19 2015-06-16 International Business Machines Corporation Chamfered corner crackstop for an integrated circuit chip
US9035702B2 (en) * 2012-03-08 2015-05-19 Kabushiki Kaisha Toshiba Microwave semiconductor amplifier
US9419580B2 (en) * 2014-10-31 2016-08-16 Raytheon Company Output matching network having a single combined series and shunt capacitor component
USD773394S1 (en) * 2015-05-07 2016-12-06 General Electric Company Enclosure for electronic device
DE102015221688A1 (de) * 2015-11-05 2017-05-11 Osram Gmbh Verfahren zur Reduzierung von Leiterbahnabständen bei elektronischen Leiterplatten und elektronische Leiterplatte mit reduzierten Abständen zwischen Leiterbahnen
JP6273247B2 (ja) * 2015-12-03 2018-01-31 株式会社東芝 高周波半導体増幅器
JP1563812S (zh) * 2016-04-11 2016-11-21
US20170338179A1 (en) * 2016-05-20 2017-11-23 Qualcomm Incorporated Device package with wire bond assisted grounding and inductors
JP1577511S (zh) * 2016-11-15 2017-05-29
JP1580899S (zh) * 2016-11-15 2017-07-10
US10069462B1 (en) * 2017-02-27 2018-09-04 Nxp Usa, Inc. Multiple-stage RF amplifier devices
JP1592769S (zh) * 2017-05-02 2017-12-11
WO2019138760A1 (ja) * 2018-01-09 2019-07-18 株式会社村田製作所 高周波モジュール
JP1660133S (zh) * 2019-09-26 2020-05-25
JP1741186S (ja) * 2022-11-01 2023-04-06 半導体素子
JP1741185S (ja) * 2022-11-01 2023-04-06 半導体素子

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4410874A (en) * 1975-03-03 1983-10-18 Hughes Aircraft Company Large area hybrid microcircuit assembly
US4193083A (en) * 1977-01-07 1980-03-11 Varian Associates, Inc. Package for push-pull semiconductor devices
US4193093A (en) * 1978-08-03 1980-03-11 The United States Of America As Represented By The Secretary Of The Navy CCD camera interface circuit
JPS5681962A (en) * 1979-12-06 1981-07-04 Fujitsu Ltd Preventing of crosstalk in semiconductor integrated circuit
JPS59195856A (ja) * 1983-04-20 1984-11-07 Fujitsu Ltd 半導体装置及びその製造方法
JPS6077436A (ja) * 1983-10-04 1985-05-02 Nec Corp 半導体集積回路
JPS62109351A (ja) 1985-11-07 1987-05-20 Mitsubishi Electric Corp 半導体装置
JPH01243441A (ja) 1988-03-25 1989-09-28 Hitachi Ltd 半導体装置及びその製造方法
US5144535A (en) * 1989-04-20 1992-09-01 U.S. Philips Corporation Method of mounting electrical and/or electronic components of a printed circuit board
JP2901091B2 (ja) * 1990-09-27 1999-06-02 株式会社日立製作所 半導体装置
JPH04221837A (ja) 1990-12-21 1992-08-12 Mitsubishi Electric Corp 半導体装置
US5768109A (en) * 1991-06-26 1998-06-16 Hughes Electronics Multi-layer circuit board and semiconductor flip chip connection
JP3123616B2 (ja) * 1991-10-09 2001-01-15 キヤノン株式会社 液晶表示装置の実装方法
JPH0685154A (ja) * 1992-09-07 1994-03-25 Hitachi Ltd 半導体集積回路装置
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
KR0156334B1 (ko) 1995-10-14 1998-10-15 김광호 차폐 본딩 와이어를 구비하는 고주파, 고밀도용 반도체 칩 패키지
US6049126A (en) * 1995-12-14 2000-04-11 Nec Corporation Semiconductor package and amplifier employing the same
JP3476612B2 (ja) * 1995-12-21 2003-12-10 三菱電機株式会社 半導体装置
JP2755250B2 (ja) 1996-03-22 1998-05-20 日本電気株式会社 半導体集積回路
JPH1032680A (ja) 1996-07-15 1998-02-03 Canon Inc 画像読取装置及び蛍光ランプ
JP3796016B2 (ja) 1997-03-28 2006-07-12 三洋電機株式会社 半導体装置
US6166436A (en) * 1997-04-16 2000-12-26 Matsushita Electric Industrial Co., Ltd. High frequency semiconductor device
JP3472455B2 (ja) * 1997-09-12 2003-12-02 沖電気工業株式会社 半導体集積回路装置及びそのパッケージ構造
JPH11234053A (ja) * 1998-02-12 1999-08-27 Nec Corp デバイス負荷変動保護回路
US6377464B1 (en) * 1999-01-29 2002-04-23 Conexant Systems, Inc. Multiple chip module with integrated RF capabilities
JP3932259B2 (ja) * 2001-12-12 2007-06-20 株式会社ルネサステクノロジ 高周波電力増幅回路および無線通信用電子部品
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール

Also Published As

Publication number Publication date
EP0971411A3 (en) 2000-09-06
EP0971411A2 (en) 2000-01-12
US20050269590A1 (en) 2005-12-08
US6943441B2 (en) 2005-09-13
US20070001300A1 (en) 2007-01-04
DE69935182D1 (de) 2007-04-05
EP1770777A3 (en) 2009-01-21
US6330165B1 (en) 2001-12-11
US6489680B2 (en) 2002-12-03
US20030102574A1 (en) 2003-06-05
US20020015291A1 (en) 2002-02-07
EP0971411B1 (en) 2007-02-21
DE69935182T2 (de) 2008-01-03
US7068521B2 (en) 2006-06-27
EP1770777A2 (en) 2007-04-04

Similar Documents

Publication Publication Date Title
TW473882B (en) Semiconductor device
US7817437B2 (en) Semiconductor device
US7061329B2 (en) Semiconductor device having balanced circuit for use in high frequency band
US7176774B2 (en) Differential mode inductor with a center tap
CN111048487A (zh) 具有双朝向非圆形通孔连接件的晶体管
CN107005204B (zh) 具有单一组合的串联和并联电容器组件的输出匹配网络
EP1840913A1 (en) Capacitor and electronic circuit
JP4260456B2 (ja) システム
JP2000021926A (ja) 半導体装置
Estreich A monolithic wide-band GaAs IC amplifier
Chan et al. A low-distortion monolithic wide-band amplifier
JPH08116028A (ja) マイクロストリップ線路、スパイラルインダクタ、マイクロ波増幅回路及びマイクロ波増幅装置
JP5357907B2 (ja) システム
US6355972B1 (en) Semiconductor device and method of manufacturing same
JP3667136B2 (ja) 高周波電力増幅器モジュール
GB2230396A (en) FET element with feedback
JP4918652B2 (ja) 半導体装置
JP4153898B2 (ja) 高周波電力増幅器モジュール
KR100562349B1 (ko) 반도체장치
JP2008228347A (ja) 高周波電力増幅器モジュール
JP2007074000A (ja) 半導体装置
JPH11204728A (ja) 高周波半導体装置
JP2007074001A (ja) 半導体装置
JPS61263146A (ja) 半導体装置
JPH0766222A (ja) 電界効果トランジスタ

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent