JPS6077436A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS6077436A
JPS6077436A JP58185416A JP18541683A JPS6077436A JP S6077436 A JPS6077436 A JP S6077436A JP 58185416 A JP58185416 A JP 58185416A JP 18541683 A JP18541683 A JP 18541683A JP S6077436 A JPS6077436 A JP S6077436A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
island
integrated circuit
crosstalk
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58185416A
Other languages
English (en)
Inventor
Koichi Tanaka
康一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58185416A priority Critical patent/JPS6077436A/ja
Publication of JPS6077436A publication Critical patent/JPS6077436A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は、特にモノリシックチップ上の回路ブロック間
の相互干渉の少ない半導体集積回路の組立構造′に四す
る。
第１図は、１８ピンデユアルインパツケージにＡ１−Ａ
４の４個の増幅器を内蔵した半導体集積回路の模式図で
ある。それぞれの増幅器Ａ１〜Ａ４して出力端より構成
されＣいる。第１図では、各増幅器の相互干渉（クロス
トーク）會なくすため接地端子は独立に３．　７．　１
２．　１６ピンに設けられている。
しかしながら半導体集積回路が多機能化してくると、ピ
ン数の制約から接地端子に４ピンも使用することができ
ず、接地端子を共通にしなければならない。
半導体集積回路では、配線としてはアルミニウムが一般
に使用されアルミニウムの厚さが１．５μｍのときアル
ミニウムの層抵抗は約２５ｍΩ／口になる。従って、モ
ノリシックチップ上で２個の増幅器の接地配線を共通に
して幅Ｗ＝２０μで長さＬ＝ｌ暉布締布線ときの共、■
インピーダンスＲ＋は式＋１）で示される。
第２図はクロースドータを示す図である。Ａ２゜Ａ４は
増幅器、ｌ、５は入力端子、３．７はそれぞれＡ２．Ａ
４の接地端子、Ｒ＋は共通インピー源を示す。接地電流
１２＋”４は共通インピーダンスＲｔに流れ込むため、
増幅器Ａ２０入力信号は式（２）に示される８１′に、
増幅器Ａ４の入力信号は式（３）に示されるＳｚ’にそ
れぞれ変化し、クロストークを生じる。
Ｓ　１’　＝Ｓ　ｔ　−４−ｉ　４几ｌ　・・・（２）
８ｚ’＝Ｓｚ−１−ｉ２Ｒｔ　・・・（３）例えば、増
幅器Ａ２．Ａ４の増幅度を４０ｄＢ（１００倍）？’２
＋’４を１ｍＡ、増幅器の出力電圧３■、すなわちＳ　
ｒ　＝　Ｓ　ｚ　＝−’−Ｍ−＝　３０　ｍＶ００ のとき、クロストークを４ｏｄＢ以上の減衰率を得るた
めには式（４）を満足しなければならない。
ＩＱＱ　ｘ　ｉ　１　・　■も　１（Ｓ　１ｉ００　ｘ
　ｉ　２・Ｒ１（Ｓ　２ ・°・　Ｒ１（０，３０・・・（４） すなわち共通インピータンスは０．３Ω以下でなければ
ならない。
このような低い共通布線インピーダンスを得るために従
来の半導体集積回路は第３図に示す構造をとっていた。
２１はモノリシックチップ２２を搭載するためのアイラ
ンド、２３〜２７はボンディングをする為のパッド、２
８．２９は３４〜３６のリードに電気的に接続するため
の金属ワイヤ、３０．３１は最低電位のアルミニウム配
線。
３２は最高電位のアルミニウム配線を示す。このように
、従来構造では、共通インピータンスを小さくするため
に最低電位のアルミニウム配＃ｊ！３０゜３１に図示し
たようにパッド２３．２７の外側を独立に布線し、更に
独立のパッド２５．２６から共通リード３４に金属ワイ
ヤ２８．２９で接続していた。この様な方法では最低電
位のアルミニウム配線３０．３１の引きまわしによりチ
ップサイズが大きくなってコスト高となりまた、クロス
トークはなくなるが配線３０．３１の布線抵抗が大きい
ため自分の信号・電流により出力が形骨をうけるという
欠点があった。更には、増幅器が４個以上になると、マ
スクパターンレイアウトが不可能になった。
本発明は係る不具合を解決するためになされたものであ
り、その実施例を第４図に示す、第３図と同一番号が付
されているものは同一名称である。
本発明ではＡ　Ｉ　−Ａ　４の増幅器の独立の接地電位
パッド５０〜５３よりアイランド２１に金属ワイヤ４０
〜４３でそれぞれ接続しており、更にアイランド２１と
リード３４を金属ワイヤ４４で接続している。アイラン
ド２１の共通インピーダンスは１ＱｙｉΩ以下なので無
視できる。従って、共通インピーダンスは金属ワイヤ４
４とリード３４の抵抗和となり０．３Ω以下を容易に実
現できる。ワイヤ４４を複数ボンディングで接続すれば
更にクロストーク特性を向上させることができる。第４
図の実施例ではリード３４を最低電位としたが、本発明
では第４図から明らかなように任意のリードを最低・電
位にすることができる。
以上述べてきたように本発明に係る半導体集積回路では
チップサイズを大きくすることなしにクロストークを減
少することができるので多機能化されたＩＣに非常に適
する。
第１図は４個の増幅器を内蔵した従来の半導体集積回路
の模式図、化２図はクロストークを説明するための図、
第３図は従来の半導体集積回路の模式平面図、第４図は
本発明に係る半導体集積回路の一実施例を示す平面図で
ある。
Ａｌ−Ａ４・・・・・・増幅器、１〜１８・・・・・・
ピン。
２２・・・・・・チップ、２１・・・・・・アイランド
、２３．　２６゜５０〜５１・・・・・・接地電位パッ
ド、２４・・・・・・ＶＣＣパッド、３０．　３１．　
３２−・・・・・アルミニウム配線、３４〜３６・・・
・・・リード。

Claims (1)

    【特許請求の範囲】
  1. モノリシック半導体チップ上の複数個の同電位パッドを
    前記モノリシック半導体チップが搭載されているアイラ
    ンドに金属ワイヤで接続し、該アイランドを１本以上の
    リードに他の金属ワイヤで接続したことを特徴とする半
    導体集積回路。
JP58185416A 1983-10-04 1983-10-04 半導体集積回路 Pending JPS6077436A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58185416A JPS6077436A (ja) 1983-10-04 1983-10-04 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58185416A JPS6077436A (ja) 1983-10-04 1983-10-04 半導体集積回路

Publications (1)

Publication Number Publication Date
JPS6077436A true JPS6077436A (ja) 1985-05-02

Family

ID=16170402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58185416A Pending JPS6077436A (ja) 1983-10-04 1983-10-04 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS6077436A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225445A (ja) * 1985-07-25 1987-02-03 Toshiba Corp 半導体集積回路装置
JPS62283636A (ja) * 1986-06-02 1987-12-09 Matsushita Electronics Corp 半導体集積回路装置
JPS6362336A (ja) * 1986-09-03 1988-03-18 Nec Corp 半導体集積回路装置
JPS6355539U (ja) * 1986-09-30 1988-04-14
JPS63246832A (ja) * 1987-04-02 1988-10-13 Matsushita Electronics Corp 半導体装置
US7068521B2 (en) * 1998-07-06 2006-06-27 Renesas Technology Corp. Semiconductor device
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225445A (ja) * 1985-07-25 1987-02-03 Toshiba Corp 半導体集積回路装置
JPS62283636A (ja) * 1986-06-02 1987-12-09 Matsushita Electronics Corp 半導体集積回路装置
JPS6362336A (ja) * 1986-09-03 1988-03-18 Nec Corp 半導体集積回路装置
JPS6355539U (ja) * 1986-09-30 1988-04-14
JPS63246832A (ja) * 1987-04-02 1988-10-13 Matsushita Electronics Corp 半導体装置
US7068521B2 (en) * 1998-07-06 2006-06-27 Renesas Technology Corp. Semiconductor device
US7525813B2 (en) 1998-07-06 2009-04-28 Renesas Technology Corp. Semiconductor device
US7817437B2 (en) 1998-07-06 2010-10-19 Renensas Electronics Corporation Semiconductor device
US8295057B2 (en) 1998-07-06 2012-10-23 Murata Manufacturing Co., Ltd. Semiconductor device

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