JP4918652B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4918652B2 JP4918652B2 JP2009205653A JP2009205653A JP4918652B2 JP 4918652 B2 JP4918652 B2 JP 4918652B2 JP 2009205653 A JP2009205653 A JP 2009205653A JP 2009205653 A JP2009205653 A JP 2009205653A JP 4918652 B2 JP4918652 B2 JP 4918652B2
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Description
基板側ボンディング用電極は、基板側入力用電極と基板側出力用電極との間に配置されている。即ち、基板側入力用電極、基板側ボンディング用電極、基板側出力用電極の夫々は、半導体チップの一辺に沿って一直線上に配置されている。
平面が方形状で形成された半導体チップと、一主面側に前記半導体チップが搭載された配線基板と、前記半導体チップの一主面の第1領域に形成され、前記半導体チップの一辺側に配置された第1電極と、前記半導体チップの一主面の第1領域に形成され、入力部が前記第1電極と電気的に接続された第1増幅手段と、前記半導体チップの一主面の第2領域に形成され、前記半導体チップの一辺側に配置された第2電極と、前記半導体チップの一主面の第2領域に形成され、出力部が前記第2電極と電気的に接続された第2増幅手段と、前記半導体チップの一主面の第1領域と第2領域との間の第3領域に形成された第3電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第1ワイヤを介して前記第1電極と電気的に接続された第4電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、第2ワイヤを介して前記第2電極と電気的に接続された第5電極と、前記半導体チップの一辺と向かい合うようにして前記配線基板の一主面に形成され、基準電位に電位固定される第3ワイヤを介して前記第3電極と電気的に接続された第6電極とを有する半導体装置であって、前記第6電極は、前記第5電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。前記第4電極は、前記半導体チップの一辺からの距離が前記第5電極とほぼ同一となる位置、又は前記第6電極よりも前記半導体チップの一辺から遠く離れた位置に配置されている。
半導体装置の小型化を図ることができる。
(実施形態1)
図1は、本発明の実施形態1である高周波電力増幅器の外観構成を示す斜視図であり、図2は、前記高周波電力増幅器の等価回路図であり、図3は図2に示す一点鎖線で囲まれた部分と対応する配線基板の要部平面図であり、図4は図3の要部斜視図であり、図5は図3の要部拡大平面図であり、図6は前記高周波電力増幅器に組み込まれた半導体チップのトランジスタ形成領域における要部断面図であり、図7は、前記半導体チップのアイソレーション領域における要部断面図である。
(1)基板側ボンディング用電極2Cは、基板側入力用電極2A及び基板側出力用電極2Bよりも半導体チップ5の一辺5Xから遠く離れた位置に配置され、基板側ボンディング用電極2Fは、基板側入力用電極2E及び基板側出力用電極2Dよりも半導体チップ5の他の辺5Yから遠く離れた位置に配置されていることから、基板側ボンディング用電極2Cの占有面積に相当する分、基板側入力用電極2Aと基板側出力用電極2Bとの間隔を狭くすることができ、また、基板側ボンディング用電極2Fの占有面積に相当する分、基板側入力用電極2Eと基板側出力用電極2Dとの間隔を狭くすることができるので、半導体チップ5の第1領域5Aと第2領域5Bとの間隔を狭くすることができる。この結果、半導体チップ5の占有面積を縮小することができるので、高周波電力増幅器の小型化を図ることができる。
図8は、本発明の実施形態2である高周波電力増幅器の配線基板の要部平面図である。
図9は、本発明の実施形態3である高周波電力増幅器の配線基板の要部平面図である。
図10は、本発明の実施形態4である高周波電力増幅器の配線基板の要部平面図である。
Claims (4)
- 携帯通信機器に搭載される高周波電力増幅器を含む半導体装置であって、
主面および裏面を有する配線基板と、
前記配線基板の前記主面上に搭載された半導体チップを含み、
前記半導体チップは、
前記高周波電力増幅器を構成する第1および第2の増幅手段と、
前記第1の増幅手段の入力部と電気的に接続するチップ側入力用電極と、
前記第2の増幅手段の出力部と電気的に接続するチップ側出力用電極を含み、
前記配線基板は、前記主面上に、
基板側入力用電極と、
基板側出力用電極と、
を有し、
前記第1の増幅手段の出力部は、前記第2の増幅手段の入力部と電気的に接続され、
前記チップ側入力用電極と前記基板側入力用電極は、入力用ワイヤによって電気的に接続され、
前記チップ側出力用電極と前記基板側出力用電極は、出力用ワイヤによって電気的に接続され、
前記半導体チップの平面形状は、一対の第1の辺および一対の第2の辺を有する四辺形状であり、
前記入力用ワイヤは、前記一対の第1の辺のうちの一つの辺を跨ぐように形成され、
前記出力用ワイヤは、前記一対の第2の辺のうちの一つの辺を跨ぐように形成されていることを特徴とする半導体装置。 - 前記第1および第2の増幅手段はトランジスタであることを特徴とする請求項1記載の半導体装置。
- 前記第1の増幅手段と前記第2の増幅手段は、容量素子を介して電気的に接続されていることを特徴とする請求項1記載の半導体装置。
- 前記配線基板の前記主面には導電プレートが配置され、
前記導電プレート上に前記半導体チップが搭載され、
前記配線基板の前記裏面に基準電位用外部端子が形成され、
前記配線基板の内部にはスルーホール配線が形成され、
前記半導体チップと前記基準電位用外部端子は、前記導電プレートおよび前記スルーホール配線を介して電気的に接続されていることを特徴とする請求項1記載の半導体装置。
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JP2009205653A JP4918652B2 (ja) | 2009-09-07 | 2009-09-07 | 半導体装置 |
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JP2009205653A JP4918652B2 (ja) | 2009-09-07 | 2009-09-07 | 半導体装置 |
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JP2006339316A Division JP2007074000A (ja) | 2006-12-18 | 2006-12-18 | 半導体装置 |
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JPS59126654A (ja) * | 1983-01-10 | 1984-07-21 | Toshiba Corp | 高周波電力増幅器 |
JP2755250B2 (ja) * | 1996-03-22 | 1998-05-20 | 日本電気株式会社 | 半導体集積回路 |
JP3426842B2 (ja) * | 1996-04-16 | 2003-07-14 | 京セラ株式会社 | 高周波用電力増幅器 |
JP2001189404A (ja) * | 1999-12-28 | 2001-07-10 | Hitachi Kokusai Electric Inc | 高周波半導体装置の実装構造及び実装方法 |
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