JPS59195856A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

Info

Publication number
JPS59195856A
JPS59195856A JP58070558A JP7055883A JPS59195856A JP S59195856 A JPS59195856 A JP S59195856A JP 58070558 A JP58070558 A JP 58070558A JP 7055883 A JP7055883 A JP 7055883A JP S59195856 A JPS59195856 A JP S59195856A
Authority
JP
Japan
Prior art keywords
bonding
wire
wires
container
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58070558A
Other languages
English (en)
Other versions
JPH0239866B2 (ja
Inventor
Masataka Mizukoshi
正孝 水越
Teiichi Endo
禎一 遠藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58070558A priority Critical patent/JPS59195856A/ja
Priority to US06/601,360 priority patent/US4618879A/en
Priority to EP84400788A priority patent/EP0126664B1/en
Priority to DE8484400788T priority patent/DE3479271D1/de
Publication of JPS59195856A publication Critical patent/JPS59195856A/ja
Publication of JPH0239866B2 publication Critical patent/JPH0239866B2/ja
Granted legal-status Critical Current

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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置とその製造方法にかかり、特にワイ
ヤボンディング方法に関する。
fbl  従来技術と問題点 半導体装置はxc、msxと益々高集積化されており、
それに伴って半導体チップ並びに半導体容器も大型化さ
れてきた。従って、半導体チップを半導体容器に取りつ
けた後、両者の電極を接続するボンディングワイヤ数も
非常に増加し、LSIでは200本にも及んでいる。
第1図は半導体装置の組立断面図を示しており、■は半
導体チップlO上の接続パッド、2は半導体容器20上
の接続電極で、通常ワイヤ3のボンディングは先に接続
パッド1にボンディングして立ち上り、そのまま空間を
引っ張って(矢印方向)次いで外部リードに電気的に接
続されている接続電極2にボンディングして立ち下り、
ワイヤを切断する方法が採られている。稀には、接続電
極2から接続パッド1にボンディングする方法も採られ
るが、それば特別な都合に限られる。
また、ワイヤは一般に直径20〜30μmのアルミニウ
ム線又は金線が用いられており、ボンディング装置は自
動化された装置である。
このようなボンディング方法において、ワイヤ数が増大
してくるとワイヤは立ち上り部から空間に浮かんで形成
されるために、空間で相互に接触しやすい状態になる。
更に、半導体チップが大きくなって半導体容器が大型化
してくれば、配線ワイヤの長さも長くなるから上記空間
での接触の機会は益々増加し、また配線長さが長くなる
と、配線容量が増えてそれだけ半導体装置の動作特性(
高速動作)に悪影響を与える。
(C1発明の目的 本発明の目的は、半導体装置にとって非常に重要なこの
ような問題点を軽減させる製造方法を提案するものであ
る。
fd)  発明の構成 その目的は、半導体チップと、それを収容する容器と、
該半導体チップ上に形成された電極パッドと該容器に形
成された電極との間を接続するホンディングワイヤとを
具備し、該ホンディングワイヤはボンディング面に対し
て急峻な角度をもって接続された立ぢ上り部と、ホンデ
ング面に対して前記立ち上り部よりもゆるやかな角度を
もって接続された立ち下り部とを有し、隣合うボンディ
ングワイヤの該立ち上り部と該立ち下り部との位置が互
いに逆になるようにワイヤボンディングがなされている
半導体装置によって達成され、且つ該電極バンドが該半
導体チップ周縁に2列に設けられ、且つ該容器の電極が
少なくとも上下2段に設けられている半導体装置によっ
て達成することができる。
また、その製造方法の特徴は半導体チップ上の電極パ・
ノドと、それを収容する容器に形成された電極との間を
ボンディングワイヤで接続するに際し、隣合うボンディ
ングワイヤの一方は該電極パッドを始点として該容器の
電極ヘボンディングし、且つ他方は該容器の電極を始点
として該電極パソドヘボンディングし、隣合うボンディ
ングワイヤのボンディング方向が互いに逆方向になるよ
うにワイヤボンディングを行なうものである。
(e)発明の実施例 以下9図面を参照して実施例によって詳細に説明する。
第2図は本発明にかかる一実施例の組立平面図を示して
おり、半導体チップ10上の接続パッド1と半導体容器
20上の接続電極2とを接続するボンディングワイヤの
ボンディング方向は図中の矢印のように隣接する接続パ
ッド相互間および隣接する接続電極相互間をすべて反対
方向にする。図において、3aは順方向のボンディング
ワイヤ、3bは逆方向のボンディングワイヤを示してお
り、このような配線方法は自動ボンディング装置によっ
て交互に順方向と逆方向とに容易に行うことができる。
第3“図はこのようにして配線したボンディングワイヤ
の部分拡大図を示しており、第3図(a)は断面図、第
3図(blはその平面図である。ワイヤボンディングす
ると、初めにボンディングした接続パソドエまたは接続
電極2の立ち上り部でボンディングワイヤが高く立ち上
がり、それを矢印方向に引っ張ってボンデングして立ち
下がるから、空間ではワイヤ相互を一層遠い間隔にする
ことができて、同じ方向(例えば順方向のみ)に引っ張
ってボンディングするよりも接触しにくくなる。それは
本図によって容易に理解されることである。
次に、接続電極が高低を有する上下段に設けられた半導
体容器上の接続電極とのワイヤボンディング方法につい
て説明する。第4図は本発明によってワイヤボンディン
グした組立平面図を示しており、半導体容器21の下段
の接続電極2Cと半導体チップ11のチップ周縁に近い
接続バ・ノドICとを逆方向にワイヤボンディングし、
半導体容器21の上段の接続電極2dと半導体チップ1
1のチップ周縁より遠い接続パッド1dとを順方向にワ
イヤボンディングする。第5図はその部分拡大図を示し
、第5図(alは断面図、第5図fblは平面図である
。このようにワイヤボンディングすると、空間でワイヤ
ー相互をより遠ざけることが可能になることは、上記例
と同様である。
ここに、第5図に示している半導体チップ11ば接続バ
ンドをチップ周縁に近い接続パッド1cとチップ周縁よ
り遠い接続パッド1dとの二列に形成しているが、現在
では未だこのように接続パッドは高密度には形成されて
いない。本発明によるワイヤボンディング方法を行うこ
とによって、初めて接触の心配が少なくなるから接続パ
ッドを二列にして密度を高くし、かくして半導体チップ
を小さくし、更に半導体容器を小型化することができる
ところで、アルミニウムワイヤを用いる場合には、ボン
ディングツールはウェッジツールと呼ばれるもので、順
方向にボンディングすると半導体容器20上の接続電極
2形成面の面積を考慮する必要がある。それは、その面
積が狭いとウェッジツールの後端が接続電極面の側壁に
当たるためで、そのために従来の順方向のボンデングで
は接続電極面を特に広くしていた。しかし、上記実施例
の下段のように逆方向にホンディングすれば、その接続
電極面は更に狭くすることができて、一層半導体容器の
小型化に役立つ。なお、金ワイヤの場合は、キャピラリ
ーツールであるから、このような心配はない。
また、第5図(clは第5図(alとは反対に上下段共
逆にボンデインクした断面図で、このようにボンディン
グしても空間ではワイヤの距離が従来に比べて遠くなる
から接触の問題は減少する。
(fl  発明の効果 以上の実施例から判るように、本発明によれば空間にお
けるボンディングワイヤ相互の間隔を拡げることができ
て、接触事故を減少させ、半導体装置の信頼度を向上さ
せることが出来る。
且つ、実装密度を高めて高集積化するメリットも大きく
、半導体装置、更には電子回路の特性向上に極めて寄与
するものである。
【図面の簡単な説明】
第1図は従来の半導体装置の組立断面図、第2図は本発
明にかかる一実施例の組立平面図、第3図はその部分拡
大図で、第3図(a)は断九図、第3図(blはその平
面図、第4図は本発明にかかる他の実施例の組立平面図
、第5図はその部分拡大図、第5図(a)は断面図2第
7図(blはその平面図である。 図中、1.lc、lclは接続パッド、2.2C。 2dは接続電極、3.3a、  3bはボンディングワ
イヤ、10.11は半導体チップ、20.21は半導体
容器を示している。 第1図 第2図 第3図 第4図 第5図 (Q)         (b)

Claims (3)

    【特許請求の範囲】
  1. (1)  半導体チップと、それを収容する容器と、該
    半導体チップ上に形成された電極バンドと該容器に形成
    された電極との間を接続するボンディングワイヤとを具
    備し、該ボンディングワイヤはボンディング面に対して
    急峻な角度をもって接続された立ち上り部と、ボンデン
    グ面に対して前記立ち上り部よりもゆるやかな角度をも
    って接続された立ち下り部とを有し、隣合うボンディン
    グワイヤの該立ち上り部と該立ち下り部との位置が互い
    に逆になるようにワイヤボンディングがなされているこ
    とを特徴とする半導体装置。
  2. (2)  k極バッドが該半導体チップ周縁に2列に設
    けられ、且つ該容器の電極が少な(とも上下2段に設け
    られていることを特徴とする特許請求の範囲第1項記載
    の半導体装置。
  3. (3)半導体チップ上の電極パッドと、それを収容する
    容器に形成された電極との間をポンディングワイヤで接
    続するに際し、隣合うボンディングワイヤの一方は該電
    極バンドを始点として該容器の電極ベボンディングし、
    且つ他方は該容器の電極を始点として該電極パッドヘボ
    ンディングし・隣合うポンディングワイヤのボンディン
    グ方向が互いに逆方向になるようにワイヤボンディング
    を行なうことを特徴とする半導体装置の製造方法。
JP58070558A 1983-04-20 1983-04-20 半導体装置及びその製造方法 Granted JPS59195856A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP58070558A JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法
US06/601,360 US4618879A (en) 1983-04-20 1984-04-18 Semiconductor device having adjacent bonding wires extending at different angles
EP84400788A EP0126664B1 (en) 1983-04-20 1984-04-19 Wire bonding method for producing a semiconductor device and semiconductor device produced by this method
DE8484400788T DE3479271D1 (en) 1983-04-20 1984-04-19 Wire bonding method for producing a semiconductor device and semiconductor device produced by this method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58070558A JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPS59195856A true JPS59195856A (ja) 1984-11-07
JPH0239866B2 JPH0239866B2 (ja) 1990-09-07

Family

ID=13434975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58070558A Granted JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法

Country Status (4)

Country Link
US (1) US4618879A (ja)
EP (1) EP0126664B1 (ja)
JP (1) JPS59195856A (ja)
DE (1) DE3479271D1 (ja)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185833A (ja) * 1984-10-03 1986-05-01 Toshiba Corp ワイヤボンデイング方法

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Also Published As

Publication number Publication date
EP0126664A3 (en) 1986-01-22
US4618879A (en) 1986-10-21
JPH0239866B2 (ja) 1990-09-07
DE3479271D1 (en) 1989-09-07
EP0126664A2 (en) 1984-11-28
EP0126664B1 (en) 1989-08-02

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