CN1332445C - 一种高频集成电路多排线打线结构 - Google Patents

一种高频集成电路多排线打线结构 Download PDF

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CN1332445C
CN1332445C CNB200310100690XA CN200310100690A CN1332445C CN 1332445 C CN1332445 C CN 1332445C CN B200310100690X A CNB200310100690X A CN B200310100690XA CN 200310100690 A CN200310100690 A CN 200310100690A CN 1332445 C CN1332445 C CN 1332445C
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wire
pad
routing
chip
metal wire
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CN1595648A (zh
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徐鑫洲
李胜源
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Via Technologies Inc
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Abstract

一种高频集成电路多排线打线结构，此结构具有第一电子组件、第二电子组件及多个金属线。其中，第一电子组件迭合于第二电子组件之上，且第一电子组件相对于迭合面的侧面上周围具有第一群打线垫，第二电子组件于迭合面相同的侧面上周围具有第二群打线垫，又第一群打线垫自周围往中心方向顺序至少可被区分为第一排打线垫与第二排打线垫，且这些金属线中的一个先以反打线方式起始第二群打线垫中的一个并截断于第一排打线垫中的一个，这些金属线中的一个再以正打线方式起始于第一群打线垫中的一个并截断于第二群打线垫中的一个。

Description

一种高频集成电路多排线打线结构
技术领域
本发明是有关于一种高频集成电路多排线打线结构，特别是有关于同时使用正反打线的高频集成电路多排线打线结构，以使芯片与封装体间的电性连接能具有最佳的电气特性。
背景技术
电子封装的目的可以归纳为传递电能、传递电路信号、提供散热途径与结构保护与支持。如果将IC芯片与各种电路零件分别比喻成人体头脑与身体内部的各项器官，电子封装就如将这些器官组合而成的肌肉骨架，封装中的联机电路一如血管神经提供能量与电路信号传递的路径，以使此IC芯片与各种电路封装后所形成的电子产品功能得以发挥。由于电子产品在工作频率与性能上不断推陈出新，因此为使电子产品的电气特性表现能够最佳，封装技术就是一种可使电子产品性能与层次提升的明显因素。
请参考图1，图1绘示的是现有封装组件的俯视示意图。此封装组件100主要具有芯片(头脑)105以及内部含有联机电路(血管神经)的基板110。芯片100与基板110间的电性连接则通过将金属线140等打线于芯片上的打线垫130及基板上的打线垫120来完成。而芯片(头脑)105与布有电子零件(器官)的印刷电路板(未绘示)的电性连接，为信号经由金属线140等以及基板110内部联机电路后，由引脚145导出至印刷电路板来完成。
或请参考图2A，图2A是现有封装组件的剖面示意图。此封装组件200主要包含有基板210以及芯片240。基板210上具有承载垫(die pad)220，并铺上一层环氧树酯层(epoxy，热熔胶)225以承载芯片240。芯片240与基板110间的电性连接则依赖金属线242、243先分别打线于芯片240打线面241上的打线垫245、243，再分别截断于基板210引脚(lead)230、235上的打线垫237、239来达成。
不过，由于射频电路或高速电路对工作频率与性能上有着极大需求的考虑下，现有封装组件会增加信号线的数量，因此会在打线面241上增加打线垫排数(并列或交错排列)，且为了使整个封装组件200能具有较佳的电气特性，更将环氧树酯层225铺的较窄。
请参考图2B，是现有封装组件的剖面示意图。打线垫245、247旁各增加打线垫248、249，且将环氧树酯层225铺比图2A来的窄，因此承载垫220裸露在环氧树酯层225周围的部分即可作为接地端(因承载垫220本身为绝缘体，因此可作为接地端)。由于承载垫220裸露在环氧树酯层225周围的部分即可作为接地端，故打线垫245、247上需接地的信号即不必通过打线垫237、239接地，而直接经由金属线260、270，再通过承载垫220裸露在环氧树酯层225周围的部分(为整圈环绕的线状)接地。如此一来，图2B接地信号接地的距离较图2A的短(金属线260、270比金属线241、243短的多)，因此芯片240的接地点直接通过金属线260、270以较短的距离来连接，同时将此连接至印刷电路板的接地端，以达到较好的电气特性与良好的散热的需求。
不过，在射频电路或高速电路中，封装组件中芯片上的接点虽通过较短距离的金属线与承载芯片的基板相接，提供多点接地处，但是于金属线在打线时高低弧与打陷落点的限制，而使高频的信号在经过此封装组件时，有着较严重的失真情形。况且，在射频电路或高速电路中，封装组件经常例如QFN、BCC++或CSP这类胶膜高度(封装时，封装组件一般会铺上一层胶膜覆盖芯片、金属线以及基板)较低的封装体，而其金属线有着弧高限制与打线时的困难，而无法以在芯片上以三排并列方式来对金属线进行不同弧高的打线。
有鉴于此，本发明提出一种高频集成电路多排线打线结构可有效降低组件间的介入损耗以及返回损耗，而使整体电气特性提升。
发明内容
本发明的主要目的是提供一种高频集成电路多排打线结构，其具有第一电子组件、第二电子组件以多条金属线。其中，第一电子组件还包括有第一打线面、第二承载面以及第一群打线垫。又第二承载面位于第一电子组件相对于第一打线面的一侧表面，而第一群打线垫围绕着第一打线面周围分布置，且第一群打线垫自第一打线面周围往中心方向顺序而至少可被区分为第一排打线垫与第二排打线垫。第二电子组件，则更包括有第二承载面以及第二群打线垫。又第二承载面用以承载第一电子组件并使第一承载面与第二承载面相互邻贴，且使第一电子组件与第二电子组件相互迭合。第二群打线垫则围绕分布于第二承载面周围且与第二承载面位于相同一侧表面上。至于这些金属线，则用以电性连接第一与第二电子组件，且这些金属线依据打线的方式而至少可被区分为若干正打线与若干反打线，且各正打线与反打线均依据打线的方式而分别具有打线的起始端与截断端，其中，这些正打线中的某一的起始端是连接于第一群打线垫中的某一、且这些正打线中的某一的截断端连接于第二群打线垫中的某一，而这些反打线中的某一的起始端却是连接于第二群打线垫中的某一，且这些反打线中的某一的截断端是连接于第一排打线垫中的某一。
综合上述，本发明提出了一种高频集成电路多排打线结构，通过同时使用正打线方式布局第一电子组件与第二电子组件的连接方式，可实现组件间使用多排并列打线，且可有效降低组件间的介入损耗以及返回损耗，而使整体电气特性提升。
本发明的技术方案是这样实现的：一种高频集成电路多排线打线结构，包含有：芯片，配置在基板表面；至少一个接地面，配置在所述基板上，且围绕所述芯片；多个交错排列的第一打线垫，配置在所述芯片上；用于高频信号的多个第二打线垫，配置在所述基板的表面；至少一个第一金属线，所述第一金属线具有第一起始端和第一截断端，所述第一金属线以正打线的方式连接所述第一打线垫的其中之一以及对应的其中一个第二打线垫，从而使所述第一金属线的第一起始端连接对应的第一打线垫，所述第一金属线的第一截断端连接对应的第二打线垫；以及至少一个第二金属线，所述第二金属线具有第二起始端和第二截断端，所述第二金属线以反打线的方式连接所述第一打线垫的其中之一以及对应的接地面，所述第二金属线的第二截断端连接对应的第一打线垫。
本发明还提供了一种高频集成电路多排线打线结构，包含有：芯片，配置在基板表面；至少一个接地面，配置在所述基板上，且围绕所述芯片；多个交错排列的第一打线垫，配置在所述芯片上；用于高频信号的多个第二打线垫，配置在所述基板的表面；至少一个第一金属线，连接所述第一打线垫的其中之一以及对应的其中一个所述第二打线垫；以及至少一个第二金属线，连接所述第一打线垫的其中之一以及对应的所述接地面，其中所述第一金属线的打线弧高高于相邻接的所述第二金属线的打线弧高。
附图说明
图1绘示的是现有封装组件的俯视示意图；
图2A绘示的是现有封装组件的剖面示意图；
图2B绘示的是现有封装组件的剖面示意图；
图3绘示的是现有封装组件以正打线模式布局的立体示意图；
图4绘示的是现有封装组件以反打线模式布局的立体示意图；
图5绘示的是较佳实施例的多排线布局装置的示意图；
图6A、6B分别绘示的是两排及三排交错打线垫群的示意图；
图7A、7B分别绘示的是两排及三排并列打线垫群的示意图；
图8A、8B分别绘示的是现有打线布局方式及本发明较佳实施例打线布局方式的立体示意图；
图9A绘示的是相同结构封装组件分别以现有打线布局及本发明较佳实施例打线布局下，高频信号介入损耗的频率响应比较图；
图9B绘示的是相同结构封装组件分别以现有打线布局及本发明较佳实施例打线布局下，高频信号返回损耗的频率响应比较图；以及
图9C绘示的是9A及9B图中介入损耗与返回损耗的频率响应比较表。
其中，附图标记说明如下：
100、200、300、460、500、800、850：封装组件
105、240、410、465、510、810：芯片
110、210、320、470、520、830：基板
120、130、237、239、245、247、330、335、340、475、480、495、530、535、540、553、557、811、813、815、817、819、821、823、831、833、835：打线垫
350、485、555、840：线状打线垫
140、242、243、260、270、305、315、490、497、533、537、543：金属线
230、235：引脚
220：承载垫
225：环氧树脂层
具体实施方式
为了使本发明的特征、目的及功能有更进一步的认知与了解，现配合附图详细说明如后：
一般来说，封装组件中金属线打线方式可根据打线的起始端与截断端所在的位置来区分正打线或是反打线。举例来说，请参考图3，图3绘示的是现有封装组件以正打线模式布局的立体示意图。在封装时，封装组件300以金属线305先打线于芯片310上的打线垫330后，将金属线305拉高形成一个弧度，最后截断于基板320上的打线垫340。或是以金属线315先打线于芯片310上的打线垫335后，将金属线305拉高形成一个弧度，最后截断于基板320上的接地线350。
这种将金属线先打线于芯片上的打线垫，再将金属线拉高一个弧度，最后将金属线截断于基板上的打线垫或接地线的方式，通常称为正打线的方式。
反之，请参考图4，图4绘示的是现有封装组件以反打线模式布局的立体示意图。在封装时，封装组件460以金属线490先打线于基板470上的打线垫480后，将金属线490拉高形成一个弧度(此弧度较在正打线方式中所形成的弧度大，但弧高较低)，最后截断于芯片465上的打线垫475。或是以金属线497先打线于基板470上的接地线485后，再将金属线497拉高形成一个弧度，最后截断于芯片上的接地线450。
这种将金属线先打线于基板上的打线垫或接地线，再将金属线拉高一个弧度，最后将金属线截断于芯片上打线垫的方式，通常称为反打线的方式。
由于在封装时，正打线的方式有着金属线弧高与QFN胶体高度限制所产生打线时的困难，而无法以在芯片上以三排并列方式来对金属线进行不同弧高的打线。而反打线的方式有着金属线弧度较大，以致芯片与基板间打线长度较长、电气特性较差的不足，且完全不适用于具有多排打线垫的芯片。
基于在射频电路或高速电路中，对封装组件其工作频率与性能有着严苛的要求，因此本发明在以正打线以及反打线的布局作为考虑的基础上，提出一种打线布局装置及方法。
本发明提出了一种同时使用正打线以及反打线方式的高频集成电路多排打线结构及方法。请参考图5，图5绘示的是本发明较佳实施例的多排线布局装置示意图。此多排打线布局装置500主要具有电子组件510及520。此电子组件510及520可分别例如是芯片或是基板，而在此较佳实施例中，电子组件510为芯片，电子组件520为基板。其中，芯片510具有打线面505，芯片510相对于打线面505的另一侧面则具有承载面507。打线面505周围设置有一群打线垫，且自打线面505周围往打线面505中心至少设置有两排以上的打线垫，在此较佳实施例中，打线面505上设置有第一排打线垫530、第二打线垫535以及第三排打线垫540。至于基板520上，则具有承载面550，芯片510的承载面507则迭合于此承载面550之上。
在承载面550周围还设置有一群打线垫，可自承载面550周围往承载面550中心设置多排的打线垫，而在此较佳实施例中，承载面550上设置有两排打线垫553、557，且在承载面550上，还设置有整圈围绕在芯片510周围的线状打线垫555(类似圆圈)。
至于金属线间的布局，为先将金属线以反打线方式起始基板520上打线垫群中的其一并截断于芯片510打线垫群中第一排打线垫中的其一，再将金属线以正打线方式起始于芯片510上打线垫群中的其一并截断于基板520打线垫群中的其一。在此较佳实施例中则是首先将金属线543先以反打线方式起始于线状打线垫555并截断于第一排打线垫530中的某一，再将金属线537以正打线方式起始于第二排打线垫535中的某一并截断于第五排打线垫557中的某一，以及最后将金属线533以正打线方式起始于第三排打线垫540中的某一并截断于第四排打线垫553中的某一。
当金属线543、537、533将芯片510与基板520连接完成后，即可进行胶膜590的铺置，到此，此高频集成电路多排打线结构500即完成。
在此较佳实施例中，由于以反打线方式进行芯片510上第一排打线垫530的打线，因此金属线543在第一排打线垫530上的弧高与第一排打线垫530的高度几乎相同。也因此，芯片510上第二排打线垫535上的金属线537可维持正常弧高，第三排打线垫540上的金属线533也是只需将弧高拉高至较金属线537略高的弧高即可。故本发明的设计除了可运用在两排并列或交错的打线垫群，也可运用在三排并列或交错的打线垫群。
请参考图6A、6B及7A、7B。图6A、6B分别绘示的是为两排及三排交错打线垫群的示意图，图7A、7B分别绘示的是两排及三排并列打线垫群的示意图。
此外，请再参考图5，在此较佳实施例中，高频信号可通过金属线537、533在芯片510与基板520间流通，而高频信号的接地则可通过的金属线543由芯片导引至基板555上的线状打线垫555(通常作为接地端)。因此，可在高频信号的金属线两旁安排与其平行且通过反打线方式产生在芯片端较低弧高、较短距离的接地保护线路，来完成整个高频信号的传输。
所以，本发明多排线布局装置的设计除了将整体金属线弧高降低，同时通过反打线方式可有效降低其介入损耗以及返回损耗，而整体提升组件间的电气特性。
本发明的功能与效果还可通过在相同架构下的封装组件分别施以现有打线布局方式以及本发明正反打线同时运用的布局方式间的比较来得知。请参考图8A及图8B，图8A及图8B分别绘示的是现有打线布局方式及本发明较佳实施例打线布局方式的立体示意图。图8A中，封装组件800具有芯片810以及基板830，芯片810上具有两排打线垫，第一排打线垫为打线垫817～823，第二排打线垫为打线垫811～815。基板上830具有一排打线垫831～835以及线状打线垫840。其中，焊垫813以及打线垫833分别为芯片810及基板830上的信号端，其它打线垫则均为接地端，且打线垫间金属线的连接方式均为：将金属线以正打线方式起始于芯片810上的打线垫群并截断于基板830上的打线垫群。其中，在与打线垫813上信号线平行的两侧，以打线垫819、821上的线路接地作为其保护线路。
同时请参考图8B，在相同的架构下，将图8A中的保护线路以反打线的方式接地，也就是将金属线以反打线的方式起始于线状打线垫840并截断于打线垫819、821。当高频信号于封装组件800中传递时，并且当其线路使用图8B图的打线模式时，此封装组件800的介入损耗以及返回损耗会较其线路使用图8A的打线模式时相对应的减少。此封装组件800在高频信号下，其介入损耗以及返回损耗的实验数据可参考图9A、9B及9C。图9A绘示的是相同结构封装组件分别以现有打线布局及本发明较佳实施例打线布局下，高频信号介入损耗的频率响应比较图。图9B绘示的是相同结构封装组件分别以现有打线布局及本发明较佳实施例打线布局下，高频信号返回损耗的频率响应比较图。图9C绘示的是图9A及9B中介入损耗与返回损耗的频率响应比较表。
综上所述，本发明提供了一种同时运用正反打线方式布局的多排线布局装置以及方法，其中通过反打线方式降低正打线方式金属线的整体弧高，而在胶膜高度的封装体中实现可使用三排并列打线，且通过反打线方式可有效降低高频信号的介入损耗以及返回损耗，使高频信号能完整传递且降低在信号连接端处阻抗不匹配的反射，而提升其整体电气特性。
然而以上所述仅为本发明的较佳实施例，当不能以之限制本发明的范围，因此凡依本发明权利要求所做的均等变化及修饰，仍将不失本发明的要义所在，即不脱离本发明的精神和范围，都应视为本发明的进一步实施例，本发明的保护范围以权利要求书所界定的为准。

Claims (10)

1.一种高频集成电路多排线打线结构，其特征在于包含有：
芯片，配置在基板表面；
至少一个接地面，配置在所述基板上，且围绕所述芯片；
多个交错排列的第一打线垫，配置在所述芯片上；
用于高频信号的多个第二打线垫，配置在所述基板的表面；
至少一个第一金属线，所述第一金属线具有第一起始端和第一截断端，所述第一金属线以正打线的方式连接所述第一打线垫的其中之一以及对应的其中一个第二打线垫，从而使所述第一金属线的第一起始端连接对应的第一打线垫，所述第一金属线的第一截断端连接对应的第二打线垫；以及
至少一个第二金属线，所述第二金属线具有第二起始端和第二截断端，所述第二金属线以反打线的方式连接所述第一打线垫的其中之一以及对应的接地面，所述第二金属线的第二截断端连接对应的第一打线垫。
2.如权利要求1所述的高频集成电路多排线打线结构，其特征在于，在所述芯片上的所述第一打线垫自所述芯片周围往所述芯片中心方向至少可顺序分为第一排以及第二排。
3.如权利要求2所述的高频集成电路多排线打线结构，其特征在于，位于所述芯片的第二排的所述第一打线垫的其中之一用于高频信号传递，而所述第一金属线以正打线的方式连接对应的第一打线垫和第二打线垫。
4.如权利要求3所述的高频集成电路多排线打线结构，其特征在于，位于所述芯片的第一排的所述第一打线垫的其中两个用于接地，而所述第二金属线以反打线的方式连接对应的第一打线垫和接地面。
5.如权利要求4所述的高频集成电路多排线打线结构，其特征在于，所述用于高频信号传递的第一打线垫位于用于接地的两个第一打线垫之间。
6.一种高频集成电路多排线打线结构，其特征在于包含有：
芯片，配置在基板表面；
至少一个接地面，配置在所述基板上，且围绕所述芯片；
多个交错排列的第一打线垫，配置在所述芯片上；
用于高频信号的多个第二打线垫，配置在所述基板的表面；
至少一个第一金属线，连接所述第一打线垫的其中之一以及对应的其中一个所述第二打线垫；以及
至少一个第二金属线，连接所述第一打线垫的其中之一以及对应的所述接地面，
其中所述第一金属线的打线弧高高于相邻接的所述第二金属线的打线弧高。
7.如权利要求6所述的高频集成电路多排线打线结构，其特征在于，所述芯片上的所述第一打线垫自所述芯片周围往所述芯片中心方向顺序至少可被区分为第一排以及第二排。
8.如权利要求7所述的高频集成电路多排线打线结构，其特征在于，位于所述芯片的第二排的所述第一打线垫的其中之一用于高频信号传递。
9.如权利要求8所述的高频集成电路多排线打线结构，其特征在于，所述用于高频信号传递的第一打线垫以正打线的方式通过所述第一金属线连接对应的所述第一打线垫和所述第二打线垫，而所述第二金属线以反打线的方式连接对应的所述第一打线垫和所述接地面。
10.如权利要求8所述的高频集成电路多排线打线结构，其特征在于，位于所述芯片的第一排的所述第一打线垫的其中两个用于接地，并且以反打线的方式与所述接地面连接，而且用于高频信号传递的第一打线垫位于用于接地的两个第一打线垫之间。
CNB200310100690XA 2003-10-09 2003-10-09 一种高频集成电路多排线打线结构 Expired - Lifetime CN1332445C (zh)

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US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles
US6194786B1 (en) * 1997-09-19 2001-02-27 Texas Instruments Incorporated Integrated circuit package providing bond wire clearance over intervening conductive regions
US6288444B1 (en) * 1998-11-17 2001-09-11 Fujitsu Limited Semiconductor device and method of producing the same
US6559536B1 (en) * 1999-12-13 2003-05-06 Fujitsu Limited Semiconductor device having a heat spreading plate

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US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles
US6194786B1 (en) * 1997-09-19 2001-02-27 Texas Instruments Incorporated Integrated circuit package providing bond wire clearance over intervening conductive regions
US6288444B1 (en) * 1998-11-17 2001-09-11 Fujitsu Limited Semiconductor device and method of producing the same
US6559536B1 (en) * 1999-12-13 2003-05-06 Fujitsu Limited Semiconductor device having a heat spreading plate

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