JPS61101067A - メモリモジユ−ル - Google Patents

メモリモジユ−ル

Info

Publication number
JPS61101067A
JPS61101067A JP59223201A JP22320184A JPS61101067A JP S61101067 A JPS61101067 A JP S61101067A JP 59223201 A JP59223201 A JP 59223201A JP 22320184 A JP22320184 A JP 22320184A JP S61101067 A JPS61101067 A JP S61101067A
Authority
JP
Japan
Prior art keywords
memory
electrodes
chip carrier
chip
carriers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59223201A
Other languages
English (en)
Inventor
Hajime Nakamura
肇 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59223201A priority Critical patent/JPS61101067A/ja
Publication of JPS61101067A publication Critical patent/JPS61101067A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多数のメモリ装置が高密度に実装されたメモリ
モジュールに関する。
近年、各種電子機器に使われているメモＩＪ　Ｉ　ＣＯ
量は膨大であシ、需要は年々増大している。
〔従来の技術〕
メモリＩＣは通常、モールド、あるいはセラミックケー
スで封止されデュアル・イン・ラインパッケージ（ＤＩ
Ｐ）として使われている。
〔発明が解決しようとする問題点〕
電子機器のメモリ谷型を増大するには、限られたスペー
スにできるだけ多くのメモリＩＣを搭載する必要が、Ｄ
ＩＰ型のパッケージでは比較的大きな実装スペースを必
要とする。
本発明の目的はメモＩＪ　Ｉ　Ｃを限られたスペースに
、高密度で実装できるメモリモジュールを提供するもの
である。
〔問題点を解決するだめの手段〕
本発明は各メモリ装置をチップキャリア方式で構成し、
複数個を縦方向に積み重ねたことを特徴とする。
〔実施例〕
第１図乃至第７図を参照して本発明の詳細な説明を以下
に述べる。
メモリＩＣを使用した回路として、１６ｋｘ８ｂｉｔの
Ｓ　ＲＡＭ　（Ｓｔａｔ　ｉｃ　Ｒａｎｄａｍ　Ａｃｃ
ｅｓｓ　Ｍｅｍｏｒｙ）ＩＣを４ケ使用した回路を第１
図に示す。これよシ分るように、ＡＯ−Ａｌ　Ｏ、ＩＯ
１〜■０８゜１〜メモリ’　Ｉ　Ｃ４において共通の配
線であり、ＣＥｌのみ各ＩＣ毎に独立に人力される。こ
の点を利用して本発明においては、第２図に示すように
チップキャリアの周辺部表面に電極３を形成しておきこ
れらの電極３はチップキャリア内の電極２とそれぞれ接
続されている。
チップキャリアを京ねた時に、周辺部の電極３は他のチ
ップキャリアの裏面電極（第３図３）と軍なり合うよう
目装置することにより、チップキャリアを皿ね合わせた
けで電気的接続がとれるようにし、小型化することを可
能にしたものである。
なお、４は半纏体素子でこの電極はチップキャリアの内
部電極２にワイヤボンディングされている。
第４図は本発明によるチップキャリアの断面図でアシ、
キャリア周辺部及び側面、及び裏面にチップキャリア相
互間の接続を行う電極３を有している。
第５図はチップキャリアにメモリＩＣ４をマウントし、
ワイヤーボンディングした後、樹脂５で封止したもので
あシ、チップキャリアは必要に応じてバーン、イン、テ
スト、及び電気的特性検査を行い、良品を選びだす。
良品のチップキャリアは、第６図に示すように電極３に
半田６を供給する。
次に、チップキャリアを必賛数だけ（第７図の場合４ケ
）Ｎね合せ、半田リフロ一工程を通すことにより、各チ
ップキャリアは電気的９機械的に接続され、メモリモジ
ュールとなる。
尚ＣＥ、のように各ＩＣ毎に独立して出す必要のある電
極は各ＩＣ毎に異なった電極パッドに接続しておけばよ
い。
〔発明の効果〕
以上述べたように、本発明によれば、チップキャリアを
使用するためモジュールに組み込む前に充分な検査が行
えるため、歩留シが高いこと、またチップキャリア１ケ
の高さはせいぜい２關くらいであるため４ヶ重ねても８
朋と大幅に小型化が可能になる等の効果が得られるもの
である。
【図面の簡単な説明】
第１図は１６ｋｘ８ｂｉｔのＳＲＡＭＩＣを４ヶ使った
メモリモジュールの１回路例、第２図、第３図は本発明
によるチップキャリアの表側からの図と裏側の図である
。第４〜第７図は、本発明によるメモリモジュールの各
製造プロセスの断面図である。 １・・・・・・セラミック、２・・・・・・ＩＣ搭載用
電極、３・・・・・・チップキャリア接続用電極、４・
・・・・・メモリＩＣ１訃・・・・・封止樹脂、６・・
・・・・半田。

Claims (1)

    【特許請求の範囲】
  1. 　夫々がメモリチップを内蔵し、かつ容器外壁に該チッ
    プの電極を外部へ導出するための電極パターンを有する
    複数の半導体装置を重ね合せ、もって前記容器外壁の電
    極パターン相互間を電気的に接続したことを特徴とする
    メモリモジュール。
JP59223201A 1984-10-24 1984-10-24 メモリモジユ−ル Pending JPS61101067A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59223201A JPS61101067A (ja) 1984-10-24 1984-10-24 メモリモジユ−ル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59223201A JPS61101067A (ja) 1984-10-24 1984-10-24 メモリモジユ−ル

Publications (1)

Publication Number Publication Date
JPS61101067A true JPS61101067A (ja) 1986-05-19

Family

ID=16794372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59223201A Pending JPS61101067A (ja) 1984-10-24 1984-10-24 メモリモジユ−ル

Country Status (1)

Country Link
JP (1) JPS61101067A (ja)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992849A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded board multiple integrated circuit module
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5241450A (en) * 1992-03-13 1993-08-31 The United States Of America As Represented By The United States Department Of Energy Three dimensional, multi-chip module
US5363067A (en) * 1993-05-19 1994-11-08 Motorola, Inc. Microstrip assembly
US5426563A (en) * 1992-08-05 1995-06-20 Fujitsu Limited Three-dimensional multichip module
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5568361A (en) * 1992-03-17 1996-10-22 Massachusetts Institute Of Technology Three-dimensional electronic circuit of interconnected modules
US5583375A (en) * 1990-06-11 1996-12-10 Hitachi, Ltd. Semiconductor device with lead structure within the planar area of the device
US5691885A (en) * 1992-03-17 1997-11-25 Massachusetts Institute Of Technology Three-dimensional interconnect having modules with vertical top and bottom connectors
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5723900A (en) * 1993-09-06 1998-03-03 Sony Corporation Resin mold type semiconductor device
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5801439A (en) * 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
US5815427A (en) * 1997-04-02 1998-09-29 Micron Technology, Inc. Modular memory circuit and method for forming same
US6002167A (en) * 1995-09-22 1999-12-14 Hitachi Cable, Ltd. Semiconductor device having lead on chip structure
EP0862217A3 (en) * 1992-05-26 1999-12-15 Motorola, Inc. Semiconductor device and semiconductor multi-chip module
US6022759A (en) * 1994-09-20 2000-02-08 Fujitsu Limited Method for producing a semiconductor device, base member for semiconductor device and semiconductor device unit
KR100271640B1 (ko) * 1997-12-27 2000-11-15 김영환 반도체 패키지 및 그 적층구조
US6188127B1 (en) 1995-02-24 2001-02-13 Nec Corporation Semiconductor packing stack module and method of producing the same
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
US6683373B1 (en) * 1999-08-02 2004-01-27 Alcatel Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby
US6717251B2 (en) * 2000-09-28 2004-04-06 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US6763578B2 (en) 1988-09-30 2004-07-20 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6815263B2 (en) 2000-05-17 2004-11-09 Dr. Johannes Heidenhain Gmbh Component assembly and method for producing the same
US6885106B1 (en) 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
US6897090B2 (en) 1994-12-29 2005-05-24 Tessera, Inc. Method of making a compliant integrated circuit package
US6913949B2 (en) 2001-10-09 2005-07-05 Tessera, Inc. Stacked packages
DE19802347B4 (de) * 1997-09-12 2005-10-06 LG Semicon Co., Ltd., Cheongju Stapelbares Halbleitersubstrat und stapelbare Halbleiterbaugruppe sowie Herstellungsverfahren derselben und Herstellungsverfahren eines stapelbaren Halbleiterbaugruppenmoduls
US6983536B2 (en) 1991-06-04 2006-01-10 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
US7843051B2 (en) * 2007-09-28 2010-11-30 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
USRE45463E1 (en) 2003-11-12 2015-04-14 Tessera, Inc. Stacked microelectronic assemblies with central contacts

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US6763578B2 (en) 1988-09-30 2004-07-20 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US4992849A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded board multiple integrated circuit module
US5583375A (en) * 1990-06-11 1996-12-10 Hitachi, Ltd. Semiconductor device with lead structure within the planar area of the device
US6983536B2 (en) 1991-06-04 2006-01-10 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5241450A (en) * 1992-03-13 1993-08-31 The United States Of America As Represented By The United States Department Of Energy Three dimensional, multi-chip module
US5568361A (en) * 1992-03-17 1996-10-22 Massachusetts Institute Of Technology Three-dimensional electronic circuit of interconnected modules
US5691885A (en) * 1992-03-17 1997-11-25 Massachusetts Institute Of Technology Three-dimensional interconnect having modules with vertical top and bottom connectors
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
EP0862217A3 (en) * 1992-05-26 1999-12-15 Motorola, Inc. Semiconductor device and semiconductor multi-chip module
US5426563A (en) * 1992-08-05 1995-06-20 Fujitsu Limited Three-dimensional multichip module
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5363067A (en) * 1993-05-19 1994-11-08 Motorola, Inc. Microstrip assembly
US5723900A (en) * 1993-09-06 1998-03-03 Sony Corporation Resin mold type semiconductor device
US5760471A (en) * 1994-04-20 1998-06-02 Fujitsu Limited Semiconductor device having an inner lead extending over a central portion of a semiconductor device sealed in a plastic package and an outer lead exposed to the outside of a side face of the plastic package
US5801439A (en) * 1994-04-20 1998-09-01 Fujitsu Limited Semiconductor device and semiconductor device unit for a stack arrangement
US6022759A (en) * 1994-09-20 2000-02-08 Fujitsu Limited Method for producing a semiconductor device, base member for semiconductor device and semiconductor device unit
US6897090B2 (en) 1994-12-29 2005-05-24 Tessera, Inc. Method of making a compliant integrated circuit package
US6188127B1 (en) 1995-02-24 2001-02-13 Nec Corporation Semiconductor packing stack module and method of producing the same
US6002167A (en) * 1995-09-22 1999-12-14 Hitachi Cable, Ltd. Semiconductor device having lead on chip structure
US5815427A (en) * 1997-04-02 1998-09-29 Micron Technology, Inc. Modular memory circuit and method for forming same
DE19802347B4 (de) * 1997-09-12 2005-10-06 LG Semicon Co., Ltd., Cheongju Stapelbares Halbleitersubstrat und stapelbare Halbleiterbaugruppe sowie Herstellungsverfahren derselben und Herstellungsverfahren eines stapelbaren Halbleiterbaugruppenmoduls
KR100271640B1 (ko) * 1997-12-27 2000-11-15 김영환 반도체 패키지 및 그 적층구조
US6380616B1 (en) 1998-01-15 2002-04-30 Infineon Technologies Ag Semiconductor component with a number of substrate layers and at least one semiconductor chip, and method of producing the semiconductor component
US6683373B1 (en) * 1999-08-02 2004-01-27 Alcatel Method of modifying connecting leads and thinning bases of encapsulated modular electronic components to obtain a high-density module, and a module obtained thereby
US6815263B2 (en) 2000-05-17 2004-11-09 Dr. Johannes Heidenhain Gmbh Component assembly and method for producing the same
US6717251B2 (en) * 2000-09-28 2004-04-06 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US6885106B1 (en) 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
US6913949B2 (en) 2001-10-09 2005-07-05 Tessera, Inc. Stacked packages
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
USRE45463E1 (en) 2003-11-12 2015-04-14 Tessera, Inc. Stacked microelectronic assemblies with central contacts
US7843051B2 (en) * 2007-09-28 2010-11-30 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Similar Documents

Publication Publication Date Title
JPS61101067A (ja) メモリモジユ−ル
KR0147259B1 (ko) 적층형 패키지 및 그 제조방법
US6376914B2 (en) Dual-die integrated circuit package
US5563446A (en) Surface mount peripheral leaded and ball grid array package
JPS63211660A (ja) 集積回路用高端子数パッケージ
US8253228B2 (en) Package on package structure
KR19990006158A (ko) 볼 그리드 어레이 패키지
JP2001156251A (ja) 半導体装置
CA1165465A (en) Over/under dual in-line chip package
JPH08279588A (ja) 半導体集積回路装置及び半導体集積回路装置の製造方法
JPH06177501A (ja) メモリモジュール
JPH04196253A (ja) 半導体装置用パッケージ
JPH02229461A (ja) 半導体装置
KR970005719B1 (ko) 이중 어태치된 메모리 장치용 반도체 패키지
JPS617657A (ja) マルチチツプパツケ−ジ
JPS5996759A (ja) 半導体装置
JPH0473298B2 (ja)
JPS62277753A (ja) 半導体パツケ−ジ
JPH06216492A (ja) 電子装置
JP2529254B2 (ja) Ｉｃ実装装置
KR100480908B1 (ko) 적층 칩 패키지의 제조 방법
JPS6276753A (ja) 半導体装置およびその製造方法
JPH0121568Y2 (ja)
JPH02280359A (ja) 半導体装置
US5691243A (en) Process for manufacturing composite semiconductor device