CN1328787C - 半导体芯片封装体的焊线排列结构 - Google Patents

半导体芯片封装体的焊线排列结构 Download PDF

Info

Publication number
CN1328787C
CN1328787C CNB2004100020938A CN200410002093A CN1328787C CN 1328787 C CN1328787 C CN 1328787C CN B2004100020938 A CNB2004100020938 A CN B2004100020938A CN 200410002093 A CN200410002093 A CN 200410002093A CN 1328787 C CN1328787 C CN 1328787C
Authority
CN
China
Prior art keywords
bonding wire
power supply
weld pad
packaging
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2004100020938A
Other languages
English (en)
Other versions
CN1595645A (zh
Inventor
谢佳容
陈俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Priority to CNB2004100020938A priority Critical patent/CN1328787C/zh
Publication of CN1595645A publication Critical patent/CN1595645A/zh
Application granted granted Critical
Publication of CN1328787C publication Critical patent/CN1328787C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体芯片封装体的焊线排列结构，包括：至少一组差动信号焊线，由一芯片连接至一封装基板上并具有差动信号；以及至少两电源焊线，分别排列在所述至少一组差动信号焊线的两侧，由芯片连接至所述封装基板。利用所述电源焊线包围差动信号焊线组或者是一般信号焊线，而使得信号焊线能受到更完整的屏蔽保护。

Description

半导体芯片封装体的焊线排列结构
技术领域
本发明涉及一种半导体芯片的封装结构，特别涉及一种半导体芯片封装体的焊线排列结构。
背景技术
电子封装的目的可以归纳为传递电能、传递电路信号、提供散热途径与结构保护及支持。如果将芯片当作是人体中的头脑，那么各种电路零件可视为人体内部的各项器官，而电子封装则有如将这些器官组合而成的肌肉骨架，封装中的联机电路一如血管神经提供能量与电路信号传递的路径，以使此芯片与各种电路零件封装后所形成的电子产品的功能得以发挥。由于电子产品在工作频率与效能上不断推陈出新，因此为使电子产品的电气特性表现最佳，封装技术即是一种可使电子产品的效能与层次提升的重要因素。
以使用金属打线的高频电子封装为例，半导体芯片与内含多层电路板的封装基板间的电连接即可通过信号焊线旁包围接地线来达到较佳的电气特性。通常使用接地线可以达到隔离噪声与防止信号耦合干扰的效果，于是使用各种不同的焊线排列，成为半导体封装技术中一项创新的发明。
但是，在某些半导体芯片中，没有足够的接地线可以进行噪声隔离或阻止信号间的电感耦合现象，因此，必须使用其它的线路来完成此项工作。
发明内容
有鉴于此，本发明提出一种半导体芯片封装体的焊线排列结构及其排列方法，利用电源焊线来保护信号焊线的信号传递，利用电源焊线与信号焊线之间各种不同的排列方式，以及半导体芯片的焊垫与封装基板上的引脚的排列组合，完全保护信号焊线的信号传输，避免遭受到噪声干扰，隔绝信号焊线间的电感耦合现象。
本发明揭示一种半导体芯片封装体的焊线配置结构，在封装体的差动信号焊线组的两侧，各配置一条电源焊线，以包围所述差动信号焊线组，以完成噪声隔离与防止电感耦合效应。
所述半导体芯片封装体的焊线排列结构，至少包含：至少一组差动信号焊线，由一芯片连接至一封装基板上并具有差动信号；以及至少两电源焊线，分别排列在所述至少一组差动信号焊线的两侧，而且由所述芯片连接至所述封装基板。
本发明还揭示了一种半导体芯片封装体的焊线配置结构，在差动信号焊线组的两侧，各配置至少一条电源焊线，使得一组差动信号焊线组至少两条或以上的电源焊线所包围，将会有助于差动信号焊线组的信号传递，降低噪声干扰与减少差动信号线组之间的信号干扰。
本发明又揭示了一种半导体芯片封装体的焊线配置结构，在差动信号焊线组的两侧，各配置两条电源焊线，使得一组差动信号焊线组至少由四条的电源焊线所包围，将会使得每一组差动信号焊线组在上下左右的方向将被电源焊线所包围，有助于差动信号焊线组的信号传递，减少差动信号焊线组之间的电感耦合干扰。
附图说明
图1A显示本发明的第一具体实施例，为半导体芯片封装体的焊线排列结构的俯视示意图；
图1B显示本发明的第一具体实施列，为半导体芯片封装体的焊线排列结构的剖面示意图；
图2A显示本发明的第二具体实施例，为半导体芯片封装体的焊线排列结构的俯视示意图；以及
图2B显示本发明的第二具体实施例，为半导体芯片封装体的焊线排列结构的剖面示意图。
其中，附图标记说明如下：
100    封装基板
11     半导体芯片
21        接地环
31        电源环
50        引脚
P1～P6    电源焊垫
S1+、S1-、S2+、S2-、S3+、S3-、S4+与S4-信号焊垫
具体实施方式
为了在封装工艺时，使信号焊线间不会互相干扰，且不会有信号焊线与接地线互相接触的情况发生。本发明特别考虑在信号焊线两旁，以电源焊线加以包围，且这些电源焊线与信号焊线一样从半导体芯片连接至封装基板之上，再由封装基板上的引脚短接至原本就用来耦接电源的电源环。以同时使信号焊线间不会互相干扰，且在封装工艺时与封装工艺之后，信号焊线与电源焊线间不会有任何接触。本发明揭示一种芯片封装体的焊线排列结构，至少一信号焊线连接芯片与封装基板上，并利用至少两条电源焊线，包围信号焊线的两侧，而电源焊线由芯片连接至封装基板。
请参考图1A，此图显示本发明的第一具体实施例的俯视示意图，于封装基板100之上安置半导体芯片11，此半导体芯片11连接在封装基板100的上表面，而且在封装基板100的上表面设置有接地环21与电源环31，在接地环21与电源环31的外围设置许多个引脚50。换言之，接地环21与电源环31设置在引脚50与半导体芯片11的中间。
请继续参阅图1A，在半导体芯片11上设置许多个焊垫，这些焊垫包括电源焊线与信号焊线，用来将半导体芯片11上的信号传输到封装基板100，或者将印刷电路板要传输至半导体芯片的信号或电源，经由封装基板100的引脚50，以焊线连接至半导体芯片11上的焊垫，达到信号传输的目的。半导体芯片11的焊垫，包括电源焊垫P1～P4、信号焊垫S1+、S1-、S2+、S2-、S3+、S3-、S4+与S4-。这些焊垫的排列方式是以两两交错的方式进行排列，换言之，这些焊垫以两排直线来进行排列，第一个焊垫排列在第一条直线上时，则第二个焊垫排列在第二条直线上，使得所有相邻的焊垫都是两两相错，如电源焊垫P1与信号焊垫S1+是相错开，不会排列在同一条直线之上；如信号焊垫S1+与信号焊垫S1-是相错开，也不会排列在同一条直线上。其中，信号焊垫S1+与S1-为差动信号(differential signal)组，当其中一个焊垫传输信号为1时，则另一个焊垫的传输信号一定为0，使得连接这两个焊垫的信号焊线所传输的信号一定是相反，使得高频电子组件能够有较好的信号传输品质。其它的差动信号组(例如：S2+与S2-，S3+与S3-，S4+与S4-)也以同样的方式来传输信号。
请继续参阅图1A，半导体芯片11上的焊垫经由焊线连接至封装基板100上的相对应的引脚50，使得半导体芯片上的电子组件，能够经由封装基板100来传输信号与供应电源。根据本发明的第一具体实施例，封装基板100上的引脚50的排列方式，是排列在同一直在线，而连接电源焊垫的引脚50以封装基板的内部布线来连接至封装基板100上的电源环31。
请参阅图1B，此图为图1A在AA’线的剖面图，显示出焊线的排列方式，经由在半导体芯片11上的焊垫排列，焊线的排列将会是每一组差动信号焊线(如S1+与S1-)的两侧分别紧邻一个电源焊线(如P1与P2)，这将使得电源焊线将差动信号焊线包围起来。由于电源焊线具有稳定的信号性质，与接地线同样为直流信号，因此在差动信号焊线的两侧包围电源焊线，将会有助于差动信号焊线组的信号品质，避免两个差动信号组之间的信号干扰与电感耦合现象，对于高频电子组件而言，将有效提供信号传输品质。
请参阅图2A，此图显示本发明的第二具体实施例的俯视示意图，在半导体芯片11上的焊垫排列，包括电源焊垫P1～P6、信号焊垫S1+、S1-、S2+、S2-、S3+与S3-。在每一组差动信号焊垫(例如S1+与S1-)两侧，分别紧邻设置两个电源焊垫，换言之，在差动信号焊垫组的第一侧紧邻设置两个电源焊垫P1与P2，在差动信号焊垫组的第二侧紧邻设置两个电源焊垫P3与P4，使得每一组差动信号组被四个电源焊垫或电源焊线所包围。而信号焊垫与电源焊垫经由焊线，连接至在封装基板100上的相对应引脚50之上。而在半导体芯片11上的电源焊垫与信号焊垫是以两两相错的方式进行排列，如本发明的第一具体实施例。而在本发明的第二具体实施例的封装基板100上的引脚50，也是以两两相错的方式进行排列，使得连接焊垫与引脚的焊线，在相邻的两条焊线具有不同的长度。
请参阅图2B，此图显示图2A的AA’线的剖面示意图，一组差动信号焊线(如S1+与S1-)被四条电源焊线(P1、P2、P3、P4)以上下立体的方式所包围，使得差动信号焊线组不只在直线方面被包围，同时也在上下方向被电源焊线所包围。这样的焊线配置方法，将更有效的保护信号焊线的信号传递，减少差动信号焊线组之间的信号干扰与电感耦合效应，尤其对于高频电子组件的信号传递有更好的屏蔽效果。
综合上述，本发明提出一种半导体芯片封装体的焊线配置结构，利用电源焊线包围差动信号焊线组或者是一般信号焊线，而使得信号焊线能受到更完整的屏蔽保护。同时，本发明还可使得封装体内的焊线回路具有较低的回路电感以及较佳的匹配阻抗。
以上所述仅为本发明的较佳实施例，当不能以此限制本发明的范围。即凡依本发明权利要求所作的均等变化及修饰，都应视为本发明的进一步实施形式。

Claims (8)

1.一种芯片封装体的焊线排列结构，其中包含：
至少一组差动信号焊线，由一芯片连接至一封装基板上并具有差动信号；以及
至少两电源焊线，分别排列在所述至少一组差动信号焊线的两侧，而且由所述芯片连接至所述封装基板。
2.如权利要求1所述的芯片封装体的焊线排列结构，其中所述至少一组差动信号焊线由所述芯片上的焊垫连接至所述封装基板上的引脚。
3.如权利要求1所述的芯片封装体的焊线排列结构，其中所述电源焊线由所述芯片上的焊垫连接至所述封装基板上的引脚。
4.如权利要求1所述的芯片封装体的焊线排列结构，其中在所述芯片上，耦接所述至少两电源焊线的两焊垫分别紧邻于耦接所述至少一组差动信号焊线的焊垫的两侧。
5.如权利要求1所述的芯片封装体的焊线排列结构，其中所述封装体上用来耦接电源焊线的电源环位于所述芯片与所述封装基板的引脚之间。
6.如权利要求1所述的芯片封装体的焊线排列结构，其中所述至少一组差动信号焊线的第一侧被第一电源焊线与第二电源焊线所包围，而所述至少一组差动信号焊线的第二侧被第三电源焊线与第四电源焊线所包围。
7.如权利要求6所述的芯片封装体的焊线排列结构，其中所述第一电源焊线、所述第二电源焊线、所述第三电源焊线与所述第四电源焊线是从所述芯片连接至所述封装基板的一第一引脚、一第二引脚，一第三引脚与一第四引脚，而所述第一引脚与所述第二引脚为交错排列，所述第二引脚与所述第三引脚为交错排列，所述第三引脚与所述第四引脚为交错排列。
8.如权利要求6所述的芯片封装体的焊线排列结构，其中所述第一电源焊线、所述第二电源焊线、所述第三电源焊线与所述第四电源焊线是从所述芯片的一第一焊垫、一第二焊垫、一第三焊垫与一第四焊垫连接至所述封装基板，而所述第一焊垫与所述第二焊垫为交错排列，所述第三焊垫与所述第四焊垫为交错排列。
CNB2004100020938A 2004-01-15 2004-01-15 半导体芯片封装体的焊线排列结构 Expired - Lifetime CN1328787C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100020938A CN1328787C (zh) 2004-01-15 2004-01-15 半导体芯片封装体的焊线排列结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100020938A CN1328787C (zh) 2004-01-15 2004-01-15 半导体芯片封装体的焊线排列结构

Publications (2)

Publication Number Publication Date
CN1595645A CN1595645A (zh) 2005-03-16
CN1328787C true CN1328787C (zh) 2007-07-25

Family

ID=34662369

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100020938A Expired - Lifetime CN1328787C (zh) 2004-01-15 2004-01-15 半导体芯片封装体的焊线排列结构

Country Status (1)

Country Link
CN (1) CN1328787C (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077037A (ja) * 1993-06-16 1995-01-10 Hitachi Ltd 半導体集積回路装置
US5497030A (en) * 1993-06-24 1996-03-05 Shinko Electric Industries Co., Ltd. Lead frame and resin-molded-type semiconductor device
CN1250227A (zh) * 1998-09-18 2000-04-12 株式会社日立制作所 半导体装置
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US20030094703A1 (en) * 2001-11-22 2003-05-22 Chung-Ju Wu Integrated circuit bonding device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077037A (ja) * 1993-06-16 1995-01-10 Hitachi Ltd 半導体集積回路装置
US5497030A (en) * 1993-06-24 1996-03-05 Shinko Electric Industries Co., Ltd. Lead frame and resin-molded-type semiconductor device
CN1250227A (zh) * 1998-09-18 2000-04-12 株式会社日立制作所 半导体装置
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US20030094703A1 (en) * 2001-11-22 2003-05-22 Chung-Ju Wu Integrated circuit bonding device and manufacturing method thereof

Also Published As

Publication number Publication date
CN1595645A (zh) 2005-03-16

Similar Documents

Publication Publication Date Title
US7609500B2 (en) Universal energy conditioning interposer with circuit architecture
US7110227B2 (en) Universial energy conditioning interposer with circuit architecture
US9054094B2 (en) Energy conditioning circuit arrangement for integrated circuit
JP3530920B2 (ja) 多層パッケージ、パッケージング方法及び多層パッケージ化半導体装置
CN101615604B (zh) 半导体器件和半导体集成电路
CN107221527B (zh) 半导体封装件
JP2013033988A (ja) 回路基板およびこれを利用した半導体パッケージ
KR20040012864A (ko) 반도체장치
CN206961822U (zh) 芯片的封装结构及印刷电路板
CN106935572A (zh) 改进在射频和毫米波产品中的bga封装隔离的方法
EP3547363B1 (en) Electronic assembly and electronic system with impedance matched interconnect structures
US20100164076A1 (en) Stacked semiconductor package
EP1714530B1 (en) Method for increasing a routing density for a circuit board and such a circuit board
KR100586278B1 (ko) 본딩 와이어 차폐 구조를 가지는 고속 반도체 패키지용인쇄 회로 기판
CN101142676B (zh) 电子器件和载体基板
KR20070059000A (ko) 전자 디바이스 및 이것에 이용하는 패키지
CN1328787C (zh) 半导体芯片封装体的焊线排列结构
CN110911384A (zh) 一种嵌入式无源桥接芯片及其应用
CN100392849C (zh) 封装体及封装体模块
CN101212858B (zh) 线路基板
WO2012153835A1 (ja) プリント配線基板
US20030148077A1 (en) High-performance laminate for integrated circuit interconnection
CN218959183U (zh) 印刷电路板和电子装置
CN1332445C (zh) 一种高频集成电路多排线打线结构
TWI244189B (en) Arrangement of bonding wires in a semiconductor chip package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20070725