TWI244189B - Arrangement of bonding wires in a semiconductor chip package - Google Patents
Arrangement of bonding wires in a semiconductor chip package Download PDFInfo
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- TWI244189B TWI244189B TW093100010A TW93100010A TWI244189B TW I244189 B TWI244189 B TW I244189B TW 093100010 A TW093100010 A TW 093100010A TW 93100010 A TW93100010 A TW 93100010A TW I244189 B TWI244189 B TW I244189B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
之技術領域】 疋有關於一種半導體晶片之封裝結構 將半導體晶片封裝體之銲線排列詰構 以歸納 構保護 種電路 如將這 _如血 片與各 。由於 此為使 一種可 為傳遞 與支持 零件可 些器官 管神經 種電路 在電子 電子產 使電子 電能、傳 。如果將 視為人體 組合而成 提供能量 零件封裝 產品在工 品之電氣 產品效能 1244189 '五、發明說明（！） 【發明所屬 本發明 有關於一種 【先前技術 電子封 號、提供散 人體中的頭 器s ’而電 架，封裝中 傳遞的路徑 電子產品功 能上不斷推 夠最佳，封 的顯然因素 舉使用 内含多層電 線旁包圍接 可以達到隔 各種不同的 發明。 但是， 來進行雜訊 須使用其他 裝的目的可 熱途徑與結 腦，那麼各 子封裝則有 的連線電路 ’以使此晶 能得以發揮 陳出新，因 裝技術即是 特別是 遞電路訊 晶片當作是 内部的各項 的肌肉骨 與電路訊號 後所形成的 作頻率與效 特性表現能 與層次提升 金屬打線之高頻電子封裝為例，半導體晶片與 路板之封裝基板間之電性連接即可透過訊號銲 地線來達到較佳之電氣特性。通常使用接地線 f雜訊與防止訊號耦合干擾的效果，於是使用 杯線排列’成為半導體封裝技術中一項創新的 在某些半導體晶片中，沒有足夠的接地線可以 隔離或阻止訊號間的電感耦合現象，因此，必 的線路來完成此項工作。[Technical field] There is a packaging structure of a semiconductor wafer. Arrangement of the bonding wires of the semiconductor wafer package structure can be summarized to protect the circuit. Such as this. Because this is to make a kind of transmission and support parts, organs, nerves, and nerves, a kind of circuit can produce electronic energy and transmit electricity in electronics. If it is regarded as a human body, it will provide the energy efficiency of the encapsulation products of electrical parts. The product's electrical product efficiency is 1244189 'V. Description of the invention (!) [The invention belongs to the present invention is related to a [prior art electronic seal, providing a head device in the human body] s' Electrical frame, the path of the electronic product in the package is constantly pushing the best function, the obvious factor of the sealing is to use a multi-layer wire next to the surrounding connection can achieve a variety of different inventions. However, to carry out the noise, you must use other packaging purposes to thermally connect the circuit and the brain. Then each sub-package has some wiring circuits to allow this crystal to play a new role, because the packaging technology is particularly a circuit. The signal chip is regarded as the internal musculoskeletal and circuit signals. The high-frequency electronic package with frequency and efficiency characteristics that can improve the performance and level of metal wiring is taken as an example. Sexual connection can achieve better electrical characteristics through signal bonding ground wire. Ground wire f noise and the effect of preventing signal coupling interference are usually used, so the use of cup line arrangement has become an innovation in semiconductor packaging technology. In some semiconductor chips, there is not enough ground wire to isolate or prevent the inductance between signals. Coupling phenomenon, therefore, a necessary line to accomplish this task.
IH 第5頁 1244189IH Page 5 1244189
'五、發明說明（2) 排列結構及其排列方法，：用；二：U片封裝體之銲線 合 訊號傳遞，利用電源銲線與訊號銲、線之間：：線的 方式，以及半導體晶片之銲墊盥封 f種不同的排列 擾，隔絕 ，一…全保護訊號銲線之 輪：2丨腳的排列 【發明内容】 本發明係揭露一種半導體封駐脚 卞等體封裝體之銲線配士 封裝體之訊號銲線的兩側，各署 ^ 直…構，在 丨』合配置一條電源銲線，— 訊號銲線，以完成雜訊隔離與電感麵合現象、' 匕圍 本發明揭露-種半導體封裝體之^配置 裝體之訊號銲線的兩側，各配置兩條電源鲜了構’在封 板之引腳係以兩兩相錯的方式進行排列使p —而封裝基 一組訊號銲線的兩側皆各包圍兩條電源銲線于:—條或每 線的上下左右皆有電源銲線作為屏壁，降低==號銲 的電感耦合現象。 ％ #線之間 本發明揭露一種半導體封裝體之銲線配置結 動訊號銲線組的兩側，各配置至少一條電源鲜〜# ’在差 組差動机5虎鲜線組至少兩條或以上的^源^線、 使件一 會有助於差動訊號銲線組的訊號傳遞，降低雜所包圍’將 少差動訊號線組之間的訊號干’擾。 、A干擾與減 本發明揭露一種半導體封裝體之銲線配置矣士 動訊號銲線組的兩側，各配置兩條電源銲線 構’在差 、、、，使得一組差'Fifth, the description of the invention (2) Arrangement structure and arrangement method: use; 2: U-chip package body wire and signal transmission, using power supply wire and signal welding, wire-to-wire: wire method, and semiconductor The solder pads of the chip are sealed in f different ways to isolate, and ... a wheel of the full-protection signal bonding wire: an arrangement of 2 feet [Summary of the Invention] The present invention discloses the welding of a semiconductor package such as a semiconductor package. The two sides of the signal bonding wire of the cable package package are each designed with a straight line, and a power bonding wire is combined with the signal bonding wire to complete the noise isolation and inductance surface bonding phenomenon. Disclosure of the Invention-A type of semiconductor package, two sides of the signal bonding wire of the package, two power sources are arranged on each side, and the pins on the package board are arranged in a staggered manner so that p-and the package Both sides of the base set of signal welding wires are surrounded by two power supply welding wires:-Each line has power supply welding wires as the screen wall, reducing the inductance coupling phenomenon of == number welding. % # Between the wires The present invention discloses a semiconductor package with a wire configuration configured on both sides of the signal bonding wire group, each of which is configured with at least one power supply. The above ^ source ^ lines and the first piece will help the signal transmission of the differential signal wire group, and reduce the interference of the signal interference between the differential signal wire groups. A, A interference and reduction The present invention discloses a solder package configuration for a semiconductor package. Two sides of a signal bonding wire group are provided with two power bonding wires, respectively.
第6頁 1244189 '五、發明說明（3) 動訊號銲線組至少有四條的電源銲線所包圍，將會使得每 一組差動汛5虎銲線組在上下左右的方向將被電源銲線所包 圍，有助於差動訊號銲線組的訊號傳遞，減少差動訊號銲 線組之間的電感耦合干擾。 【實施方式】 為了在封裝製程時，使訊號銲線間仍不會互相干擾， 且不會有訊號銲線與接地線互相接觸的情況發生。本發明 特別考慮在訊號銲線兩旁，以電源銲線加以包圍，且這些 電源銲線與訊號銲線一樣從半導體晶片連接至封裝基板^ 上，再由封裝基板上之引腳再短接至原本就用來耦接電源 之電源環。以同時達到使訊號銲線間不會互相干擾，且在 封裝製程時與封裝製程之後，訊號銲線與電源銲線間不會 有任何接觸。本發明揭露一種晶片封裝體之銲線排列結 構，至少一訊號銲線連接晶片與封裝基板上，並利用^少 兩條電源I于線’包圍訊號銲線的兩側，而電源銲線由晶片 連接至封裝基板。 ' % 請參考第一 A圖，此圖係顯示本發明之第一具體實施 例的俯視示意圖，於封裝基板丨〇〇之上安置半導體晶片 11，此半導體晶片11連接在封裝基板100的上表面，而且 在封裝基板100的上表面設置有接地環21與電源環31，在 接地環21與電源環31的外圍設置許多個引腳50。換言之， 接地環21與電源環31係設置在引腳50與半導體晶片丨丨的中 間。Page 6 1244189 'V. Description of the invention (3) The dynamic signal welding wire group is surrounded by at least four power welding wires, which will make each group of differential 5 tiger welding wire groups be welded by the power supply in the up, down, left and right directions. Surrounded by wires, it is helpful for the signal transmission of the differential signal bonding wire group and reduces the inductive coupling interference between the differential signal bonding wire group. [Embodiment] In order to ensure that the signal bonding wires do not interfere with each other during the packaging process, and that the signal bonding wires and the ground wire do not contact each other. In the present invention, it is particularly considered that the signal bonding wires are surrounded by power bonding wires, and these power bonding wires are connected from the semiconductor chip to the packaging substrate ^ as the signal bonding wires, and then the pins on the packaging substrate are shorted to the original It is used to couple the power supply ring. In order to prevent the signal bonding wires from interfering with each other at the same time, there is no contact between the signal bonding wires and the power bonding wires during and after the packaging process. The invention discloses a bonding wire arrangement structure of a chip package. At least one signal bonding wire is connected to the chip and the packaging substrate, and at least two power sources I are used to surround both sides of the signal bonding wire, and the power bonding wire is formed by the chip. Connected to the package substrate. '% Please refer to the first diagram A. This diagram is a schematic plan view showing a first embodiment of the present invention. A semiconductor wafer 11 is placed on the package substrate. The semiconductor wafer 11 is connected to the upper surface of the package substrate 100. Furthermore, a ground ring 21 and a power supply ring 31 are provided on the upper surface of the package substrate 100, and a plurality of pins 50 are provided on the periphery of the ground ring 21 and the power supply ring 31. In other words, the ground ring 21 and the power ring 31 are disposed between the pin 50 and the semiconductor wafer.
第7頁 '五、發明說明（4) 請繼續參閲第一A圖，在半導體晶片n上設置許多個 銲墊，這些銲墊包括電源銲線與訊號銲線用來將半導體 晶片11上的訊號傳輸到封裝基板〗〇〇，或者將印刷電路板 要傳輸至半導體晶片的訊號或電源，經由封裝基板丨〇〇的 引腳5 0以#線連接半導體晶片！ i上的銲墊彡到訊號傳 輸的目的。半導體晶片u的銲墊，包括電源銲墊ρι〜ρ4、 訊號鲜塾S1+、s卜、S2+、S2-、S3+、S3-、S4+盥S4-。這 些銲墊的排列方式係以兩兩交錯的方式進行排列、，換言 之，這些銲墊以兩排直線來進行排列，第一個銲墊排列在 第一條直線上時，則第二個銲墊排列在第二條直線上，使 Z有相鄰的銲塾都是兩兩相錯，如電源銲墊^與訊號鲜 墊S1 +係相錯開，不會排列在同一條直線之上；如 塾與訊號鋒塾S1-係相錯開，也不會排列在同一條^象 上。其中，訊號銲墊S1+與S1-係為差動訊號 、 (jiffyentiai signal)組，當其中一個銲墊傳輸訊號為1 Π另「巧銲墊的傳輸訊號一定為〇，使得連接這兩個 鲜墊的讯唬銲線所傳輸的訊號一定是相反，使得高頻電子 元件能夠有較好的訊號傳輸品質。其他的差動訊號組（例 = S2+與 S2-，S3+與 S3-，S4+與 S4-)也以同樣 傳輸訊號。 〜 請繼續參閱第一A圖，半導體晶片丨丨上的銲墊經由銲 線連接至封裝基板1〇〇上的相對應的引腳5〇，使得半導體 ^ =上的電子元件，能夠經由封裝基板1〇〇來傳輸訊號盘 供應電源。根據本發明的第一具體實施例，#裝基板ι〇〇 1244189 '五、發明說明（5) 一~·— 上的引腳50的排列方式，係排列在同一直線上，而連 “ 源銲塾之引腳5 0係以封裝基板的内部佈線來連接至 #妾電 板100上的電源環31。 、▲基 請參閱第一β圖，此圖係為第一A圖在AA，線的剖面 圖，顯示出銲線的排列方式，經由在半導體晶片丨丨上的俨 塾排列’銲線的排列將會是每一組差動訊號銲線（如s 1 f 與SI-)的兩側分別緊鄰一個電源銲線（如P1與”），這將使 得電源銲線將差動訊號銲線包圍起來。由於電源銲線具有 穩疋的吼號性質，與接地線同樣為直流訊號，因此在差動 訊號鮮線的兩側包圍電源銲線，將會有助於差動訊號銲線 組的訊號品質，避免兩個差動訊號組之間的訊號干擾與電 感耦合現象，對於高頻電子元件而言，將有效提供訊號傳 輸品質。 請參閱第二A圖，此圖顯示本發明之第二具體實施例 的俯視示意圖’在半導體晶片丨丨上的銲墊排列，係在每一 組差動訊號銲墊（例如S1 +與s 1 -)兩侧，分別緊鄰設置兩個 電源鋅墊’換言之，在差動訊號銲墊組的第一側緊鄰設置 兩個電源銲墊P1與P2，在差動訊號銲墊組的第二側緊鄰設 置兩個電源知墊p 3與p 4，使得每一組差動訊號組被四個電 源鲜塾或電源銲線所包圍。而訊號銲墊與電源銲墊經由銲 ^ 連接至在封裝基板1〇〇上的相對應引腳Μ之上。而在 半導體晶片11上的電源銲墊與訊號銲墊係以兩兩相錯的方 式進行排列，如本發明之第一具體實施例。而在本發明之 第二具體實施例之封裝基板1〇〇上的引腳50，亦以兩兩相(5) Description of the invention on page 7 (4) Please continue to refer to FIG. 1A. A plurality of bonding pads are provided on the semiconductor wafer n, and these bonding pads include a power bonding wire and a signal bonding wire for bonding the semiconductor wafer 11 The signal is transmitted to the package substrate, or the signal or power to be transmitted from the printed circuit board to the semiconductor chip is connected to the semiconductor chip through the pin 50 of the package substrate, with a # line! The pad on i is used for the purpose of signal transmission. The pads of the semiconductor wafer u include power pads p4 to p4, signals S1 +, sb, S2 +, S2-, S3 +, S3-, S4 + and S4-. These pads are arranged in a staggered manner. In other words, these pads are arranged in two straight lines. When the first pad is arranged on the first line, the second pad is arranged. Arranged on the second straight line, so that the adjacent welding pads of Z are staggered in pairs, such as the power pad ^ and the signal pad S1 + are staggered, and will not be arranged on the same straight line; such as 塾It is staggered with the signal front 塾 S1- series, and will not be arranged on the same image. Among them, the signal pads S1 + and S1- are a differential signal (jiffyentiai signal) group. When one of the pads transmits a signal of 1 and the other is “the transmission signal of a smart pad must be 0, so that the two fresh pads are connected. The signal transmitted by the signal wire must be the opposite, so that high-frequency electronic components can have better signal transmission quality. Other differential signal groups (eg = S2 + and S2-, S3 + and S3-, S4 + and S4- ) The same transmission signal. ~ Please continue to refer to the first A, the pad on the semiconductor wafer 丨 丨 is connected to the corresponding pin 50 on the packaging substrate 100 through the bonding wire, so that the semiconductor ^ = on the The electronic component can transmit power to the signal board through the package substrate 100. According to the first specific embodiment of the present invention, the #mount substrate ι〇〇1244189 'V. Description of the invention (5) Pins on ~~~ The arrangement of 50 is arranged on the same straight line, and the pin 50 of the "source welding pad" is connected to the power supply ring 31 on the # 妾 电 板 100 by the internal wiring of the package substrate. Please refer to the first β diagram for this picture. This diagram is a cross-sectional view of the first A diagram at line AA, showing the arrangement of the bonding wires. The arrangement of the bonding wires is arranged on the semiconductor wafer. There will be two sets of differential signal bonding wires (such as s 1 f and SI-) next to a power supply bonding wire (such as P1 and "), which will make the power supply welding wire surround the differential signal bonding wires. .Because the power wire has a stable roaring nature and is a DC signal like the ground wire, surrounding the power wire on both sides of the fresh signal wire will help the signal quality of the differential signal wire group. , To avoid signal interference and inductive coupling between two differential signal groups, for high-frequency electronic components, it will effectively provide signal transmission quality. Please refer to Figure A, which shows the second specific implementation of the present invention A schematic plan view of the example 'The pad arrangement on the semiconductor wafer is arranged on both sides of each set of differential signal pads (such as S1 + and s 1-), and two power zinc pads are provided next to each other'. In other words, in The first side of the differential signal pad set is placed immediately Two power supply pads P1 and P2, two power supply pads p 3 and p 4 are arranged next to the second side of the differential signal pad group, so that each group of differential signal pads is powered by four power supplies or power wires. The signal pads and the power pads are connected to the corresponding pins M on the package substrate 100 through soldering. The power pads and the signal pads on the semiconductor wafer 11 are in pairs. The phases are arranged in the wrong phase, as in the first specific embodiment of the present invention, and the pins 50 on the package substrate 100 of the second specific embodiment of the present invention are also in two phases.
1244189 五、發明說明（6) 錯的方式進行排列，使得連接銲墊與引腳的銲線，在相鄰 的兩條銲線具有長短不同的長度。1244189 V. Description of the invention (6) Arrange in the wrong way, so that the bonding wires connecting the pads and the pins have different lengths in the two adjacent bonding wires.
請參閱第二B圖，此圖係顯示第二A圖之AA，線的剖面 示意圖’一組差動訊號銲線（如S1 +與S1 -)被四條電源焊線 (PI、P2、P3、P4)以上下立體的方式所包圍，使得差動訊 號銲線組不只在直線方面被包圍，同時也在上下方向被電 源If*線所包圍。這樣的銲線配置方法，將更有效的保護訊 號銲線上的訊號傳遞，減少差動訊號銲線組之間的訊號干 擾與電感耦合效應，尤其對於高頻電子元件的訊號傳^ 更好的屏壁效果。 b 4 a上述，本發明提出一種半導體晶片封裝體的銲 配置結構，利用電源銲線包圍差動訊號線組或者是一般 號線’而使得訊號銲線能受到更完整的屏蔽保護。連:° 月更可使得封裝體内的録線迴路具有較低之：路 電感以及較佳之匹配阻抗。 〜纷 唯以上所述者，僅為本發明之較佳實 ^ ^ 之限制本發明的範圍。即大凡依本發 μ = 肐以 之均等變化及修飾，仍將不失本發明利㈣所做Please refer to the second diagram B. This diagram shows the cross-section of AA in the second diagram A. 'A set of differential signal bonding wires (such as S1 + and S1-) are four power bonding wires (PI, P2, P3, P4) Surrounded by the up and down three-dimensional manner, the differential signal bonding wire group is not only surrounded by a straight line, but also surrounded by a power source If * line at the same time. Such a bonding wire configuration method will more effectively protect the signal transmission on the signal bonding wire and reduce the signal interference and inductive coupling effects between the differential signal bonding wire groups, especially for the signal transmission of high-frequency electronic components. Wall effect. b 4 a. As mentioned above, the present invention proposes a soldering arrangement structure for a semiconductor chip package. The power supply wire is used to surround a differential signal wire group or a general signal wire, so that the signal wire can be more completely shielded and protected. Connection: ° Month can make the recording circuit in the package lower: circuit inductance and better matching impedance. The above are only the preferred embodiments of the present invention, and the scope of the present invention is limited. That is to say, all equal changes and modifications according to the present μ = will still be made without losing the benefits of the present invention.
=發明之精神和範圍’故都應視為本發明的= The spirit and scope of the invention ’should be considered as the invention
1244189 圖式簡單說明 【圖式簡單說明】 晶片 晶片 晶片 晶片 第一 A圖係顯示本發明之第一具體實施例，為半導體 封裝體之銲線排列結構的俯視示意圖； 第一B圖係顯示本發明之第一具體實施列，為半導體 封裝體之銲線排列結構的剖面示意圖； 第二A圖係顯示本發明之第二具體實施例，為半 封裝體之銲線排列結構的俯視示意圖；以及 _ 第二B圖係顯示本發明之第二具體實施例，為 封裝體之銲線排列結構的俯視示意圖。 等體 圖號說明： 1 0 0 -封裝基板 11 -半導體晶片 2 1 -接地環 31 -電源環 50-引腳 P1〜P4-電源銲墊 S4+與S4-訊號銲塾 si+、si—、S2+、S2—、S3+、S3 一1244189 Brief description of the drawings [Simplified description of the drawings] Wafer Wafer Wafer The first A diagram is a top view showing a first embodiment of the present invention, and is a schematic plan view of a bonding wire arrangement structure of a semiconductor package. The first embodiment of the invention is a schematic cross-sectional view of a bonding wire arrangement structure of a semiconductor package; FIG. 2A is a schematic plan view showing a second embodiment of the present invention, a bonding wire arrangement structure of a semi-package; and _ Second diagram B is a schematic plan view showing a second embodiment of the present invention, which is a bonding wire arrangement structure of a package. Equal body drawing number description: 1 0 0-package substrate 11-semiconductor wafer 2 1-ground ring 31-power ring 50-pins P1 ~ P4- power pads S4 + and S4- signal pads si +, si-, S2 +, S2—, S3 +, S3 a
第11頁Page 11
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| US8513708B2 (en) | 2007-05-25 | 2013-08-20 | Realtek Semiconductor Corp. | Integrated circuit for various packaging modes |
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| US8513708B2 (en) | 2007-05-25 | 2013-08-20 | Realtek Semiconductor Corp. | Integrated circuit for various packaging modes |
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