JPH0239866B2 - - Google Patents

Info

Publication number
JPH0239866B2
JPH0239866B2 JP58070558A JP7055883A JPH0239866B2 JP H0239866 B2 JPH0239866 B2 JP H0239866B2 JP 58070558 A JP58070558 A JP 58070558A JP 7055883 A JP7055883 A JP 7055883A JP H0239866 B2 JPH0239866 B2 JP H0239866B2
Authority
JP
Japan
Prior art keywords
bonding
bonding wire
electrode
container
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58070558A
Other languages
English (en)
Other versions
JPS59195856A (ja
Inventor
Masataka Mizukoshi
Teiichi Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58070558A priority Critical patent/JPS59195856A/ja
Priority to US06/601,360 priority patent/US4618879A/en
Priority to EP84400788A priority patent/EP0126664B1/en
Priority to DE8484400788T priority patent/DE3479271D1/de
Publication of JPS59195856A publication Critical patent/JPS59195856A/ja
Publication of JPH0239866B2 publication Critical patent/JPH0239866B2/ja
Granted legal-status Critical Current

Links

Classifications

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置とその製造方法にかかり、
特にワイヤボンデイング方法に関する。
(b) 従来技術と問題点 半導体装置はIC、LSIと益々高集積化されてお
り、それに伴つて半導体チツプ並びに半導体容器
も大型化されてきた。従つて、半導体チツプを半
導体容器に取りつけた後、両者の電極を接続する
ボンデイングワイヤ数も非常に増加し、LSIでは
200本にも及んでいる。
第１図は半導体装置の組立断面図を示してお
り、１は半導体チツプ１０上の接続パツド、２は
半導体容器２０上の接続電極で、通常ワイヤ３の
ボンデイングは先に接続パツド１にボンデイング
して立ち上り、そのまま空間を引つ張つて（矢印
方向）次いで外部リードに電気的に接続されてい
る接続電極２にボンデイングして立ち下り、ワイ
ヤを切断する方法が採られている。稀には、接続
電極２から接続パツド１にボンデイングする方法
も採られるが、それは特別な都合に限られる。
また、ワイヤは一般に直径20〜30μｍのアルミ
ニウム線又は金線が用いられており、ボンデイン
グ装置は自動化された装置である。
このようなボンデイング方法において、ワイヤ
数が増大してくるとワイヤは立ち上り部から空間
に浮かんで形成されるために、空間で相互に接触
しやすい状態になる。更に、半導体チツプが大き
くなつて半導体容器が大型化してくれば、配線ワ
イヤの長さも長くなるから上記空間での接触の機
会は益々増加し、また配線長さが長くなると、配
線容量が増えてそれだけ半導体装置の動作特性
（高速動作）に悪影響を与える。
(c) 発明の目的 本発明の目的は、半導体装置にとつて非常に重
要なこのような問題点を軽減させる製造方法を提
案するものである。
(d) 発明の構成 その目的は、半導体チツプと、それを収容する
容器と、該半導体チツプ上に形成された電極パツ
ドと、該容器の少なくとも上下２段に形成された
電極と、該電極パツド面に対して急峻な角度をも
つて接続された第１の立ち上り部と、前記容器の
上段に形成された電極面に対して前記第１の立ち
上り部よりもゆるやかな角度をもつて接続された
第１の立ち下り部とをもつ第１のボンデイングワ
イヤと、前記容器の下段に形成された電極面に対
して急峻な角度をもつて接続された第２の立ち上
り部と、前記電極パツド面に対して前記第２の立
ち上り部よりもゆるやかな角度をもつて接続され
た第２の立ち下り部とをもつ第２のボンデイング
ワイヤとを具備し、 互いに隣合う前記第１のボンデイングワイヤと
前記第２のボンデイングワイヤにおいて前記第１
のボンデイングワイヤの最高点より前記第２のボ
ンデイングワイヤの最高点が低く構成されている
半導体装置によつて達成される。
また、その製造方法は、半導体チツプ上の電極
パツドと、それを収容する容器の少なくとも上下
２段に形成された電極との間をボンデイングワイ
ヤで接続するに際し、隣合うボンデイングワイヤ
の一方は前記容器の下段に形成された電極を始点
として前記電極パツドへボンデイングし、且つ、
他方は前記電極パツドを始点とし最高点が前記一
方のボンデイングワイヤの最高点より高くなるよ
うにして前記容器の上段に形成された電極へボン
デイングし、隣合うボンデイングワイヤのワイヤ
ボンデイング方向が互いに逆方向になるようにボ
ンデイングを行なうものである。
(e) 発明の実施例 以下、図面を参照して実施例によつて詳細に説
明するが、上記の問題点を解決するためには、ま
ず、先立つて第２図および第３図に示すような構
造および方法が考えられる。即ち、第２図および
第３図は参考例を示しており、半導体チツプ１０
上の接続パツド１と半導体容器２０上の接続電極
２とを接続するボンデイングワイヤのボンデイン
グ方向は図中の矢印のように隣接する接続パツド
相互間および隣接する接続電極相互間をすべて反
対方向にする。図において、３ａは順方向のボン
デイングワイヤ（第１のボンデイングワイヤ）、
３ｂは逆方向のボンデイングワイヤ（第２のボン
デイングワイヤ）を示しており、このような配線
方法は自動ボンデイング装置によつて交互に順方
向と逆方向とに容易に行うことができる。
第３図はこのようにして配線したボンデイング
ワイヤの部分拡大図を示しており、第３図ａは断
面図、第３図ｂはその平面図である。ワイヤボン
デイングすると、初めにボンデイングした接続パ
ツド１または接続電極２の立ち上り部でボンデイ
ングワイヤが高く立ち上がり、それを矢印方向に
引つ張つてボンデングして立ち下がるから、空間
ではワイヤ相互を一層遠い間隔にすることができ
て、同じ方向（例えば順方向のみ）に引つ張つて
ボンデイングするよりも接触しにくくなる。それ
は本図によつて容易に理解されることである。
しかし、第２図および第３図に説明した構造お
よび方法では未だ不充分であるので、次に、接続
電極が高低を有する上下２段に設けられた半導体
容器を用いた本発明にかかる構造および方法につ
いて説明する。第４図は本発明によつてワイヤボ
ンデイングした組立平面図を示しており、半導体
容器２１の下段の接続電極２ｃと半導体チツプ１
１のチツプ周縁に近い接続パツド１ｃとを逆方向
にワイヤボンデイングし、半導体容器２１の上段
の接続電極２ｄと半導体チツプ１１のチツプ周縁
より遠い接続パツド１ｄとを順方向にワイヤボン
デイングする。第５図はその部分拡大図を示し、
第５図ａは断面図、第５図ｂは平面図である。こ
のようにワイヤボンデイングすると、空間でボン
デイングワイヤ相互をより遠ざけることが可能に
なり、更に、横からみて隣合うボンデイングワイ
ヤで重なつて見えるところがなく、ボンデイング
ワイヤが互いに接触することが全く起こらないよ
うにできる。
ここに、第５図に示している半導体チツプ１１
は接続パツドをチツプ周縁に近い接続パツド１ｃ
とチツプ周縁より遠い接続パツド１ｄとの二列に
形成しているが、現在では未だこのように接続パ
ツドは高密度には形成されていない。本発明によ
るワイヤボンデイング方法を行うことによつて、
初めて接触の心配が少なくなるから接続パツドを
二列にして密度を高くし、かくして半導体チツプ
を小さくし、更に半導体容器を小型化することが
できる。
ところで、アルミニウムワイヤを用いる場合に
は、ボンデイングツールはウエツジツールと呼ば
れるもので、順方向にボンデイングすると半導体
容器２０上の接続電極２形成面の面積を考慮する
必要がある。それは、その面積が狭いとウエツジ
ツールの後端が接続電極面の側壁に当たるため
で、そのために従来の順方向のボンデングでは接
続電極面を特に広くしていた。しかし、上記実施
例の下段のように逆方向にボンデイングすれば、
その接続電極面は更に狭くすることができて、一
層半導体容器の小型化に役立つ。なお、金ワイヤ
の場合は、キヤピラリーツールであるから、この
ような心配はない。
また、第５図ｃは第５図ａとは反対に上下段共
逆にボンデイングした参考例の断面図で、このよ
うにボンデイングしても空間ではワイヤの距離が
従来に比べて遠くなるから接触の問題は減少す
る。しかし、この第５図ｃでは横から見て隣合う
ボンデイングワイヤが重なるところができ、ボン
デイングワイヤが大きく傾くとボンデイングワイ
ヤが互いに接触することが起こる。
(f) 発明の効果 以上の実施例から判るように、本発明によれば
空間におけるボンデイングワイヤ相互の間隔を拡
げることができて、接触事故を減少させ、半導体
装置の信頼度を向上させることが出来る。
且つ、実装密度を高めて高集積化するメリツト
も大きく、半導体装置、更には電子回路の特性向
上に極めて寄与するものである。
【図面の簡単な説明】
第１図は従来の半導体装置の組立断面図、第２
図は参考例の組立平面図、第３図はその部分拡大
図で、第３図ａは断面図、第３図ｂはその平面
図、第４図は本発明にかかる実施例の組立平面
図、第５図はその部分拡大図、第５図ａは断面
図、第５図ｂはその平面図、第５図ｃは第５図ａ
とは逆にボンデイングした参考例の断面図であ
る。 図中、１，１ｃ，１ｄは接続パツド、２，２
ｃ，２ｄは接続電極、３，３ａ，３ｂはボンデイ
ングワイヤ、１０，１１は半導体チツプ、２０，
２１は半導体容器を示している。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体チツプと、 それを収容する容器と、 該半導体チツプ上に形成された電極パツドと、 該容器の少なくとも上下２段に形成された電極
    と、該電極パツド面に対して急峻な角度をもつて
    接続された第１の立ち上り部と、前記容器の上段
    に形成された電極面に対して前記第１の立ち上り
    部よりもゆるやかな角度をもつて接続された第１
    の立ち下り部とをもつ第１のボンデイングワイヤ
    と、前記容器の下段に形成された電極面に対して
    急峻な角度をもつて接続された第２の立ち上り部
    と、前記電極パツド面に対して前記第２の立ち上
    り部よりもゆるやかな角度をもつて接続された第
    ２の立ち下り部とをもつ第２のボンデイングワイ
    ヤとを具備し、 互いに隣合う前記第１のボンデイングワイヤと
    前記第２のボンデイングワイヤにおいて前記第１
    のボンデイングワイヤの最高点より前記第２のボ
    ンデイングワイヤの最高点が低く構成されてなる
    ことを特徴とする半導体装置。 ２ 上記電極パツドが上記半導体チツプ周縁部分
    に２列に設けられ、 上記第１のボンデイングワイヤが上記半導体チ
    ツプ周縁部分より遠い列の電極パツドに接続さ
    れ、且つ、上記第２のボンデイングワイヤが上記
    半導体チツプ周縁部分より近い列の電極パツドに
    接続されていることを特徴とする特許請求の範囲
    第１項記載の半導体装置。 ３ 半導体チツプ上の電極パツドと、それを収容
    する容器の少なくとも上下２段に形成された電極
    との間をボンデイングワイヤで接続するに際し、
    隣合うボンデイングワイヤの一方は前記容器の下
    段に形成された電極を始点として前記電極パツド
    へボンデイングし、且つ、他方は前記電極パツド
    を始点とし最高点が前記一方のボンデイングワイ
    ヤの最高点より高くなるようにして前記容器の上
    段に形成された電極へボンデイングし、隣合うボ
    ンデイングワイヤのワイヤボンデイング方向が互
    いに逆方向になるようにボンデイングを行なうこ
    とを特徴とする半導体装置の製造方法。
JP58070558A 1983-04-20 1983-04-20 半導体装置及びその製造方法 Granted JPS59195856A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP58070558A JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法
US06/601,360 US4618879A (en) 1983-04-20 1984-04-18 Semiconductor device having adjacent bonding wires extending at different angles
EP84400788A EP0126664B1 (en) 1983-04-20 1984-04-19 Wire bonding method for producing a semiconductor device and semiconductor device produced by this method
DE8484400788T DE3479271D1 (en) 1983-04-20 1984-04-19 Wire bonding method for producing a semiconductor device and semiconductor device produced by this method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58070558A JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法

Publications (2)

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JPS59195856A JPS59195856A (ja) 1984-11-07
JPH0239866B2 true JPH0239866B2 (ja) 1990-09-07

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JP58070558A Granted JPS59195856A (ja) 1983-04-20 1983-04-20 半導体装置及びその製造方法

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US (1) US4618879A (ja)
EP (1) EP0126664B1 (ja)
JP (1) JPS59195856A (ja)
DE (1) DE3479271D1 (ja)

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US5596171A (en) * 1993-05-21 1997-01-21 Harris; James M. Package for a high frequency semiconductor device and methods for fabricating and connecting the same to an external circuit
US5665649A (en) * 1993-05-21 1997-09-09 Gardiner Communications Corporation Process for forming a semiconductor device base array and mounting semiconductor devices thereon
EP0632493A1 (en) * 1993-06-30 1995-01-04 STMicroelectronics S.r.l. Semiconductor device with twice-bonded wire and method for manufacturing
US7084656B1 (en) 1993-11-16 2006-08-01 Formfactor, Inc. Probe for semiconductor devices
US7200930B2 (en) 1994-11-15 2007-04-10 Formfactor, Inc. Probe for semiconductor devices
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5814892A (en) * 1996-06-07 1998-09-29 Lsi Logic Corporation Semiconductor die with staggered bond pads
JPH1050750A (ja) * 1996-07-30 1998-02-20 Nec Kyushu Ltd 半導体装置およびその製造方法
US6090237A (en) * 1996-12-03 2000-07-18 Reynolds; Carl V. Apparatus for restraining adhesive overflow in a multilayer substrate assembly during lamination
JPH10308582A (ja) * 1997-05-07 1998-11-17 Denso Corp 多層配線基板
TW473882B (en) * 1998-07-06 2002-01-21 Hitachi Ltd Semiconductor device
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TWI242275B (en) * 2003-05-16 2005-10-21 Via Tech Inc Multi-column wire bonding structure and layout method for high-frequency IC
CN1332445C (zh) * 2003-10-09 2007-08-15 威盛电子股份有限公司 一种高频集成电路多排线打线结构
JP4206984B2 (ja) * 2004-07-29 2009-01-14 株式会社デンソー 角速度検出装置
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JP6227223B2 (ja) * 2012-03-30 2017-11-08 富士通テン株式会社 半導体装置、及び半導体装置の製造方法

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Also Published As

Publication number Publication date
US4618879A (en) 1986-10-21
DE3479271D1 (en) 1989-09-07
EP0126664A3 (en) 1986-01-22
EP0126664A2 (en) 1984-11-28
EP0126664B1 (en) 1989-08-02
JPS59195856A (ja) 1984-11-07

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