TW393745B - Manufacturing method of a semiconductor device and apparatus used to process epoxy encapsulation operation - Google Patents
Manufacturing method of a semiconductor device and apparatus used to process epoxy encapsulation operation Download PDFInfo
- Publication number
- TW393745B TW393745B TW087116822A TW87116822A TW393745B TW 393745 B TW393745 B TW 393745B TW 087116822 A TW087116822 A TW 087116822A TW 87116822 A TW87116822 A TW 87116822A TW 393745 B TW393745 B TW 393745B
- Authority
- TW
- Taiwan
- Prior art keywords
- resin
- cavity
- mold
- semiconductor device
- flip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
- B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/17—Component parts, details or accessories; Auxiliary operations
- B29C45/26—Moulds
- B29C45/34—Moulds having venting means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/29111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
五、發明説明^ ) 【發明之所屬技術領域】 本發明係關於倒裝片(flip-chip)型半導體裝置之樹 脂塡充者,特別是關於使用液狀樹脂之塡充方法。 【習知之技術】 將矽半導體等之半導體元件(以下,稱爲半導體晶片 )倒裝片式地連接於電路基板而構成之倒裝片型半導體裝 置爲所周知。倒裝片式連接係將作爲外部連接電極被安裝 之凸點(bump )電極或突起電極(以下,稱爲凸點)連接 於電路基板之連接方法。 經濟部中央標準局員工消費合作社印製 (讀先閱讀背面之注意事項再填湾本頁) 丁 圖16 (b)係習知之倒裝片型半導體裝置之剖面圖 。具備凸點3之半導體晶片2經由凸點3被連接於配線基 板1。在配線基板1之例如裡面形成連接電極(未圖示出 ),由被形成於半導體晶片2之積體電路來之信號或進入 此積體電路之信號進出外部電路地被構成。被安裝於半導 體晶片2之凸點3與被形成於配線基板1之連接電極係經 由被形成於配線基板1內部之內部配線(未圖示出)而電 氣地被連接著。此配線基板1與半導體晶片2之間,即凸 點3存在之空間係以樹脂封裝體5被保護著。依據習知之 技術之樹脂封裝體5之形成方法係以如下之工程進行之。 首先,在配線基板1之周邊,由分配噴嘴4 9供給環 氧樹脂等之液狀樹脂3 9。分配噴嘴4 9被安裝於儲存液 狀樹脂之注射器。液狀樹脂3 9利用毛細管現象之毛細管 力量滲透於配線基板1與半導體晶片2之間之內部(圖 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公楚) -4 - 五、發明説明g ) 15 (a))。即由分配噴嘴49來之液狀樹脂39被滴 下於配線基板1上之周邊(圖15 (b)),其滲透於內 部(圖16 (a))、形成樹脂封裝體5 (圖16 (b) 【發明欲解決之課題】 如上述般地,習知之倒裝片型半導體裝置之樹脂塡充 方法係在被倒裝片接合之半導體晶片之外周的1邊乃至3 邊之一部份,滴下液狀樹脂,將加熱軟化之樹脂利用毛細 管現象使之滲透於半導體晶片與配線基板之間隙。又’對 間隙之樹脂塡充終了後,爲了形成圓角’於預先沒有塗布 之2邊乃至4邊之一部份再度塗布液狀樹脂。此情形之樹 脂塗布工程所需要之時間,在塗布裝置以一台塡補之情形 ,不單是塗布時間,由半導體晶片外周於配線基板之間隙 塡充樹脂之時間也須合計,生產性低。 經濟部中央標準局員工消費合作社印製 又,適用於將半導體晶片搭載於導線架之元件搭載部 ,將被形成於半導體晶片之連接電極與導線架之導線以黏 線(wire bonding )連接之半導體裝置之樹脂封裝體,通常 以下注塑形法被形成。將被適用於此種半導體裝置之下注 塑形法適用於上述倒裝片型半導體裝置,半導體晶片與配 線基板之間隙爲0.2mm之程度,非常之小之故,塡充 不良產生以及成形時之樹脂黏度與塑膠封裝之黏度比較, 十分低乃引起樹脂之滲於四周,會有引起連不要樹脂塡充 之部份也附著之外觀不良之問題。上述半導體晶片與配線 本紙張尺度適用中國國家標率(CNS ) A4規格(210X297公釐) _ κ - Λ/ Λ/ 經濟部中央標準局員工消費合作社印製 五、發明説明$ ) 基板之間隙有變窄至0.01〜0.1mm之傾向,問題 更爲擴大。 本發明係鑑於此種情事而成者,在於提供:於半導體 晶片與配線基板之間隙樹脂封裝體均勻地短時間被形成之 倒裝片型半導體裝置之製造方法及此倒裝片型半導體裝置 之樹脂封裝體可以容易地被形成之樹脂封裝裝置。 【解決課題用之手段】 本發明係在倒裝片型半導體裝置之半導體晶片與配線 基板之間隙以及其之外周形成樹脂封裝體之樹脂塡充方法 ,其特徵爲:經由下注塑形或藉由螺桿加壓注入,使用收 容半導體晶片之成形模,由被設於加熱、減壓狀態下之成 形模之內部(模穴)之入口(澆口),藉由柱塞將液狀樹 脂押入塡充於模穴內。 又,本發明之樹脂封裝裝置之特徵爲具有:收容倒裝 片型半導體裝置之半導體晶片與配線基板,至少具有1個 之澆口之模穴被形成之成形模,以及使模穴成爲減壓狀態 之手段,以及使成形模昇溫之手段,以及具有將液狀樹脂 由澆口加壓注入之柱塞或螺桿之手段。 與圖1 5以及圖1 6所示之樹脂塡充法比較,在半導 體晶片與配線基板之間隙,樹脂封裝體均勻地被短時間內 形成。又,本發明之樹脂封裝裝置,在被設置複數之模穴 之情形,經由在成形模之外部設置彈性體可以成形模補正 配線基板之偏差,可以獲得均勻之靠模。又,藉由在配線 (锖先閲讀背面之注意事項再填寫本頁) .装. 訂 .•泉 本紙張尺度適用中國國家標準(CNS ) A4規将< 210X297公摄) -6-
五、發明説明# ) 基板上抵接彈性體,可以防止配線基板上之流出於不必要 之地方。再者,藉由在成形模之上模與下模之間,設置荷 重承受部,可以控制模穴厚度。 經满部中夹標準局員工消費合作社印製 【發明之實施型態】 以下,參考圖面說明發明之實施型態。 本發明之特徵爲:將至少1個之半導體晶片之凸點被 電氣地連接於被外端子被形成之配線基板之倒裝片型半導 體裝置搭載於被加熱、減壓狀態下之樹脂封裝用成形模, 在此減壓狀態之樹脂封裝用成形模藉由下注塑形方式加壓 注入樹脂,以將上述半導體晶片以及配線基板樹脂封裝之 。以下分別使用樹脂封裝成形模說明第1實施例以及第2 實施例。 首先,參考圖1至圖4說明第1實施例之半導體裝置 之製造方法以及藉由此方法被形成之倒裝片型半導體裝置 〇 圖1以及圖2係說明樹脂之塡充方法之樹脂封裝用成 形模之剖面圖,圖3係倒裝片型半導體裝置之剖面圖以及 平面圖,圖4係詳細說明使用於圖3之半導體裝置之配線 基板以及半導體晶片之部份剖面圖。 成形模係密閉上模(第1模)3 0以及下模(第2模 )3 2以形成收容半導體晶片等之被封裝體之模穴3 8。 在此實施例中,被封裝體之倒裝片型半導體裝置之配線基 板1以及被fe·載於此之半導體晶片2被收容著。接近模穴 (請先閱讀背面之注意事項再填寫本頁) l· Γ
L 本紙張尺度適用中國國家標準(CNS)A<l規格(210X297公t) 經濟部中央標準局員工消費合作社印製 _ 五、發明説明έ ) 38 ’排氣溝(排氣孔)36被形成於上模30。排氣溝 3 6係被形成於接近模穴3 8之一部份,例如4角落,在 排氣溝3 6之前端形成排氣溝以上之深度之偷料部5 0以 作爲切斷配線基板1之面之偷料部份。在下模3 2形成收 容熱硬化性之環氧樹脂等之液狀樹脂之孔口( port) 3 3 。孔口 3 3之中柱塞4 0可以進出自如地移動。由孔口 3 3至模穴3 8止,形成流道3 4、澆口 3 5與樹脂路徑 〇 於成形時,倒裝片型半導體裝置之半導體晶片2以及 配線基板1被置於成形模之例如下模32(圖1(a)) 。接著,被儲存於注射器(未圖示出)之液狀樹脂3 9藉 由分配噴嘴4 9 (參考圖15),利用空氣壓力適量地供 給於孔口 3 3。在成形模藉由模之閉合,於成形部形成模 穴(密閉空間)3 8。爲了使此模穴成爲高真空度空間, 在成形模周圍配置例如氟橡膠之減壓用封環3 7。減壓用 封環3 7爲了縮短真空到達時間,做成在完全模閉前上下 模間爲1 m m程度,即使保持數秒間之情形,也可以獲得 高真空度之構造。在進行成形時’最初在完全模閉前,使 模穴38成爲lOTo r r以下之高真空。而且,完全閉 合成形模。孔口 3 3之液狀樹脂3 9被押入柱塞40 ’通 過流道34,由澆口 35往模穴38移動(圖1 (b)) 。液狀樹脂3 9雖然在孔口 3 3內預先被供給有相當於適 量樹脂量之體積份以上之空間’但是使用之液狀樹脂之黏 度低之故,會有樹脂流出於孔口與柱塞之間隙。因此,爲 本紙張尺度適用中國國家標準(CNS) A4规格(21〇'乂297公赴) _8_ (誚先閱讀背面之注意事項再填本頁)
五、發明説明$ ) 了使孔口與柱塞之間隙儘可能地小,也可能在柱塞外周形 成相當於封環之鐵氟龍(Teflon)之環,以使柱塞外型合 於孔口內徑。當然最好做成環可以更換,在磨耗等產生時 可以快速地更換之構造。 往模穴3 8之樹脂注入口之澆口 3 5雖然被設於倒裝 片型半導體裝置外周之一部份,但是在形成於側面之情形 ,也有在半導體晶片2之1邊形成澆口之情形。又,爲了 防止在倒裝片型半導體裝置之配線基板1上,樹脂成形後 殘留之問題,也可以將澆口設置於半導體晶片上面部。 液狀樹脂3 9以1〜2 OMP a之程度被持續加壓( 圖2 ( a ))。加壓至液狀樹脂3 9沒有空隙(void )止 ,也確認在凸點存在之配線基板1與半導體晶片2之間被 均勻地塡充了樹脂後,才停止加壓(圖2 ( b ))。被注 入之樹脂被硬化,去除半導體晶片2被封裝之樹脂封裝體 4之多餘的樹脂,形成了倒裝片型半導體裝置。 藉由此樹脂塡充方法,在短時間內液狀樹脂可以均勻 地塡充於配線基板1與半導體晶片2之間、及凸點間。 經濟部中央標準局員工消費合作社印繁 接著,參考圖3說明經由上述方法被形成之倒裝片型 半導體裝置1 0。圖3 ( a )係半導體晶片2露出於半導 體裝置之上面之形式,圖3 ( c )係半導體晶片2被覆蓋 於樹脂封裝體4之中之形式,在圖1以及圖2記載之成形 模中,圖3 ( c )之形式之半導體裝置被形成。在配線基 板1上形成配線(未圖示出)爲半導體晶片2之連接端子 之凸點3被電氣地連接於該配線。配線基板1上之半導體 -9 - 本紙張尺度適用中國國家梯準(CNS ) Λ4規格(210X297公釐) 五'發明説明f ) 晶片1與凸點3被環氧樹脂等之樹脂封裝體4完全地覆蓋 ’配線基板1之表面之一部份也被樹脂封裝體4覆蓋。 如圖3 ( a )所示般地,配線基板1與半導體晶片2 之間隙d,即凸點3間也均勻地被形成。配線基板與半導 體晶片之間隙d即使在0 . 2 m m以下,凸點間被樹脂均 勻地塡充。又,隨著半導體裝置之小型化,配線基板與半 導體晶片之間隙即使成爲〇.01〜0.1mm之程度, 使用此方法也可以均勻地塡充樹脂。 經濟部中央標準局員工消費合作社印製 接著,參考圖4更詳細說明倒裝片型半導體裝置之半 導體晶片與配線基板之狀態。具備凸點3之半導體晶片2 經由凸點3被連接於配線基板1。鋁等之連接電極2 1被 形成於半導體晶片2之主面。在主面之連接電極2 1被形 成之領域以外藉由氧化膜等之鈍化膜2 2被覆蓋保護著。 在連接電極2 1之表面形成銅等之電鍍膜3 1,在其上連 接由P b _ S b焊錫形成之凸點3。另一方面,在配線基 板1之表面形成配線1 1,其之外藉由光阻膜1 4被覆蓋 。在配線基板1之裡面形成連接電極1 3,連接電極1 3 經由被形成於配線基板1之內部之銅等之內部配線1 2, 與主面之配線1 1電氣地連接。也可以在連接電極1 3裝 置凸點。上述凸點3被連接於配線1 1,由被形成於半導 體晶片2之積體電路來之信號或進入此積體電路之信號由 連接電極13進出外部電路地被構成之。 如本發明之藉由下注塑料方式以形成樹脂封裝體,在 圖1 5所示之習知之技術中,將液狀樹脂塗布於1個之基 -10 - (誚先閱讀背面之注意事項再功5ΐτ本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公t ) 經濟部中央標準局員工消費合作社印製 __—_ jr 五、發明説明§ ) 板至形成未塡滿(underfill )止必須1分鐘,但在如本發 明之利用下注塑料方式之樹脂封裝體之形成方法中,只需 其一半程度之時間即可以同時地形成複數的半導體裝置。 接著,參考圖5以及圖6說明第2實施例之半導體裝 置之製造方法。 圖5以及圖6皆係說明樹脂之塡充方法之樹脂封裝用 成形膜之剖面圖。成形模係密閉上膜(第1膜)3 0以及 下膜(第2膜)32以形成收容半導體晶片以及搭載半導 體晶片之配線基板之模穴3 8。在此實施例中,倒裝片型 半導體裝置支配線基板1以及被搭載於此之半導體晶片2 被收容著。排氣溝接近模穴3 8被形成於上膜3 0。在此 成形膜有複數之模穴3 8,排氣溝被形成於此模穴間。而 且,排氣閥4 1被配置於排氣溝。在下膜3 2形成環氧樹 脂等之液狀樹脂被收容之孔口 3 3。柱塞4 0在孔口 3 3 中可以出入自如地移動。由孔口 3 3至模穴3 8形成流道 34、澆口35與樹脂路徑。 於成形時,倒裝片型半導體裝置之半導體晶片2以及 配線基板1被置於成形膜之下膜32 (圖5 (a))。接 著,將被儲存於注射器(未圖示出)之液狀樹脂3 9經由 分配噴嘴,利用空氣壓力被適量地供給於孔口 3 3。在成 形膜藉由膜閉合在成形部形成模穴3 8。爲了使此模穴 3 8成爲高真空度空間,在成形模周圍配置例如氟橡膠之 減壓用封環3 7。此封環3 7爲了縮短真空到達時間,做 成在完全模閉前上下模間爲1 m m程度,即使保持數秒間 本ί氏張尺度適用中國國家摞準(CNS ) A4規格(210X297公- 11 -— (誚先閱讀背面之注意事項再填寫本頁) Γ 裝.
、eT 、泉 經濟部中央標準局員工消費合作社印聚 ____ in 五、發明説明$ ) 之情形,也可以獲得高真空度之構造。 在完全膜閉合前使模穴3 8成爲1 Ο τ 0 r r以下之 高真空。而且’完全閉合成形膜。此時,排氣閥4 1阻止 孔口 3 3與流道3 4之間之樹脂通路(圖5 ( b ))。孔 口 3 3之液狀樹脂3 9受柱塞4 0之壓,將排氣閥4 1上 頂密封住排氣溝。而且,液狀樹脂3 9通過流道3 4,由 澆口35往模穴38移動(圖6 (a))。液狀樹脂39 雖然在孔口 3 3內預先被供給有相當於適量樹脂量之體積 份以上之空間,但是使孔口與柱塞之間隙儘可能小之故, 也可能在柱塞外周形成相當於封環之鐵氟龍(Teflon)之 環,以使柱塞外型合於孔口內徑。當然最好做成環可以更 換,在磨耗等產生時可以快速地更換之構造。 往模穴3 8之樹脂注入口之澆口 3 5雖然被設於倒裝 片型半導體裝置外周之一部份,但是在形成於側面之情形 ,也有在半導體晶片2之1邊形成澆口之情形。又,爲了 防止在倒裝片型半導體裝置之配線基板1上,樹脂成形後 殘留之問題,也可以將澆口設置於半導體晶片上面部。 液狀樹脂3 9以1〜2 OMP a之程度被持續加壓。 加壓至液狀樹脂3 9沒有空隙止,也確認在凸點存在之配 線基板1與半導體晶片2之間被均勻地塡充了樹脂後,才 停止加壓(圖6 ( b ))。之後,被注入之樹脂被硬化, 去除半導體晶片2被封裝之樹脂封裝體4之多餘的樹脂, 形成了倒裝片型半導體裝置。 藉由此樹脂塡充方法,在短時間內液狀樹脂可以均勻 (請先閱讀背面之注意事項再填寫本頁) •Γ 裝.
、1T 丨^ • LH .^ϋ It · 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公t ) -12- 五、發明説明彳〇 ) 經濟部中央標準局貝工消費合作社印製 地塡充於配線基板1與半導體晶片2之間、及凸點間。 接著,參考圖7說明第3實施例。 圖7係被使用於半導體裝置之製造方法之樹脂封裝用 成形膜之剖面圖。此實施例在成形膜之構造上有特徵,孔 口等之樹脂流路部份以及排氣部份之圖示被省略。在此成 形膜中,形成沒有被塗布厚的塗層之樹脂封裝體之圖3 ( a)所示的薄的倒裝片型半導體裝置。 成形膜係密閉上模(第1模)3 0以及下模(第2模 )3 2以形成收容半導體晶片等之被封裝體之複數的模穴 3 8。在此實施例中,被封裝體之倒裝片型半導體裝置之 配線基板1以及被搭載於此之半導體晶片2被收容著。上 膜3 0被第1保持器4 4保持著,下膜3 2被第2保持器 保持著。 於成形時,倒裝片型半導體裝置之半導體晶片2以及 藉由凸點3半導體晶片2被連接著之配線基板1被置於成 形模之下模3 2。在成形模藉由模之閉合,於成形部形成 模穴(密閉空間)3 8。爲了使此模穴成爲高真空度空間 ,在第1以及第2保持器44、4 5之周圍配置氟橡膠等 之減壓用封環4 3。此封環4 3爲了縮短真空到達時間, 做成在完全模閉前上下模間爲1 mm程度,即使保持數秒 間之情形,也可以獲得高真空度之構造。在進行成形時, 最初在完全模閉前,使模穴38成爲lOTo r r以下之 高真空。之後,完全閉合成形膜往模穴3 8注入液狀樹脂 (請先閱讀背面之注意事項再填寫本頁)
T 裝_ 訂 本紙張尺度適用中國國家標準(CNS > Λ4規格(210X297公釐〉 -13 - 經濟部中央標準局員工消費合作社印黎 A" ]Γ Γ η | | -------I ι·* ... » . .一•一 .. _| ·ι· _—·* ... ·--«,-“· >» 1 1 Ι· 五、發明説明彳1 ) 在下膜3 2之模穴3 8沒有形成之領域設置突起部 4 2,使其抵接於上模3 0。此突起部4 2係荷重承受部 ,抑制對配線基板之過負荷,可以控制模穴3 8之厚度。 接著,參考圖8說明第4實施例。 圖8係被使用於半導體裝置之製造方法之樹脂封裝用 成形膜之剖面圖。此實施例在成形膜之構造上有特徵,孔 口等之樹脂流路部份以及排氣部份之圖示被省略。在此成 形膜中,形成沒有被塗布厚的塗層之樹脂封裝體之半導體 晶片露出之圖3 ( a )所示的薄的倒裝片型半導體裝置。 成形膜係密閉上模(第1模)3 0以及下模(第2模 )3 2以形成收容半導體晶片等之被封裝體之複數的模穴 3 8。在此實施例中,被封裝體之倒裝片型半導體裝置之 配線基板1以及被搭載於此之半導體晶片2被收容著。上 膜3 0被第1保持器4 4保持著,下膜3 2被第2保持器 保持著。 於成形時,倒裝片型半導體裝置之半導體晶片2以及 藉由凸點3半導體晶片2被連接著之配線基板1被置於成 形模之下模3 2 »在成形模藉由模之閉合,於成形部形成 模穴(密閉空間)3 8。爲了使此模穴成爲高真空度空間 ,在第1以及第2保持器44、4 5之周圍配置氟橡膠等 之減壓用封環4 3。此封環4 3爲了縮短真空到達時間, 做成在完全模閉前上下模間爲1 mm程度,即使保持數秒 間之情形,也可以獲得高真空度之構造。 在進行成形時,最初在完全模閉前,使模穴3 8成爲 (讀先閱讀背面之注意事項再填寫本莨) Γ 裝· 丁 --0 • LI m Lr 本紙張尺度適用中國國家標车(CNS ) A4規格(210X297公釐〉 -14- 五、發明説明彳2 ) 1 OTo r r以下之高真空。而且,完全閉合成形膜往模 穴3 8注入液狀樹脂》在下膜3 2之模穴3 8沒有形成之 領域設置突起部4 2,使其抵接於上模3 0。此突起部 4 2係荷重承受部,抑制對配線基板之過負荷,可以控制 模穴3 8之厚度。 在此實施例之成形模中,其特徵爲:在與上模3 0之 配線基板1接觸部份設置氟橡膠等之第1彈性體4 6,在 上模3 0之上部設置氟橡膠等之第2彈性體4 7。第1彈 性體4 6係爲了防止往配線基板1之不必要的液狀樹脂之 流出而形成,第2彈性體4 7係爲了以成形模補正配線基 板1之偏差以獲得均勻之靠模而形成。 接著,參考圖9以及圖1 0說明第5實施例。 經濟部中央標準局員工消費合作社印製 圖9以及圖11係被使用於半導體裝置之製造方法之 樹脂封裝用成形模之模穴以及澆口之位置關係剖面圖。此 實施例之特徵在於成形模之模穴與澆口之配置。澆口 3 5 係使液狀樹脂由孔口通過流道以供給於模穴之入口。利用 習知之下注塑料方式係被搭載於導線架之半導體裝置。此 以下注塑料形成此半導體裝置之樹脂封裝體上,必須在搭 載導線架之樣子下收容於成形模。此情形,在模穴之周邊 由於導線架存在之故,澆口位置及大小有限制。在本發明 中,不利用導線架之故,液狀樹脂在均勻狀態下被注入模 穴地,可以將任意數目之澆口配置於任意之位置。圖皆係 顯示被配置於半導體晶片2被收容之模穴3 8之澆口 3 5 之狀態。如圖示般地,澆口以可以形成於半導體晶片之上 -15- 本紙張尺度適用中國國家標準(CNS ) A4規掊(210X297公1 ) 經濟部中央標準局員工消費合作社印製 ___ ΙΓ 五、發明説明彳3 ) 面。澆口之長度適當爲設定成晶片周長之5〜9 5%。 接著,參考圖1 0以及圖1 2說明第6實施例。 圖10以及圖12係被使用於半導體裝置之製造方法 之樹脂封裝用成形模之模穴以及排氣溝之位置關係剖面圖 。此實施例之特徵在於成形模之模穴與排氣溝之配置。在 本發明中,使模穴3 8成爲減壓狀態以成形之故,排氣溝 3 6很重要。排氣溝3 6例如接近模穴3 8之4角落被形 成。與澆口同樣地被形成於模穴3 8之周圍。在本發明中 ,如果不在澆口之上配置排氣溝3 6,排氣溝3 6可以在 均勻狀態使模穴成爲減壓狀態地,可以將任意數目、任意 大小之澆口配置於任意之位置。圖也都是顯示被配置於半 導體晶片2被收容之模穴3 8之排氣溝3 6之狀態。 接著,參考圖13說明第7實施例。 圖13係說明樹脂之塡充方法之樹脂封裝用成形模之 剖面圖。成形膜係密閉上模(第1模)3 0以及下模(第 2模)3 2以形成收容半導體晶片以及搭載半導體晶片之 配線基板之模穴3 8。排氣溝接近模穴3 8被形成於上模 3 0。在排氣溝之前端形成排氣溝以上之深度的偷料部 5 0以作爲切斷配線基板1之面之偷料部。在排氣溝被配 置有排氣閥5 1,液狀樹脂在被注入模穴3 8時,排氣閥 5 1封住排氣溝地構成之。在下模3 2形成環氧樹脂等之 液狀樹脂被收容之孔口 33。孔口 33之中,柱塞40可 以進出自如地移動。由孔口 3 8至模穴3 8形成流道、澆 口及樹脂路徑。 {"先聞讀背面之注意事項再填寫本頁} -裝· 、1T. '泉 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公t ) -16- 經濟部中央標率局貝工消費合作社印製 to. \v *·· 1 1 ι·ι I —I «·» . . . · . >. ^, - ·ι . , , 五、發明説明Η ) 成形時,半導體晶片2以及配線基板1被置於成形模 之下模3 2。半導體晶片2被配置於極爲接近上模之內面 之故,不會形成過厚之塗層,而形成圖3 ( a )所示之半 導體裝置。在成形膜藉由膜閉合在成形部形成模穴3 8。 爲了使此模穴3 8成爲高真空度空間,在成形模周圍配置 氟橡膠等之減壓用封環3 7。此封環3 7爲了縮短真空到 達時間,做成在完全模閉前上下模間爲1 m m程度,即使 保持數秒間之情形,也可以獲得高真空度之構造。進行成 形時,最初在完全膜閉合前使模穴3 8成爲1 Ο T 〇 r r 以下之高真空(圖13 (a))。而且,完全閉合成形膜 (圖13 (b))。以下,樹脂注入工程與之前之實施例 相同。 接著,參考圖1 4說明第8實施例。 圖14係說明樹脂之塡充方法之樹脂封裝用成形模之 剖面圖。此成形模與圖5係同樣之構造,排氣溝與排氣閥 4 1被形成於模穴3 8之間。 成形時,半導體晶片2以及配線基板1被置於成形模 之下模3 2。半導體晶片2被配置於極爲接近上模之內面 之故,不會形成過厚之塗層,而形成圖3 ( a )所示之半 導體裝置。在成形膜藉由膜閉合在成形部形成模穴3 8 » 爲了使此模穴3 8成爲高真空度空間,在成形模周圍配置 氟橡膠等之減壓用封環3 7。此封環3 7爲了縮短真空到 達時間,做成在完全模閉前上下模間爲1 m m程度,即使 保持數秒間之情形’也可以獲得高真空度之構造。進行成 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297'>T1 ) 「17- ;--「^-- ("先閱讀背面之注意事項再填寫本頁) 訂 '東 .L·. 1 lb 經濟部中央標準局貝工消費合作社印家 h' ____ in - --— -- I I . . —. •一. - * _— - - . ._ _ ,·ι M,—_ 五、發明説明p ) 形時’最初在完全膜閉合前使模穴38成爲1 OTo r r 以下之高真空(圖14 (a))。而且,完全閉合成形膜 (圖14(b))。以下,樹脂注入工程與之前之實施例 相同。 以上,藉由本發明之樹脂塡充方法在短時間內,液狀 樹脂即使在配線基板與半導體晶片之間隙爲0 . 2 m m以 下,也可以在凸點間均勻地塡充樹脂。特別是隨著半導體 裝置之小型化之進展,配線基板與半導體晶片之間隙即使 成爲0.01〜0.1mm之程度也可以充分地應對。 本發明並不限定於上述實施例,包含製造倒裝片型裝 置之種種製造方法以及樹脂封裝裝置。例如,在上述實施 例中,雖然說明了將上述液狀樹脂於上述模穴內藉由柱塞 加壓注入之方法,但在本發明也可以使用經由螺桿加壓注 入之方法(參考圖17)。 【發明之效果】 如上述般地,依據本發明與習知者比較,於短時間內 液狀樹脂可以均勻地塡充於配線基板與半導體晶片之微細 的間隙中。 【圖面之簡單說明】 圖1係說明本發明之樹脂塡充方法之樹脂封裝用成形 模之剖面圖。 圖2係說明本發明之樹脂塡充方法之樹脂封裝用成形 (請先閲讀背面之注意事項再"寫本頁 裝· 訂 '年 本紙張尺度適用中國國家梯準(CNS M4規格(210Χ25Π公釐) -18- 五、發明説明(!6 ) 模之剖面圖。 圖3係本發明之倒裝片型半導體裝置之剖面圖以及平 面圖。 圖4係詳細說明圖3使用之板導體裝置之配線基板以 及半導體晶片之部份剖面圖。 圖5係說明本發明之樹脂塡充方法之樹脂封裝用成形 模之剖面圖。 圖6係說明本發明之樹脂塡充方法之樹脂封裝用成形 模之剖面圖。 圖7係被使用於本發明之半導體裝置之製造方法之樹 脂封裝用成形模之剖面圖。 圖8係被使用於本發明之半導體裝置之製造方法之樹 脂封裝用成形模之剖面圖。 圖9係被使用於本發明之半導體裝置之製造方法之樹 脂封裝用成形模之模穴與澆口之位置關係剖面圖。 /圖1 0係被使用於本發明之半導體裝置之製造方法之 樹脂封裝用成形模之模穴與排氣溝之位置關係剖面圖。 經濟部中央標準局貝工消費合作社印家 圖11係被使用於本發明之半導體裝置之製造方法之 樹脂封裝用成形模之模穴與澆口之位置關係剖面圖。 圖12係被使用於本發明之半導體裝置之製造方法之 樹脂封裝用成形模之模穴與排氣溝之位置關係剖面圖。 圖13係說明本發明之樹脂塡充方法之樹脂封裝用成 形模之剖面圖。 圖14係說明本發明之樹脂塡充方法之樹脂封裝用成 -19- 本紙張尺度適用中國國家標準(CNS ) A4规格(210 X 297次t ) A Η 7 圖 明S 説0 明之 發模 、 形 五 經濟部中央標準局員工消費合作社印製 圖15係說明習知之樹脂塡充方法之半導體裝置之剖 面圖。 圖1 6係說明習知之樹脂塡充方法之半導體裝置之剖 面圖。 圖17係被使用於本發明之樹脂塡充方法之樹脂封裝 用成形模之模型剖面圖。 【標號之說明】 1:配線基板、 2 :板導體晶片、 3 :凸點、 4、5 :樹脂封裝體 10:倒裝片型半導體裝置、 1 1 :配線、 1 2 :內部配線、 13:連接電極 1 4 :光阻膜、 21:連接電極、 2 2 :鈍化膜、 3 0 :上膜、 31:電鍍膜 3 2 :下膜、 3 3 :孔口、 (請先閲讀背面之注意事項再填寫本頁 -裝' 訂 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公t ) - 20 - 五、發明説明彳8 ) 、 部 環 受 封 、承 用 閥重、 、 、 、 壓 、 氣荷器器體體、 、減 脂 排丨持持性性嘴 、、溝:、樹、··部保保彈彈噴部 道口氣 3 穴狀塞 1 起 1212 配料 流澆排 4 模液柱 5 突第第第第分偷 '·# '·····'_ _··_···· 456789012456790 333333444444445 經濟部中央標準局員工消費合作社印掣 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -21 -
Claims (1)
- 經濟部中央標準局貝工消費合作社印装 A8 B8 C8 _ D8六、申請專利範圍 1 · 一種半導體裝置之製造方法,其特徵爲具備: 將至少1個之半導體元件經由其之凸點電極被電氣地 連接於具有外部端子之配線基板之倒裝片型半導體裝置搭 載於樹脂封裝用成形膜之工程, 以及在上述半導體裝置被搭載之樹脂封裝用成形模, 將樹脂藉由下注塑料成形加壓注入以將上述半導體元件及 配線基板樹脂封裝之工程。 2 .如申請專利範圍第1項記載之半導體裝置之製造 方法,其中更加上:於上述樹脂封裝用成形模加壓注入樹 脂之前,將上述半導體裝置被搭載之樹脂封裝用成形模加 熱之工程,以及使上述被加熱之樹脂封裝用成形模內部成 爲減壓狀態之工程。 3 .如申請專利範圍第1或第2項記載之半導體裝置 之製造方法,其中上述被加壓注入之樹脂爲液狀樹脂。 4 . 一種樹脂封裝裝置,其特徵爲具備: 收容至少1個之半導體元件經由其之凸點電極被電氣 地連接於具有外部端子之配線基板之倒裝片型半導體裝置 ,而且以第1模與第2模被形成之模穴, 以及液狀樹脂被注入於上述模穴內之樹脂注入口, 以及使上述模穴內爲減壓狀態之手段, 以及加熱上述第1以及第2模之手段, 以及將上述液狀樹脂藉由柱塞加壓注入或藉由螺桿加 壓注入上述模穴內之手段。 5 .如申請專利範圍第4項記載之樹脂封裝裝置,其 (請先閲讀背面之注意事項再填寫本頁)本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公釐) -22 - 經濟部中央揉準局男工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 中上述樹脂注入口係複數地形成於上述模穴周圍之任意位 置。 6 .如申請專利範圍第5項記載之樹脂封裝裝置,其 中上述模穴平面形狀實質上爲矩形,上述樹脂注入口係被 形成於上述模穴之1整邊。 7 .如申請專利範圍第4項記載之樹脂封裝裝置,其 中更具有將上述模穴內排氣之排氣手段,在塡充液狀樹脂 前使上述模穴成爲減壓狀態。 8 .如申請專利範圍第7項記載之樹脂封裝裝置,其 中在上述第1以及第2模設置排氣閥,在使上述模穴內成 爲減壓狀態時,打開此排氣閥以使上述模穴內排氣,在塡 充液狀樹脂時,使上述排氣閥關閉。 9 .如申請專利範圍第4項記載之樹脂封裝裝置,其 中於上述模穴內,使彈性體接觸上述半導體元件被配置之 領域之上述配線基板。 1 0 .如申請專利範圍第4項記載之樹脂封裝裝置, 其中上述模穴被複數設置,在構成上述模穴之上述第1模 或第2模之外表面,設置補正配線基板之偏差,進行均勻 靠模之彈性體。 (請先閲讀背面之注意事項再填寫本頁) Γ 本紙張尺度逋用中國國家標準(CNS ) A4規格(210X297公釐) -23-
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9299403A JPH11121488A (ja) | 1997-10-15 | 1997-10-15 | 半導体装置の製造方法及び樹脂封止装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW393745B true TW393745B (en) | 2000-06-11 |
Family
ID=17872116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087116822A TW393745B (en) | 1997-10-15 | 1998-10-09 | Manufacturing method of a semiconductor device and apparatus used to process epoxy encapsulation operation |
Country Status (4)
Country | Link |
---|---|
US (1) | US5998243A (zh) |
JP (1) | JPH11121488A (zh) |
KR (1) | KR100320776B1 (zh) |
TW (1) | TW393745B (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI619988B (zh) * | 2015-12-16 | 2018-04-01 | Omron Tateisi Electronics Co | 電子裝置及其製造方法 |
WO2020133169A1 (zh) * | 2018-12-28 | 2020-07-02 | 瑞声精密制造科技(常州)有限公司 | 一种模具 |
CN113276359A (zh) * | 2020-02-19 | 2021-08-20 | 长鑫存储技术有限公司 | 注塑模具及注塑方法 |
Families Citing this family (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6228688B1 (en) * | 1997-02-03 | 2001-05-08 | Kabushiki Kaisha Toshiba | Flip-chip resin-encapsulated semiconductor device |
US6001672A (en) | 1997-02-25 | 1999-12-14 | Micron Technology, Inc. | Method for transfer molding encapsulation of a semiconductor die with attached heat sink |
JP3578262B2 (ja) * | 1999-04-06 | 2004-10-20 | 日東電工株式会社 | 半導体チップの樹脂封止方法及びその方法に使用する離型フィルム |
JP3417879B2 (ja) * | 1999-07-05 | 2003-06-16 | 沖電気工業株式会社 | モールド金型 |
US6413801B1 (en) * | 2000-05-02 | 2002-07-02 | Advanced Semiconductor Engineering, Inc. | Method of molding semiconductor device and molding die for use therein |
US6916683B2 (en) * | 2000-05-11 | 2005-07-12 | Micron Technology, Inc. | Methods of fabricating a molded ball grid array |
US6589820B1 (en) * | 2000-06-16 | 2003-07-08 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US6365434B1 (en) | 2000-06-28 | 2002-04-02 | Micron Technology, Inc. | Method and apparatus for reduced flash encapsulation of microelectronic devices |
KR100583496B1 (ko) * | 2000-08-14 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지용 회로기판 |
US6483044B1 (en) | 2000-08-23 | 2002-11-19 | Micron Technology, Inc. | Interconnecting substrates for electrical coupling of microelectronic components |
US6979595B1 (en) | 2000-08-24 | 2005-12-27 | Micron Technology, Inc. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
US6838760B1 (en) | 2000-08-28 | 2005-01-04 | Micron Technology, Inc. | Packaged microelectronic devices with interconnecting units |
US6838319B1 (en) * | 2000-08-31 | 2005-01-04 | Micron Technology, Inc. | Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically |
US6632704B2 (en) * | 2000-12-19 | 2003-10-14 | Intel Corporation | Molded flip chip package |
US20020110956A1 (en) * | 2000-12-19 | 2002-08-15 | Takashi Kumamoto | Chip lead frames |
FR2820240B1 (fr) * | 2001-01-26 | 2004-07-16 | St Microelectronics Sa | Substrat support de puce a circuits integres adapte pour etre place dans un moule |
US6486554B2 (en) | 2001-03-30 | 2002-11-26 | International Business Machines Corporation | Molded body for PBGA and chip-scale packages |
US7220615B2 (en) | 2001-06-11 | 2007-05-22 | Micron Technology, Inc. | Alternative method used to package multimedia card by transfer molding |
US6444501B1 (en) | 2001-06-12 | 2002-09-03 | Micron Technology, Inc. | Two stage transfer molding method to encapsulate MMC module |
CA2350747C (en) * | 2001-06-15 | 2005-08-16 | Ibm Canada Limited-Ibm Canada Limitee | Improved transfer molding of integrated circuit packages |
KR100418428B1 (ko) * | 2001-08-07 | 2004-02-11 | 서화일 | 집적회로의 언더필 인캡슐레이션 장치 및 방법 |
US6555400B2 (en) * | 2001-08-22 | 2003-04-29 | Micron Technology, Inc. | Method for substrate mapping |
JP2003077946A (ja) * | 2001-08-31 | 2003-03-14 | Hitachi Ltd | 半導体装置の製造方法 |
DE10156386B4 (de) * | 2001-11-16 | 2007-08-09 | Infineon Technologies Ag | Verfahren zum Herstellen eines Halbleiterchips |
DE10159522A1 (de) * | 2001-12-05 | 2003-06-26 | G L I Global Light Ind Gmbh | Verfahren zur Herstellung von LED-Körpern |
KR100400496B1 (ko) * | 2001-12-13 | 2003-10-08 | 서화일 | 멀티 플립칩의 언더필 인캡슐레이션 공정용 몰드 |
DE10242947B8 (de) * | 2002-09-16 | 2009-06-18 | Odelo Led Gmbh | Verfahren zum Herstellen von LED-Körpern mit Hilfe einer Querschnittsverengung und Vorrichtung zur Durchführung des Herstellungsverfahrens |
US20040178514A1 (en) * | 2003-03-12 | 2004-09-16 | Lee Sang-Hyeop | Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method |
JP4243177B2 (ja) | 2003-12-22 | 2009-03-25 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7098082B2 (en) * | 2004-04-13 | 2006-08-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Microelectronics package assembly tool and method of manufacture therewith |
SG145547A1 (en) * | 2004-07-23 | 2008-09-29 | Micron Technology Inc | Microelectronic component assemblies with recessed wire bonds and methods of making same |
NL1026739C2 (nl) * | 2004-07-29 | 2006-01-31 | Fico Bv | Maldeel voor het omhullen van elektronische componenten. |
JP2006269486A (ja) * | 2005-03-22 | 2006-10-05 | Renesas Technology Corp | 半導体装置の製造方法 |
KR100595467B1 (ko) * | 2005-05-12 | 2006-07-03 | 박정모 | 한약추출기 |
DE102005038755B4 (de) * | 2005-08-17 | 2016-03-10 | Robert Bosch Gmbh | Mikromechanisches Bauelement |
KR100822523B1 (ko) * | 2005-09-27 | 2008-04-16 | 토와 가부시기가이샤 | 전자부품의 수지밀봉 성형 방법 및 장치 |
JP2008004570A (ja) * | 2006-06-20 | 2008-01-10 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置の製造方法、樹脂封止型半導体装置の製造装置、および樹脂封止型半導体装置 |
JP4999482B2 (ja) * | 2007-02-07 | 2012-08-15 | アピックヤマダ株式会社 | 樹脂封止装置及び樹脂封止方法 |
US7833456B2 (en) | 2007-02-23 | 2010-11-16 | Micron Technology, Inc. | Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece |
US7799608B2 (en) * | 2007-08-01 | 2010-09-21 | Advanced Micro Devices, Inc. | Die stacking apparatus and method |
US9460951B2 (en) * | 2007-12-03 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of wafer level package integration |
US10074553B2 (en) * | 2007-12-03 | 2018-09-11 | STATS ChipPAC Pte. Ltd. | Wafer level package integration and method |
JP2009194267A (ja) * | 2008-02-18 | 2009-08-27 | Panasonic Corp | 半導体装置、その製造方法、およびそれを用いた電子機器 |
US7829366B2 (en) * | 2008-02-29 | 2010-11-09 | Freescale Semiconductor, Inc. | Microelectromechanical systems component and method of making same |
US7732937B2 (en) * | 2008-03-04 | 2010-06-08 | Infineon Technologies Ag | Semiconductor package with mold lock vent |
US20100102457A1 (en) * | 2008-10-28 | 2010-04-29 | Topacio Roden R | Hybrid Semiconductor Chip Package |
JP5185069B2 (ja) * | 2008-10-31 | 2013-04-17 | アピックヤマダ株式会社 | トランスファモールド金型およびトランスファモールド装置とこれを用いた樹脂成形方法 |
KR20110018777A (ko) * | 2009-08-18 | 2011-02-24 | 삼성엘이디 주식회사 | 발광 다이오드 패키지 |
US8299633B2 (en) | 2009-12-21 | 2012-10-30 | Advanced Micro Devices, Inc. | Semiconductor chip device with solder diffusion protection |
DE102010001473A1 (de) * | 2010-02-02 | 2011-08-04 | Robert Bosch GmbH, 70469 | Vorrichtung zum Herstellen von mit einer Kunststoffmasse umspritzten Bauteilen und umspritztes Bauteil |
TWI445139B (zh) * | 2010-06-11 | 2014-07-11 | Advanced Semiconductor Eng | 晶片封裝結構、晶片封裝模具與晶片封裝製程 |
JP5539814B2 (ja) * | 2010-08-30 | 2014-07-02 | Towa株式会社 | 基板露出面を備えた樹脂封止成形品の製造方法及び装置 |
JP5824765B2 (ja) * | 2011-01-11 | 2015-12-02 | アピックヤマダ株式会社 | 樹脂モールド方法及び樹脂モールド装置並びに供給ハンドラ |
CN102626975A (zh) * | 2011-02-03 | 2012-08-08 | 宝理塑料株式会社 | 模具、热塑性树脂密封电子基板及其制造方法 |
JP5906528B2 (ja) * | 2011-07-29 | 2016-04-20 | アピックヤマダ株式会社 | モールド金型及びこれを用いた樹脂モールド装置 |
KR101548786B1 (ko) * | 2012-05-31 | 2015-09-10 | 삼성전기주식회사 | 반도체 패키지 및 반도체 패키지 제조 방법 |
KR101388892B1 (ko) * | 2012-08-20 | 2014-04-29 | 삼성전기주식회사 | 패키지 기판, 패키지 기판의 제조 방법 및 패키지 기판의 성형 금형 |
US9862057B2 (en) * | 2012-12-12 | 2018-01-09 | United Technologies Corporation | Vacuum degassing laser-blocking material system and process |
NL2011512C2 (en) * | 2013-09-26 | 2015-03-30 | Besi Netherlands B V | Method for moulding and surface processing electronic components and electronic component produced with this method. |
CN104576411A (zh) * | 2013-10-25 | 2015-04-29 | 飞思卡尔半导体公司 | 双角部顶部闸道模制 |
CN104772870A (zh) * | 2014-01-10 | 2015-07-15 | 汉达精密电子(昆山)有限公司 | 排气结构 |
US10099411B2 (en) * | 2015-05-22 | 2018-10-16 | Infineon Technologies Ag | Method and apparatus for simultaneously encapsulating semiconductor dies with layered lead frame strips |
US9831104B1 (en) * | 2015-11-06 | 2017-11-28 | Xilinx, Inc. | Techniques for molded underfill for integrated circuit dies |
US10388566B2 (en) * | 2016-03-11 | 2019-08-20 | International Business Machines Corporation | Solder fill into high aspect through holes |
US10510721B2 (en) | 2017-08-11 | 2019-12-17 | Advanced Micro Devices, Inc. | Molded chip combination |
JP2019121722A (ja) * | 2018-01-10 | 2019-07-22 | 株式会社ディスコ | パッケージ基板の製造方法 |
US10593628B2 (en) | 2018-04-24 | 2020-03-17 | Advanced Micro Devices, Inc. | Molded die last chip combination |
US10672712B2 (en) | 2018-07-30 | 2020-06-02 | Advanced Micro Devices, Inc. | Multi-RDL structure packages and methods of fabricating the same |
SG10201900061TA (en) * | 2019-01-03 | 2020-08-28 | Delphi Tech Ip Ltd | Pressure sensor assembly |
US11114313B2 (en) * | 2019-05-16 | 2021-09-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer level mold chase |
US10923430B2 (en) | 2019-06-30 | 2021-02-16 | Advanced Micro Devices, Inc. | High density cross link die with polymer routing layer |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2748592B2 (ja) * | 1989-09-18 | 1998-05-06 | セイコーエプソン株式会社 | 半導体装置の製造方法および半導体封止用成形金型 |
US5656862A (en) * | 1990-03-14 | 1997-08-12 | International Business Machines Corporation | Solder interconnection structure |
JP3059560B2 (ja) * | 1991-12-25 | 2000-07-04 | 株式会社日立製作所 | 半導体装置の製造方法およびそれに使用される成形材料 |
JPH06302633A (ja) * | 1993-04-13 | 1994-10-28 | Fujitsu Ltd | 半導体装置の製造方法 |
JP3258764B2 (ja) * | 1993-06-01 | 2002-02-18 | 三菱電機株式会社 | 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法 |
US5482896A (en) * | 1993-11-18 | 1996-01-09 | Eastman Kodak Company | Light emitting device comprising an organic LED array on an ultra thin substrate and process for forming same |
JP3423766B2 (ja) * | 1994-03-11 | 2003-07-07 | Towa株式会社 | 電子部品の樹脂封止成形方法及び金型装置 |
US5672550A (en) * | 1995-01-10 | 1997-09-30 | Rohm Co., Ltd. | Method of encapsulating semiconductor devices using a lead frame with resin tablets arranged on lead frame |
US5817545A (en) * | 1996-01-24 | 1998-10-06 | Cornell Research Foundation, Inc. | Pressurized underfill encapsulation of integrated circuits |
MY114454A (en) * | 1996-03-14 | 2002-10-31 | Towa Corp | Method of sealing electronic component with molded resin |
US5780924A (en) * | 1996-05-07 | 1998-07-14 | Lsi Logic Corporation | Integrated circuit underfill reservoir |
US5700723A (en) * | 1996-05-15 | 1997-12-23 | Lsi Logic Corporation | Method of packaging an integrated circuit |
-
1997
- 1997-10-15 JP JP9299403A patent/JPH11121488A/ja not_active Abandoned
-
1998
- 1998-10-09 TW TW087116822A patent/TW393745B/zh not_active IP Right Cessation
- 1998-10-14 US US09/172,040 patent/US5998243A/en not_active Expired - Lifetime
- 1998-10-15 KR KR1019980043180A patent/KR100320776B1/ko not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI619988B (zh) * | 2015-12-16 | 2018-04-01 | Omron Tateisi Electronics Co | 電子裝置及其製造方法 |
WO2020133169A1 (zh) * | 2018-12-28 | 2020-07-02 | 瑞声精密制造科技(常州)有限公司 | 一种模具 |
CN113276359A (zh) * | 2020-02-19 | 2021-08-20 | 长鑫存储技术有限公司 | 注塑模具及注塑方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH11121488A (ja) | 1999-04-30 |
KR100320776B1 (ko) | 2002-07-02 |
US5998243A (en) | 1999-12-07 |
KR19990037124A (ko) | 1999-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW393745B (en) | Manufacturing method of a semiconductor device and apparatus used to process epoxy encapsulation operation | |
JP3194917B2 (ja) | 樹脂封止方法 | |
US8012799B1 (en) | Method of assembling semiconductor device with heat spreader | |
US6498055B2 (en) | Semiconductor device, method of manufacturing semiconductor device, resin molding die, and semiconductor manufacturing system | |
TW310466B (en) | Method of transfer molding electronic packages and packages produced thereby | |
TWI283831B (en) | Electronic apparatus and its manufacturing method | |
US8368235B2 (en) | Resin sealing method of semiconductor device | |
US6218215B1 (en) | Methods of encapsulating a semiconductor chip using a settable encapsulant | |
US7220615B2 (en) | Alternative method used to package multimedia card by transfer molding | |
US6811738B2 (en) | Manufacturing method of an electronic device package | |
TW201722681A (zh) | 樹脂封裝裝置以及樹脂封裝方法 | |
US7033862B2 (en) | Method of embedding semiconductor element in carrier and embedded structure thereof | |
JP2000208540A (ja) | 薄型半導体チップスケ―ル・パッケ―ジを密封する方法 | |
WO2017081882A1 (ja) | 樹脂封止装置及び樹脂封止方法 | |
US20150332986A1 (en) | Semiconductor device including semiconductor chip covered with sealing resin | |
US7189601B2 (en) | System and method for forming mold caps over integrated circuit devices | |
JP6208967B2 (ja) | Led装置の製造方法 | |
TWI240393B (en) | Flip-chip ball grid array chip packaging structure and the manufacturing process for the same | |
US6352878B1 (en) | Method for molding a bumped wafer | |
TWI338342B (zh) | ||
JP3139981B2 (ja) | チップサイズパッケージの樹脂封止方法及び樹脂封止装置 | |
JPH0342495B2 (zh) | ||
JPH08335596A (ja) | 半導体パッケージの製造方法 | |
JP2000176967A (ja) | 樹脂封止装置 | |
JP4731058B2 (ja) | 樹脂封止装置及び樹脂封止方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |