TW276356B - - Google Patents
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- TW276356B TW276356B TW084100826A TW84100826A TW276356B TW 276356 B TW276356 B TW 276356B TW 084100826 A TW084100826 A TW 084100826A TW 84100826 A TW84100826 A TW 84100826A TW 276356 B TW276356 B TW 276356B
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- 239000000758 substrate Substances 0.000 claims description 26
- 239000000919 ceramic Substances 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- ZTXONRUJVYXVTJ-UHFFFAOYSA-N chromium copper Chemical compound [Cr][Cu][Cr] ZTXONRUJVYXVTJ-UHFFFAOYSA-N 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- QUQFTIVBFKLPCL-UHFFFAOYSA-L copper;2-amino-3-[(2-amino-2-carboxylatoethyl)disulfanyl]propanoate Chemical compound [Cu+2].[O-]C(=O)C(N)CSSCC(N)C([O-])=O QUQFTIVBFKLPCL-UHFFFAOYSA-L 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第8410082β號專利申請菜 中:正頁(84年ΐπ月) Β7 五、發明説明(ί )
經濟部t央標準局员工消費合作社印« 發明背暑 1 .發明頜城 本發明係關於半導體電子姐件,更詳细言之,即利用多 層陶瓷(MLC)當作姐件*板以增加姐件上输入/输出之連接 器數目。 2 .相關持蓊說明 電子姐件廣用於工業上而且使用種類繁多。一種重要之 類型即名為扁平封裝,但為方便,於下文直接說明此型產 品。工業標準之扁平封裝組件通常為40 mm或28mm具方而且 一般以陶瓷或相當之基質與薄膜結構構成。晶片貼附於上 方並以輻射狀與輸入/输出(I / 0)焊墊霣連接。本產品俗名 為單石封装。一般I /0焊墊間距,K I /0焊墊中心線間距 計算,若0.5mm則在40ιβιπ封装上通常可容納約304涸有效 I/O點或焊墊。外界至扁平封装之連接引線通常為束線, C -線夾等等,僅黏在焊墊上,且在再流焊過程中為了機械 也許或不會K彈性線夾黏在底面。底面無電接點亦可 能,因為該结構為單石。 隨著科技進步亟須增加扁平封裝焊墊數,如此才能使用 須大霣I/O點之元件。一種增加I/O焊墊數技術係/縮短引 線間寬至如0.4 mm K容納376個焊墊。不過業發現,鑑於 容納增加的單石封装之I/O焊墊所需之機械尺寸及物理限 制已不敷成本。焊墊尺寸,焊墊至焊墊累積容差及焊塾至 邊緣及基板方度均很重要,但不足以降低製造成本。扁平 封装之霄子性能或其他轉射狀設計之電子组件因此受限於 ------------A装---- (請先閱讀背面之注意事{-!.塡寫本頁) •訂 線 各纸張尺度邊用中g國定標準(CNS)A4规格(210 X 2?7公釐) 83.3.10,000 第84100826號專利申請察 中文說明書修正頁U4年碑月) B7 五、發明説明()) 經濟部4-夾桴準屬员工消費合作杜印* 單石輻射狀技術之能力而阻滞不前。承認為須容納更高性 能之元件,MLC扁平封装即可行,其利用一底板或叁考平 面且依然為單石放射狀技術,但並無法解決有限1/(]能力 問題暨述及之製造成本問題。 本發明之一目的係提供已提昇I/O能力之電子姐件。 本發明之另一目的係提供已提昇I/O能力之扁平封装電 子姐件。 本發明之再另一目的係提出已提昇I/O能力之電子姐件 製法。 本發明之其他目榑及優點則由下文輕易地顯示。 琎明摘里 本發明提出之電子姐件,包含多層陶瓷(MLC)基板,一 晶Η黏在其上方,基板至少一面有許多接點或焊墊,該基 板爾緣上之焊墊Μ基板內霄導體與晶片電連接。 本發明之一觀點,係電子姐件包含置於MLC基板頂及底 兩面之I/O焊墊,因此大幅降低原有1/0設計之焊墊密度, 。本發明之另一觀點,焊墊密度為次要,1/〇焊墊數可藉 在MLC基板之頂及底兩面放置焊墊而大體增加1/〇焊墊數 ° lit外•頂或底面之多列1/〇焊墊組態及雙面多列1/0焊 费均可使用。多列設計具相鄰交錯焊墊較佳。 圖1示之 為完金徽底了解本發明,參考配合附圖之說明,其中: HlAg先前技_具輻射狀設計之扁平封裝霄子姐件;^片 段示圖。 (請先閲讀背面之注意事{-*.塡寫本頁) 本紙張又度適用+ 一國豕標準(CNS)人4規格(21〇 X 297公爱) 83.3.10,000 276356 A7 B7 五、發明説明(3 ) (請先閱讀背面之注意事項再填寫本頁) 圖1B為圖1A沿線1B-1B之側視圃。 圖2A及2B為本發明MLC扁平封装之示圖。 圖3A及3B為本發明具交錯I/O焊墊之MLC扁平封裝示圖 0 圖4 A及4B為本發明電子姐件可使用之連接器示圖。 較住里艚甯淪例說明 多層陶瓷(MLC)電子組件如電容器即為本技蕤所热知。 一般而言,陶瓷層與金屬層相叠形成壓塊(交替性)*其中 金屬及陶瓷層相互交置。 如今已證實ML C可用來製成電子姐件,位在MLC基板上 (例如晶片)之姐件須與I/O連接器,如位在MLC基板周緣 上焊墊電連接。製成之MLC具備電導體,如銅、鉬及鋳, —般名為配線、導線、銅軌、線路、.貫孔等等。MLC壓塊 内之電接點係從晶片上某處Μ電導體引至壓塊周緣之對應 焊墊形成。電導體厚度變化很大,約由0.01mm至約0.05 mm或更厚。MLC结構之層數不定,而四曆结構則為說明本 發明目的之例示。 經濟部中央標準局員工消費合作社印裝 而電導體從焊墊通過基板再電連接至晶片,表面之導體 或如輻射技術述及之基板表面亦羼本發明特點,也可與本 發明於特殊用途之内導體併用。 圖1 A所示為一般扁平封裝電子組件10。姐件之基板11上 鑲装一晶片12。電導體13將晶片與位處姐件10周緣上之對 應I/O焊墊14電連接為本技藝热知。圖1B為姐件10之側視 圖。基板1 1通常為約1 . 5mm厚之陶瓷。晶片1 2—般為含矽 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 經濟部中央梯準局員工消費合作杜印製 A7 B7 五、發明説明(4 ) 積體電路之半導體晶片。電導體I3使晶片12與1/0焊墊14 電連接而C-線夾15使姐件10與周邊單元電連接。 基板11周緣上所示之接觸焊墊14經測得約為0.2 5 mm至 0.30mm乘M〇.9mra至l,lmm且約2«m厚’一般由多層鉻-銅 組成。 圖2 A所示為本發明之電子組件16,包括基板17,即圖 2B中側視圖之MLC基板。基板17包括陶瓷靥17a、17b、 17c及17d,即為四層陶瓷構造。内孔18及線路19由晶片 12電連接至焊墊14。精於該技藹者應得知,貫孔18及線路 19數目及位於姐件16内部之可能路徑很多,且異於輻射狀 技術,即對電子組件上配置之I/O焊墊數目無實際機械限 制影響。期望焊墊間距可縮短至0.25mm或更低並相形增加 組件之I/O密度。一般之間距為0.3mm至0.5mm,例如, 0.4 mm可能較適用。 圖3 A所示為本發明之另一電子組件20,其一表面為交錯 狀焊墊設計。姐件20包括一基板21,為圖3B所示側視圖之 四層21a、21b、21c及21d MLC。貫孔18及線路19由晶Η 12電連接至焊墊14。 圖2Α及2Β中繪示之姐件16及圖3Α及3Β中繪示之姐件20可 Μ多層陶瓷技術製造。例如,圖2Α及2Β内各層未燒成之生 壞陶瓷17a、17b, 17c及17d—般均用〇.25mm之厚度。各層 經打孔形成頂至底之電内接通道(貫孔)18,並續藉網印技 術經由罩蒂行金鼷化處理,再Μ導電蒼填充貫孔。以高溫 共燒陶瓷技術為例·導電資限為耐火金屬,一般為鎢或鉬。 --- 、 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨Ο X 297公慶) -------^---^-〈装-1-----訂------丨『 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局ΜΓ工消費合作社印製 第84100826號專利申請案 中文說明書修正頁(84年押月) __ B7 五、發明説明(X) 每層上之内連平面霣路均同樣行網印及金羼化處理。 層數係所須封装密度及獲得裔要之霄內接點為公訂約4 米爾線寬及約6米爾之貫孔直徑之能力之函數。一般言之 ’須3 0 4個I / 〇點之封裝則包含四層。 各層K適當加熱及加壓叠歷成生胚組件。封装續以 ΙβΟΟΤ:之高溫共燒技術行燒結處理而燒成。導電膏及陶瓷 之組成相苻方能於相同溫度燒结,因而可確實控制燒成姐 件之機械性質。 燒成組件上焊墊績塗上,例如,鎳及金以確保抗蝕性、 低電接觸霉阻並提供後續姐合及本技藝熟知之1/〇連接器 ,如阃4Α及4Β中22、23、24及25之銅焊之冶金易用性。 當焊墊僅位處圖1Α及1Β所示之MLC對置面之一時,電連 接外界元件與本發明之電子组件之連接器可使用先前技藝 之彈性C-線夾。圖2Α及2Β中所示雙面.均具焊塾之組件,圖 4Α中所示之線夾22及23與引線架26均可採用。同樣地,圖 4Β所示之線夾24及25引線架27適於圖3Α及3Β所示之交錯狀, 焊墊姐態。線夾長度實用上應儘可能縮短方可具有改良彈 性作用。由於焊墊密度增加,在固黏處理中使用鋼梳( comb)或輪絜(blade)定位裝置可用以支承及保持連接器 適當校準。 因此可看到根據上述之目欏,由前述施行完成者當中顯 示’均可有效達成*因為在未悖離本發明精神範赌時,上 述结構可執行特定變化,此係旨於對上述所有钿節或附圖 所示加Μ例示說明而非限制之意。 -8 - 本紙張又度適用中國國家標(CNS)A4胡格(210 X 297公釐) ~ 83.3.10,000 ------------π装---- (請先閲讀背面之注意事'ί r.填寫本頁) 訂 線 276356 A7 B7 五、發明説明(6 同時本發明所例示及說明者均視為最實用及較佳具體實 施例,成認為許多可能之改良均併入本發明範赌,因而隨 附之申請專利範圍擴及所有等效範圍。 (請先閲讀背面之注意事項再填寫本頁) 裝4! 經濟部中央標準局員工消費合作杜印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐)
Claims (1)
- A8 B8 C8 D8 經濟部中央標準局負工消費合作社印製 六、申請專利範圍 1. 一種電子姐件,包括: 一多層陶瓷基板,基板内有電等體; 一片晶片,貼附在基板上; 許多_入/输出焊墊,位於基板之至少一表面上,即 該基板之周緣,晶片與焊墊Μ電導體轚連接。 2. 根據申請專利範圍第1項之電子姐件,其中基板雙面上 均有输入/输出焊墊。 3. 根據申請專_利範圃第1項之電子姐件•其中焊墊呈交錯 狀。 4. 根據申請専利範圃第1項之電子姐件,其中位基板之一 或雙面上之電導體係用Μ電連接晶片與部份焊塾。 5. 根據申請專利範圍第1項之電子姐件,為扁平封裝。 6. 根據申請專利範圍第2項之罨子姐件,為扃平封装。 7. 根據申請專利範圍第3項之電子組件,為扁平封装。 8. 根據申誚專利範圍第4項之電子姐件,為扁平封裝。 9. 根據申請專利範園第5項之扁平封裝姐件,其中焊墊間 距介於約0.3 mm至0.5 mm之間。 10. 根據申請專利範圍第6項之扁平封裝姐件•其中焊墊間 距介於約0.3 mm至約0.5 mm之間。 11. 根據申請專利範圍第1項之電子姐件之製法•包括形成 各未燒成陶瓷層,陶瓷曆内有由頂至底之金羼化貫孔, 在陶瓷表面形成導線,該導線與貫孔内連而形成由晶片 至焊墊之®連接,然後®疊多曆體成為多曆陶瓷基板。 12. 根據申請專利範圍第11項之方法,其中貫孔與導線糖網 印法以導電膏形成。 t 〇 本紙張尺度適用中國國家標準(CNS )八4規格(210X297公釐) Ί.~^^d 装4-----訂------J-A—^ I-— (請先聞讀背面之注意事項再填寫本頁)
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JPH05109977A (ja) * | 1991-10-18 | 1993-04-30 | Mitsubishi Electric Corp | 半導体装置 |
US5454161A (en) * | 1993-04-29 | 1995-10-03 | Fujitsu Limited | Through hole interconnect substrate fabrication process |
-
1995
- 1995-01-28 TW TW084100826A patent/TW276356B/zh active
- 1995-05-19 EP EP95480064A patent/EP0689247A1/en not_active Withdrawn
- 1995-05-26 JP JP07128594A patent/JP3084209B2/ja not_active Expired - Fee Related
- 1995-10-10 US US08/541,397 patent/US5669136A/en not_active Expired - Fee Related
-
1996
- 1996-04-04 US US08/628,148 patent/US5790386A/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI483361B (zh) * | 2012-03-23 | 2015-05-01 | Chipmos Technologies Inc | 半導體封裝基板以及半導體封裝結構 |
US9082710B2 (en) | 2012-03-23 | 2015-07-14 | Chipmos Technologies, Inc. | Chip packaging substrate and chip packaging structure |
Also Published As
Publication number | Publication date |
---|---|
US5790386A (en) | 1998-08-04 |
JPH0817965A (ja) | 1996-01-19 |
EP0689247A1 (en) | 1995-12-27 |
US5669136A (en) | 1997-09-23 |
JP3084209B2 (ja) | 2000-09-04 |
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