TW201730989A - 多堆疊疊層封裝結構 - Google Patents
多堆疊疊層封裝結構 Download PDFInfo
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- TW201730989A TW201730989A TW105121518A TW105121518A TW201730989A TW 201730989 A TW201730989 A TW 201730989A TW 105121518 A TW105121518 A TW 105121518A TW 105121518 A TW105121518 A TW 105121518A TW 201730989 A TW201730989 A TW 201730989A
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- device die
- package
- dielectric layer
- die
- rewiring
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Classifications
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Abstract
一種封裝包括:一第一裝置晶粒;及一第一封裝材料,其將該第一裝置晶粒封裝於其中。該第一裝置晶粒之一底部表面與該第一封裝材料之一底部表面共面。第一介電層下伏於該第一裝置晶粒。第一重佈線在該等第一介電層中且電耦接至該第一裝置晶粒。第二介電層上覆於該第一裝置晶粒。第二重佈線在該等第二介電層中且電耦接至該等第一重佈線。一第二裝置晶粒上覆於且電耦接至該等第二重佈線。無焊接區域將該第二裝置晶粒連接至該等第二重佈線。一第二封裝材料將該第二裝置晶粒封裝於其中。一第三裝置晶粒電耦接至該等第二重佈線。一第三封裝材料將該第三裝置晶粒封裝於其中。
Description
本發明是有關於一種半導體裝置,特別係有關於一種應用於電源供應器之半導體裝置。本申請案主張以下臨時申請之美國專利申請案的權益:2015年11月10日申請且名為「Multi-Stack Package on Package-on-Package Structures」之申請案第62/253,401號;該申請案係據此以引用的方式併入本文中。
在習知整合式扇出(Integrated Fan-Out;InFO)程序中,將頂部封裝(其中結合第一裝置晶粒)結合至底部封裝。底部封裝亦可具有封裝於其中之裝置晶粒。藉由採用InFO程序,會增加封裝之整合度。
在現有InFo程序中,首先形成底部封裝,此包括將模製原料(molding compound)封裝於裝置晶粒及複數個貫通模製通孔上。形成重佈線以連接至裝置晶粒及貫通模製通孔。接著將可包括結合至額外封裝基板之裝置晶粒的頂部封裝經由焊接點而結合至底部封裝。
在一實施例中,本揭露提供一種封裝包含一第一裝置晶粒;一第一封裝材料,其將該第一裝置晶粒封裝於其中,其中該第一裝置晶粒之一底部表面與該第一封裝材料之一底部表面共面;第一介電層,其下伏於該第一裝置晶粒;第一重佈線,其在該等第一介電層中且電耦接至該第一裝置晶粒;第二介電層,其上覆於該第一裝置晶粒;第
二重佈線,其在該等第二介電層中且電耦接至該等第一重佈線;一第二裝置晶粒,其上覆於且電耦接至該等第二重佈線,其中無焊接區域將該第二裝置晶粒連接至該等第二重佈線;一第二封裝材料,其將該第二裝置晶粒封裝於其中;一第三裝置晶粒,其電耦接至該等第二重佈線;及一第三封裝材料,其將該第三裝置晶粒封裝於其中。
在一實施例中,本揭露提供一種方法包含將一第一裝置晶粒置放於一載體上方;將該第一裝置晶粒封裝於一第一封裝材料中;執行一第一平坦化以顯露該第一裝置晶粒中之第一金屬柱;形成第一介電層於該第一裝置晶粒及該第一封裝材料上方;形成第一重佈線於該等第一介電層中,其中該等第一重佈線電耦接至該等第一金屬柱;將一第二裝置晶粒黏著至該等第一介電層之一頂部表面;形成一第一貫通通孔於該等第一介電層上方;將該第二裝置晶粒及該第一貫通通孔封裝於一第二封裝材料中;執行一第二平坦化以顯露該第一貫通通孔及該第二裝置晶粒中之第二金屬柱;形成第二介電層於該第二裝置晶粒上方;及形成第二重佈線於該等第二介電層中,其中該等第二重佈線電耦接至該等第二金屬柱及該第一貫通通孔。
在一實施例中,本揭露提供一種方法包含將一第一裝置晶粒置放於一載體上方,其中該第一裝置晶粒包含:一第一半導體基板;及穿過該第一半導體基板之第一貫通通孔;將該第一裝置晶粒封裝於一第一封裝材料中;形成第一介電層於該第一裝置晶粒上方;形成第一重佈線於該等第一介電層中,其中該等第一重佈線電耦接至該第一裝置晶粒中之第一金屬柱;將一第二裝置晶粒黏著至該等第一介電層之一頂部表面;形成第二貫通通孔於該等第一介電層上方,其中該等第二貫通通孔電耦接至該等第一重佈線;將該第二裝置晶粒封裝於一第二封裝材料中;形成第二介電層於該第二裝置晶粒上方;形成第二重佈線於該等第二介電層中,其中該等第二重佈線電耦接至該第二裝置
晶粒中之第二金屬柱;使該載體與該第一裝置晶粒脫結;對該第一半導體基板執行一背面研磨以顯露該等第一貫通通孔;及形成第三重佈線以電耦接至該等第一貫通通孔。
20‧‧‧載體
22‧‧‧黏著層
24‧‧‧介電層
26‧‧‧導電晶種層
28‧‧‧遮罩層
30‧‧‧開口
32‧‧‧貫通通孔
34‧‧‧裝置晶粒
34'‧‧‧晶粒堆疊
36‧‧‧半導體基板
38‧‧‧晶粒附接膜
40‧‧‧積體電路裝置/主動及被動裝置/積體電路
42‧‧‧貫通通孔
43‧‧‧重佈線(RDL)
44‧‧‧金屬柱
46‧‧‧介電層
48‧‧‧封裝材料
50‧‧‧介電層
52‧‧‧重佈線(RDL)
54‧‧‧開口
56‧‧‧貫通通孔
58‧‧‧裝置晶粒
60‧‧‧晶粒附接膜
62‧‧‧金屬柱
64‧‧‧表面介電層
66‧‧‧封裝材料
68‧‧‧介電層
70‧‧‧重佈線(RDL)
72‧‧‧凸塊下金屬層(UBM)
74‧‧‧電連接器
76‧‧‧晶圓層級封裝/主要封裝/下伏封裝
78‧‧‧載體
80‧‧‧開口
82‧‧‧PoP封裝
84‧‧‧焊接區域
86‧‧‧底填充料
88‧‧‧封裝
90‧‧‧封裝材料
92‧‧‧重佈線(RDL)
94‧‧‧介電層
200‧‧‧上覆封裝/次要封裝
202‧‧‧封裝基板
234‧‧‧裝置晶粒
302‧‧‧封裝基板
334‧‧‧裝置晶粒
348‧‧‧封裝材料
434‧‧‧裝置晶粒
534‧‧‧裝置晶粒
536‧‧‧焊接區域
538‧‧‧貫通通孔
600‧‧‧程序流程
602‧‧‧步驟
604‧‧‧步驟
606‧‧‧步驟
608‧‧‧步驟
610‧‧‧步驟
612‧‧‧步驟
614‧‧‧步驟
616‧‧‧步驟
618‧‧‧步驟
620‧‧‧步驟
622‧‧‧步驟
624‧‧‧步驟
當與附圖一起進行閱讀時,自以下【實施方式】最好地理解本發明之態樣。應注意,根據業界中之標準慣例,各種特徵未按比例繪製。事實上,可出於論述清楚起見而任意地增加或縮減各種特徵之尺寸。
圖1至圖11A說明根據一些實施例的包括多堆疊晶粒之封裝的形成中之中間階段的橫截面圖。
圖11B至圖16說明根據一些實施例的包括多堆疊晶粒之封裝的橫截面圖。
圖17說明用於形成根據一些實施例之封裝的程序流程。
以下揭示內容提供用於實施本發明之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本發明。當然,此等者僅僅為實例且不意欲為限制性的。舉例而言,在以下描述中的第一特徵在第二特徵上方或上之形成可包括第一特徵及第二特徵被形成為進行直接接觸的實施例,且亦可包括額外特徵可形成於第一特徵與第二特徵之間使得第一特徵及第二特徵可不進行直接接觸的實施例。另外,本發明可在各種實例中重複參考數字及/或字母。此重複係出於簡單及清楚之目的,且本身並不規定所論述之各種實施例及/或組態之間的關係。
另外,本文中可出於描述簡易起見而使用諸如「下伏」、「下方」、「下部」、「上覆」、「上部」及其類似者之空間相對術語以描述如諸圖所說明的一個元件或特徵與另一(其他)元件或特徵之關係。除了
諸圖所描繪之定向以外,空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用之空間相對描述詞同樣地可被相應地解譯。
根據各種例示性實施例而提供多堆疊封裝及形成該封裝之方法。論述一些實施例之一些變化。貫穿各種視圖及說明性實施例,類似參考編號用以指定類似元件。貫穿描述,術語「多堆疊封裝」係指裝置晶粒之兩個或兩個以上層級(各自封裝於一封裝材料中)在其間不具有焊接區域的封裝。此外,貫穿描述,具有金屬柱的裝置晶粒之表面被稱作各別裝置晶粒之前表面,且與該等前表面相對之表面為後表面。根據一些實施例,後表面亦為各別裝置晶粒之半導體基板之表面。
圖1至圖11A說明根據一些實施例之封裝的形成中之中間階段的橫截面圖。在後續論述中,參看圖17所展示之程序流程600來論述圖1至圖11A所展示之程序步驟。
圖1及圖2說明貫通通孔32之形成。各別步驟被展示為圖17所展示之程序流程中的步驟602。參看圖1,提供載體20,且將黏著層22安置於載體20上方。載體20可為胚料玻璃載體、胚料陶瓷載體或其類似者,且可具有具備圓形俯視圖形狀的半導體晶圓之形狀。載體20有時被稱作載體晶圓。黏著層22可由(例如)光至熱轉換(Light-to-Heat Conversion;LTHC)材料形成,但可使用其他類型之黏著劑。根據本發明之一些實施例,黏著層22能夠在光熱下分解,且因此可自形成於載體20上之結構釋放載體20。
亦參看圖1,將介電層24形成於黏著層22上方。根據本發明之一些實施例,介電層24為由聚合物形成之聚合物層,該聚合物可為諸如聚苯并噁唑(PBO)、聚醯亞胺或其類似者之感光聚合物。根據一些實施例,介電層24係由諸如氮化矽之氮化物、諸如氧化矽之氧化物、磷
矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)或其類似者形成。
將導電晶種層26(例如)經由物理氣相沈積(PVD)而形成於介電層24上方。導電晶種層26可為包括銅、鋁、鈦、其合金或其多層之金屬晶種層。根據本發明之一些實施例,導電晶種層26包括諸如鈦層之第一金屬層(未圖示)及在該第一金屬層上方的諸如銅層之第二金屬層(未圖示)。根據本發明之替代實施例,導電晶種層26包括諸如銅層之單一金屬層,其可由實質上純銅或銅合金形成。
如圖1所展示,將遮罩層28(諸如光阻)施加於導電晶種層26上方,且接著使用光微影遮罩進行圖案化。根據本發明之一些實施例,遮罩層28係由乾膜形成,該乾膜被層壓至導電晶種層26上。根據一些實施例,遮罩層28係由光阻形成,該光阻係藉由旋塗而施加。由於圖案化(曝光及顯影),將開口30形成於遮罩層28中,導電晶種層26之一些部分係通過開口30而曝露。
貫通通孔32經由電鍍而形成於開口30中,該電鍍可為電極電鍍或無電極電鍍。貫通通孔32電鍍於導電晶種層26之經曝露部分上。貫通通孔32為導電的,且可為包括銅、鋁、鎢、鎳或其合金之金屬通孔。貫通通孔32之俯視圖形狀包括且不限於矩形、正方形、圓形及其類似者。貫通通孔32之高度係由隨後置放之裝置晶粒34(圖3)之厚度判定,其中根據本發明之一些實施例,貫通通孔32之高度稍微大於或等於裝置晶粒34之厚度。
在貫通通孔32之電鍍之後,移除遮罩層28。因此,先前由遮罩層28覆蓋的導電晶種層26之部分被曝露。接下來,執行蝕刻步驟以移除導電晶種層26之經曝露部分,其中蝕刻可為非等向性或等向性蝕刻。另一方面,被貫通通孔32重疊的導電晶種層26(圖1)之部分保持未被蝕刻。圖2中展示所得貫通通孔32。在本揭露之上下文中,導電
晶種層26之剩餘下伏部分被稱作貫通通孔32之底部部分,且未被分離地展示。導電晶種層26及貫通通孔32之上覆部分可或可不具有可區別的界面。舉例而言,導電晶種層26中之銅層可在無可區別的界面的情況下與貫通通孔32合併。導電晶種層26中之鈦層可區別於含銅貫通通孔32。由於導電晶種層26之蝕刻,介電層24被曝露。
圖3說明裝置晶粒34在介電層24上方之置放。各別步驟被展示為圖17所展示之程序流程中的步驟604。可將裝置晶粒34經由晶粒附接膜38而黏著至介電層24,晶粒附接膜38為黏著膜。晶粒附接膜38之邊緣與裝置晶粒34之各別邊緣共端(對準)。裝置晶粒34可包括具有與各別下伏晶粒附接膜38進行實體接觸之後表面(面向下之表面)的半導體基板36。裝置晶粒34進一步包括在各別半導體基板36之前表面(面向上之表面)處的積體電路裝置40(諸如主動裝置或被動裝置)。裝置晶粒34可為諸如靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒、快閃記憶體晶粒等等之記憶體晶粒。裝置晶粒34可彼此相同。
根據一些實施例,裝置晶粒34不具有在半導體基板36中之貫通通孔。根據替代實施例,裝置晶粒34具有延伸至半導體基板36中之貫通通孔42。在存在貫通通孔42之實施例中,由於貫通通孔42可充當用於互連上覆於及下伏於裝置晶粒34之導電特徵的電連接,故可不(或可)形成貫通通孔32。因此,不必形成貫通通孔32,且可節省各別製造成本。根據一些實施例,貫通通孔42中之一些或全部單獨地用於電互連上覆於及下伏於裝置晶粒34之導電特徵,且不電連接/耦接至諸如電晶體、二極體、電容器、電阻器等等之任何主動及被動裝置40。貫穿描述,當特徵(諸如貫通通孔32及42)被展示為虛線時,指示可或可不形成此等特徵。
裝置晶粒34可包括接近於其頂部表面之金屬柱44。金屬柱44電
耦接至裝置晶粒34內部之積體電路40。根據本發明之一些例示性實施例,金屬柱44係由介電層46覆蓋,其中介電層46之頂部表面高於金屬柱44之頂部表面。介電層46進一步延伸至金屬柱44之間的間隙中。根據本發明之替代實施例,金屬柱44之頂部表面與各別介電層46之頂部表面共面。根據一些例示性實施例,介電層46可由諸如聚苯并噁唑(PBO)或聚醯亞胺之聚合物形成。金屬柱44可為銅柱,且亦可包括諸如鋁、鎳或其類似者之其他導電/金屬材料。
參看圖4,將封裝材料48封裝於裝置晶粒34及貫通通孔32上。各別步驟被展示為圖17所展示之程序流程中的步驟606。封裝材料48填充相鄰裝置晶粒34之間的間隙,且包圍裝置晶粒34及貫通通孔32中之每一者。封裝材料48可包括模製原料、模製底填充料、環氧樹脂及/或樹脂。在封裝程序之後,封裝材料48之頂部表面高於金屬柱44及貫通通孔32之頂部表面。
接下來,執行諸如化學機械拋光(CMP)步驟或研磨步驟之平坦化步驟以平坦化封裝材料48,直至貫通通孔32被曝露為止。裝置晶粒34之金屬柱44亦由於平坦化而被曝露。歸因於平坦化,貫通通孔32之頂部表面與金屬柱44之頂部表面實質上齊平(共面),且與封裝材料48之頂部表面實質上齊平(共面)。
參看圖5,將複數個介電層50及各別重佈線(RDL)52形成於封裝材料48、貫通通孔32及金屬柱44上方。各別步驟被展示為圖17所展示之程序流程中的步驟608。根據本發明之一些實施例,介電層50係由諸如PBO、聚醯亞胺或其類似者之聚合物形成。根據本發明之替代實施例,介電層50係由諸如氮化矽、氧化矽、氮氧化矽或其類似者之無機介電材料形成。
RDL 52電耦接至金屬柱44及貫通通孔32,且可將金屬柱44及貫通通孔32彼此互連。RDL 52可包括金屬跡線(金屬線)及下伏於且連接
至金屬跡線之通孔。根據本發明之一些實施例,RDL 52係經由電鍍程序而形成,其中RDL 52中之每一者包括一晶種層(未圖示)及在該晶種層上方之一經電鍍金屬材料。晶種層及經電鍍金屬材料可由相同材料或不同材料形成。
參看圖5,介電層50包括上覆於RDL 52之頂部介電層,其中RDL 52之一些金屬接合墊係經由頂部介電層50中之開口54而被曝露。
接下來,參看圖6,將貫通通孔56形成於介電層50及RDL 52上方。各別步驟被展示為圖17所展示之程序流程中的步驟610。形成程序可包括:形成在介電層50上方且延伸至開口54(圖5)中之晶種層(未圖示);形成經圖案化遮罩層(未圖示),其中開口54被曝露至經圖案化遮罩層中之開口;電鍍經圖案化遮罩層中之開口中的貫通通孔56;移除經圖案化遮罩層;及蝕刻晶種層。
貫通通孔56之晶種層可包括鈦層及在鈦層上方之銅層。經電鍍材料可具有均一組合物且可由銅或銅合金形成。經電鍍材料包括在頂部介電層50之頂部表面上方的一些部分,及延伸至開口54(圖5)中之其他部分。
圖6亦說明裝置晶粒58經由(例如)晶粒附接膜60而至介電層50上之黏著。各別步驟被展示為圖17所展示之程序流程中的步驟612。裝置晶粒58之後表面(該後表面可為裝置晶粒58中之半導體基板之後表面)與晶粒附接膜60接觸。裝置晶粒58可為諸如中央處理單元(CPU)晶粒、圖形處理單元(GPU)晶粒或其類似者之邏輯晶粒。裝置晶粒58包括表面介電層64中之金屬柱62。表面介電層64可由(例如)PBO或其他介電材料形成。
圖7說明貫通通孔56及裝置晶粒58運用封裝材料66之封裝。各別步驟被展示為圖17所展示之程序流程中的步驟614。封裝材料66可為模製原料。在封裝材料66之施配及固化之後,執行平坦化以移除過量
封裝材料66,使得貫通通孔56及金屬柱62被曝露。
接下來,參看圖8,將介電層68及RDL 70形成於封裝材料66及裝置晶粒58上方。各別步驟被展示為圖17所展示之程序流程中的步驟616。介電層68亦可由諸如PBO或聚醯亞胺之聚合物形成。RDL 70電耦接至貫通通孔56及金屬柱62。此外,RDL 70亦可將貫通通孔56電連接至金屬柱62。
進一步參看圖8,根據本發明之一些例示性實施例而形成凸塊下金屬層(UBM)72及電連接器74。電連接器74電耦接至RDL 70及52、金屬柱62及44,及/或貫通通孔32、42及56。電連接器74之形成可包括將焊球置放於RDL 70上方,且接著回焊焊球。根據本發明之替代實施例,電連接器74之形成包括執行電鍍程序以將焊接區域形成於RDL 70上方且接著回焊焊接區域。電連接器74亦可包括金屬柱,或金屬柱及焊接帽,其亦可經由電鍍而形成。
在本揭露之上下文中,上覆於黏著層22之結構被稱作晶圓層級封裝76,其可為複合晶圓。接下來,使封裝76與載體20脫結。根據一些例示性脫結程序,如圖9所展示,將載體78附接至封裝76以保護電連接器74。各別步驟被展示為圖17所展示之程序流程中的步驟618。載體78可為固定至切割框架(未圖示)上之切割帶。脫結係(例如)藉由將UV光或雷射投影於黏著層22(圖8)上而執行。舉例而言,當黏著層22係由LTHC形成時,自光或雷射產生之熱致使LTHC分解,且因此使載體20與晶圓層級封裝76分離。圖9中展示所得結構。
圖10說明用於將開口80形成於介電層24中之圖案化。各別步驟被展示為圖17所展示之程序流程中的步驟620。舉例而言,當介電層24為聚合物層時,其可使用雷射鑽取予以圖案化以移除重疊於貫通通孔32之部分,使得貫通通孔32通過開口80而被曝露。
圖11A說明封裝200至封裝76之結合,因此形成PoP封裝82。各別
步驟被展示為圖17所展示之程序流程中的步驟622。封裝76及200亦分別被稱作主要封裝及次要封裝。結合係經由焊接區域84而執行,焊接區域84將貫通通孔32接合至上覆封裝200中之金屬接合墊。根據本發明之一些實施例,封裝200包括裝置晶粒234,其可為諸如SRAM晶粒、DRAM晶粒或其類似者之記憶體晶粒。裝置晶粒234亦可與裝置晶粒34相同。根據一些例示性實施例,記憶體晶粒亦結合至封裝基板202。封裝材料90將裝置晶粒234封裝於其中,其中封裝材料90可為模製原料、模製底填充料等等。在次要封裝200至主要封裝76之結合之後,將底填充料86施配至次要封裝200與主要封裝76之間的間隙中,且接著進行固化。接著可執行晶粒鋸切以將封裝82鋸切成個別封裝88,封裝88彼此相同。各別步驟被展示為圖17所展示之程序流程中的步驟624。
由於晶粒鋸切,封裝材料48、封裝材料66、介電層50及介電層68之各別邊緣彼此對準。封裝材料90及封裝基板202之邊緣可或可不與下伏封裝76之邊緣對準。
根據形成貫通通孔42之一些實施例,在形成如圖9所展示之結構之後,執行背面研磨以移除晶粒附接膜38及半導體基板36之一些部分,直至貫通通孔42被曝露為止。接下來,如圖11B所展示,將RDL 43形成於貫通通孔42上方且電耦接至貫通通孔42。當形成貫通通孔42時,根據一些實施例而可或可不形成貫通通孔32。根據一些實施例,貫通通孔42充當RDL 43與RDL 52之間的互連(通過貫通通孔42與金屬柱44之間的金屬線及通孔(未圖示))。貫通通孔42可單獨地用於RDL 43及52之互連,且未電耦接至裝置晶粒34中之任何被動或主動裝置。此由於可形成小於貫通通孔32之貫通通孔42而具有增加貫通通孔之總數的有利特徵。另外,節省了以其他方式將被招致用於形成貫通通孔32之成本。
在圖11A及圖11B所展示之封裝中,裝置晶粒58、34及234形成包括藉由中間介電層50及RDL 52而分離之兩個封裝區域/材料的多堆疊封裝。由於無焊接點用於裝置晶粒34與裝置晶粒58之間,故將裝置晶粒34堆疊於經封裝裝置晶粒58上方會引起極薄封裝。另外,兩個或兩個以上裝置晶粒34可位於同一封裝材料48中,且因此進一步縮減封裝88之高度。然而,由於裝置晶粒58相比於裝置晶粒34具有較大俯視圖面積,故未增加封裝88之佔據面積(俯視圖面積)。
圖12至圖16說明根據本發明之一些實施例的封裝88。除非另有指定,否則此等實施例中之組件之材料及形成方法與由圖1至圖11A及圖11B所展示之實施例中之類似參考數字表示的類似組件基本上相同。因此可在圖1至圖11A及圖11B所展示之實施例之論述中找到關於圖12至圖16所展示之組件之形成程序及材料的細節。在此等實施例中之每一者中,裝置晶粒234可與裝置晶粒34相同或不同。此外,在圖12至圖16中之每一者所展示之實施例中,形成貫通通孔32或貫通通孔42,或形成貫通通孔32及貫通通孔42兩者。
圖12說明在裝置晶粒58、34及234之不同層級之間不具有焊接區域的封裝88。裝置晶粒234係經由RDL 92而電耦接至裝置晶粒34,RDL 92形成於介電層94中。根據本發明之一些實施例,圖12中之結構之形成程序可包括將裝置晶粒234封裝於封裝材料90中,接著形成RDL 92及介電層94。圖1至圖8中基本上展示後續步驟。藉由使用圖12中之實施例,由於在所得封裝88中不存在焊接區域,故進一步縮減該所得封裝之厚度。
圖13說明根據一些實施例之封裝88。此等實施例相似於圖11A及圖11B中之實施例,惟如下情形除外:主要封裝76具有裝置晶粒58之單一層級,而次要封裝200包括多層疊式裝置晶粒34及234。
圖14說明根據一些實施例之封裝88。此等實施例相似於圖11A及
圖11B中之實施例,惟如下情形除外:主要封裝76及次要封裝200兩者包括多層疊式裝置晶粒。舉例而言,主要封裝76包括形成多堆疊封裝之裝置晶粒58及裝置晶粒34。次要封裝200包括形成多堆疊封裝之裝置晶粒234及裝置晶粒334。裝置晶粒234可與裝置晶粒334相同或與裝置晶粒334不同。裝置晶粒334進一步封裝於封裝材料348中。
圖15說明根據一些實施例之封裝88。此等實施例相似於圖11A及圖11B中之實施例,惟如下情形除外:次要封裝200包括經由線結合而結合至各別封裝基板202之裝置晶粒434。裝置晶粒34可與裝置晶粒234不同。舉例而言,裝置晶粒34可為DRAM晶粒,而裝置晶粒234可為快閃記憶體晶粒。
圖16說明根據一些實施例之封裝88。此等實施例相似於圖15中之實施例,惟如下情形除外:圖15中之裝置晶粒34係由晶粒堆疊34'替換,其中晶粒堆疊34'中之每一者包括結合在一起之複數個裝置晶粒534。晶粒堆疊34'係在用以形成封裝88之前被預先形成。晶粒堆疊34'中之裝置晶粒534係由焊接區域536結合。此外,裝置晶粒534包括穿過各別半導體基板之貫通通孔538。
本發明之實施例具有一些有利特徵。藉由形成多堆疊封裝,消除了或在數目方面至少縮減了用於習知疊層封裝(PoP)結構之焊接區域。因此,縮減了所得封裝之厚度。
根據本發明之一些實施例,一種封裝包括一第一裝置晶粒,及一第一封裝材料,其將該第一裝置晶粒封裝於其中。該第一裝置晶粒之一底部表面與該第一封裝材料之一底部表面共面。第一介電層下伏於該第一裝置晶粒。第一重佈線在該等第一介電層中且電耦接至該第一裝置晶粒。第二介電層上覆於該第一裝置晶粒。第二重佈線在該等第二介電層中且電耦接至該等第一重佈線。一第二裝置晶粒上覆於且電耦接至該等第二重佈線。無焊接區域將該第二裝置晶粒連接至該等
第二重佈線。一第二封裝材料將該第二裝置晶粒封裝於其中。一第三裝置晶粒電耦接至該等第二重佈線。一第三封裝材料將該第三裝置晶粒封裝於其中。
根據本發明之一些實施例,一種方法包括將一第一裝置晶粒置放於一載體上方、將該第一裝置晶粒封裝於一第一封裝材料中、執行一第一平坦化以顯露該第一裝置晶粒中之第一金屬柱、形成第一介電層於該第一裝置晶粒及該第一封裝材料上方,及形成第一重佈線於該等第一介電層中。該等第一重佈線電耦接至該等第一金屬柱。該方法進一步包括將一第二裝置晶粒黏著至該等第一介電層之一頂部表面、形成一第一貫通通孔於該等第一介電層上方、將該第二裝置晶粒及該第一貫通通孔封裝於一第二封裝材料中、執行一第二平坦化以顯露該第一貫通通孔及該第二裝置晶粒中之第二金屬柱、形成第二介電層於該第二裝置晶粒上方,及形成第二重佈線於該等第二介電層中。該等第二重佈線電耦接至該等第二金屬柱及該第一貫通通孔。
根據本發明之一些實施例,一種方法包括將一第一裝置晶粒置放於一載體上方。該第一裝置晶粒包括一第一半導體基板,及穿過該第一半導體基板之第一貫通通孔。該方法進一步包括將該第一裝置晶粒封裝於一第一封裝材料中、形成第一介電層於該第一裝置晶粒上方,及形成第一重佈線於該等第一介電層中。該等第一重佈線電耦接至該第一裝置晶粒中之第一金屬柱。將一第二裝置晶粒黏著至該等第一介電層之一頂部表面。形成第二貫通通孔於該等第一介電層上方。該等第二貫通通孔電耦接至該等第一重佈線。該方法進一步包括將該第二裝置晶粒封裝於一第二封裝材料中、形成第二介電層於該第二裝置晶粒上方,及形成第二重佈線於該等第二介電層中。該等第二重佈線電耦接至該第二裝置晶粒中之第二金屬柱。使該載體與該第一裝置晶粒脫結。對該半導體基板執行一背面研磨以顯露該等第一貫通通
孔。形成第三重佈線以電耦接至該等第一貫通通孔。
前述內容概述若干實施例之特徵,使得熟習此項技術者可較好地理解本發明之態樣。熟習此項技術者應瞭解,其可容易使用本發明作為用於設計或修改用於實行本文中所引入之實施例之相同目的及/或達成本文中所引入之實施例之相同優點的其他程序及結構之基礎。熟習此項技術者亦應認識到,此等等效構造並不脫離本發明之精神及範疇,且其可在不脫離本發明之精神及範疇的情況下在本文中進行各種改變、取代及更改。
32‧‧‧貫通通孔
34‧‧‧裝置晶粒
36‧‧‧半導體基板
40‧‧‧積體電路裝置/主動及被動裝置/積體電路
42‧‧‧貫通通孔
43‧‧‧重佈線(RDL)
44‧‧‧金屬柱
46‧‧‧介電層
48‧‧‧封裝材料
50‧‧‧介電層
52‧‧‧重佈線(RDL)
56‧‧‧貫通通孔
58‧‧‧裝置晶粒
60‧‧‧晶粒附接膜
62‧‧‧金屬柱
64‧‧‧表面介電層
66‧‧‧封裝材料
68‧‧‧介電層
70‧‧‧重佈線(RDL)
72‧‧‧凸塊下金屬層(UBM)
74‧‧‧電連接器
76‧‧‧晶圓層級封裝/主要封裝/下伏封裝
82‧‧‧PoP封裝
86‧‧‧底填充料
88‧‧‧封裝
90‧‧‧封裝材料
200‧‧‧上覆封裝/次要封裝
202‧‧‧封裝基板
234‧‧‧裝置晶粒
Claims (10)
- 一種封裝,其包含:一第一裝置晶粒;一第一封裝材料,其將該第一裝置晶粒封裝於其中,其中該第一裝置晶粒之一底部表面與該第一封裝材料之一底部表面共面;第一介電層,其下伏於該第一裝置晶粒;第一重佈線,其在該等第一介電層中且電耦接至該第一裝置晶粒;第二介電層,其上覆於該第一裝置晶粒;第二重佈線,其在該等第二介電層中且電耦接至該等第一重佈線;一第二裝置晶粒,其上覆於且電耦接至該等第二重佈線,其中無焊接區域將該第二裝置晶粒連接至該等第二重佈線;一第二封裝材料,其將該第二裝置晶粒封裝於其中;一第三裝置晶粒,其電耦接至該等第二重佈線;及一第三封裝材料,其將該第三裝置晶粒封裝於其中。
- 如請求項1之封裝,其中該第三裝置晶粒上覆於該第二裝置晶粒,且無焊接區域在該第三裝置晶粒與該等第一重佈線之間。
- 如請求項1之封裝,其中該第三裝置晶粒上覆於該第二裝置晶粒,且該封裝進一步包含將該第三裝置晶粒電耦接至該等第二重佈線之焊接區域。
- 如請求項1之封裝,其進一步包含穿過該第二封裝材料之一貫通通孔,其中該貫通通孔將該第三裝置晶粒電耦接至該等第二重佈線。
- 如請求項1之封裝,其中該第二裝置晶粒包含:一半導體基板;及穿過該半導體基板之貫通通孔,其中該等貫通通孔將該等第二重佈線電耦接至該第三裝置晶粒。
- 如請求項5之封裝,其中該等貫通通孔與該第二裝置晶粒中之全部主動及被動裝置電解耦。
- 如請求項6之封裝,其中無貫通通孔穿過該第二封裝材料。
- 如請求項1之封裝,其中該等第一介電層、該等第二介電層、該第一封裝材料及該第二封裝材料之各別邊緣彼此對準。
- 一種方法,其包含:將一第一裝置晶粒置放於一載體上方;將該第一裝置晶粒封裝於一第一封裝材料中;執行一第一平坦化以顯露該第一裝置晶粒中之第一金屬柱;形成第一介電層於該第一裝置晶粒及該第一封裝材料上方;形成第一重佈線於該等第一介電層中,其中該等第一重佈線電耦接至該等第一金屬柱;將一第二裝置晶粒黏著至該等第一介電層之一頂部表面;形成一第一貫通通孔於該等第一介電層上方;將該第二裝置晶粒及該第一貫通通孔封裝於一第二封裝材料中;執行一第二平坦化以顯露該第一貫通通孔及該第二裝置晶粒中之第二金屬柱;形成第二介電層於該第二裝置晶粒上方;及形成第二重佈線於該等第二介電層中,其中該等第二重佈線電耦接至該等第二金屬柱及該第一貫通通孔。
- 一種方法,其包含: 將一第一裝置晶粒置放於一載體上方,其中該第一裝置晶粒包含:一第一半導體基板;及穿過該第一半導體基板之第一貫通通孔;將該第一裝置晶粒封裝於一第一封裝材料中;形成第一介電層於該第一裝置晶粒上方;形成第一重佈線於該等第一介電層中,其中該等第一重佈線電耦接至該第一裝置晶粒中之第一金屬柱;將一第二裝置晶粒黏著至該等第一介電層之一頂部表面;形成第二貫通通孔於該等第一介電層上方,其中該等第二貫通通孔電耦接至該等第一重佈線;將該第二裝置晶粒封裝於一第二封裝材料中;形成第二介電層於該第二裝置晶粒上方;形成第二重佈線於該等第二介電層中,其中該等第二重佈線電耦接至該第二裝置晶粒中之第二金屬柱;使該載體與該第一裝置晶粒脫結;對該第一半導體基板執行一背面研磨以顯露該等第一貫通通孔;及形成第三重佈線以電耦接至該等第一貫通通孔。
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US10784248B2 (en) | 2020-09-22 |
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US9735131B2 (en) | 2017-08-15 |
US11462530B2 (en) | 2022-10-04 |
TWI670777B (zh) | 2019-09-01 |
DE102016015805B3 (de) | 2021-06-17 |
CN106684048B (zh) | 2019-10-22 |
US20170133351A1 (en) | 2017-05-11 |
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